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prjxray/minitests/litex/src.yosys
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Maciej Kurc 3783e7b2e3 Fixed the LiteX generated SoC to be Linux capable 
Signed-off-by: Maciej Kurc <mkurc@antmicro.com>
 		2019-06-17 13:45:11 +02:00
..
Makefile Changed Vivado invocation 2019-06-14 09:40:21 +02:00
VexRiscv_Linux.v Fixed the LiteX generated SoC to be Linux capable 2019-06-17 13:45:11 +02:00
mem.init Added LiteX SoC project (VexRiscV + DRAM + Ethernet for Arty board) 2019-06-13 15:58:06 +02:00
mem_1.init Added LiteX SoC project (VexRiscV + DRAM + Ethernet for Arty board) 2019-06-13 15:58:06 +02:00
synth.ys Fixed the LiteX generated SoC to be Linux capable 2019-06-17 13:45:11 +02:00
top.tcl Fixed the LiteX generated SoC to be Linux capable 2019-06-17 13:45:11 +02:00
top.v Fixed the LiteX generated SoC to be Linux capable 2019-06-17 13:45:11 +02:00
top.xdc Added LiteX SoC project (VexRiscV + DRAM + Ethernet for Arty board) 2019-06-13 15:58:06 +02:00