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prjxray/minitests/litex
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Keith Rothman 2c7b64ea22 Create script for generating remaining bit report. 
This report is fairly fragile, but works well enough for the remaining
LiteX bits.

Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com>
 		2019-07-26 15:04:29 -07:00
..
src.vivado Added source files dependencies to Makefiles 2019-06-25 10:14:20 +02:00
src.yosys Create script for generating remaining bit report. 2019-07-26 15:04:29 -07:00
.gitignore Added LiteX SoC project (VexRiscV + DRAM + Ethernet for Arty board) 2019-06-13 15:58:06 +02:00
README.md Fixed the LiteX generated SoC to be Linux capable 2019-06-17 13:45:11 +02:00

README.md

LiteX minitest

This folder contains a minitest for a Linux capable LiteX SoC for Arty board.

There are two variants: for Vivado only flow and for Yosys+Vivado flow. In order to run one of them enter the specific directory and run make.

The SoC "gateware" files were generated using the command:

./arty.py --cpu-type vexriscv --cpu-variant linux --with-ethernet --no-compile-software --no-compile-gateware