History

Alessandro Comodi ab759c7b84 minitest: add/fix gitignore Signed-off-by: Alessandro Comodi <acomodi@antmicro.com>		2021-01-29 19:16:42 +01:00
..
tcl	minitest: litex: litesata: fix Makefile and build process	2021-01-22 13:42:02 +01:00
.gitignore	minitest: add/fix gitignore	2021-01-29 19:16:42 +01:00
Makefile	minitest: litex: litesata: download riscv-gcc as well in Makefile	2021-01-22 16:52:20 +01:00
README.md	minitest: fix litex packages versions	2021-01-29 19:16:42 +01:00
requirements.txt	minitest: fix litex packages versions	2021-01-29 19:16:42 +01:00
retarget.v	minitest: add lite-sata minitest to verify GTP status	2021-01-22 10:19:29 +01:00

LiteSATA minitest

This minitest is intended to provide a counter-prove on the possible remaining features to document for the Gigabit Transcievers (GTP tiles).

It uses the following litex modules:

Repo URL	SHA
https://github.com/enjoy-digital/litex	7abfbd9
https://github.com/enjoy-digital/litedram	ab2423e
https://github.com/enjoy-digital/liteeth	7448170
https://github.com/enjoy-digital/liteiclink	0980a7c
https://github.com/enjoy-digital/litesata	fae9f8d
https://github.com/enjoy-digital/litex-boards	1d8f0a9
https://github.com/m-labs/migen	40b1092
https://github.com/nmigen/nmigen	490fca5
https://github.com/litex-hub/pythondata-cpu-vexriscv	16c5dde

The minitest synthesis step can be performed with Yosys or Vivado.

The final FASM file with the unknown bits can be obtained by running the following:

make all

All the pre-requisites (LiteX, Yosys, etc.) are automatically installed/built. It is required though to have Vivado installed in the system.