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prjxray
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14 Commits

Author SHA1 Message Date
Keith Rothman 6c4e6aa718 Update HCLK_IOI offset to match tilegrid 
Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com>
 2019-07-26 17:18:48 -07:00
Keith Rothman 2c7b64ea22 Create script for generating remaining bit report. 
This report is fairly fragile, but works well enough for the remaining
LiteX bits.

Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com>
 2019-07-26 15:04:29 -07:00
Keith Rothman fa2f61f914 Run make format. 
Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com>
 2019-07-23 17:21:26 -07:00
Keith Rothman a7ba547acb Filter out non-IOB bits. 
Also add output from LiteX to verify IOB FASM features.

Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com>
 2019-07-23 13:38:03 -07:00
Maciej Kurc 68c810ce3b Added source files dependencies to Makefiles 
Signed-off-by: Maciej Kurc <mkurc@antmicro.com>
 2019-06-25 10:14:20 +02:00
Maciej Kurc 64a05b4fa2 Changed makefiles to use XRAY_DIR 
Signed-off-by: Maciej Kurc <mkurc@antmicro.com>
 2019-06-19 09:19:28 +02:00
Maciej Kurc bf1c7d3183 Fixed invication of prjxray scripts in Makefiles 
Signed-off-by: Maciej Kurc <mkurc@antmicro.com>
 2019-06-18 13:00:23 +02:00
Maciej Kurc 728a6a76d2 Added bitread and segprint to the Makefile flow 
Signed-off-by: Maciej Kurc <mkurc@antmicro.com>
 2019-06-17 14:52:06 +02:00
Maciej Kurc 3783e7b2e3 Fixed the LiteX generated SoC to be Linux capable 
Signed-off-by: Maciej Kurc <mkurc@antmicro.com>
 2019-06-17 13:45:11 +02:00
Maciej Kurc 4798c08ad8 Changed Vivado invocation 
Signed-off-by: Maciej Kurc <mkurc@antmicro.com>
 2019-06-14 09:40:21 +02:00
Maciej Kurc 4f459cfde3 Ran format-tcl 
Signed-off-by: Maciej Kurc <mkurc@antmicro.com>
 2019-06-13 16:39:49 +02:00
Maciej Kurc 421af109b1 Added bit2fasm targets to Makefiles 
Signed-off-by: Maciej Kurc <mkurc@antmicro.com>
 2019-06-13 16:29:20 +02:00
Maciej Kurc 0c244f242d Added submodule with Yosys and integrated it with the LiteX minitest 
Signed-off-by: Maciej Kurc <mkurc@antmicro.com>
 2019-06-13 16:16:11 +02:00
Maciej Kurc 01f77fd2b2 Added LiteX SoC project (VexRiscV + DRAM + Ethernet for Arty board) 
Signed-off-by: Maciej Kurc <mkurc@antmicro.com>
 2019-06-13 15:58:06 +02:00