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prjxray
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950 Commits

Author SHA1 Message Date
Karol Gugala bb9bc7bfdd fuzzers: 007: refactor aliased pins detection 
Signed-off-by: Karol Gugala <kgugala@antmicro.com>
 2019-06-18 18:30:48 +02:00
Karol Gugala 26614e5ed4 fuzzers: 007: restore missing continue 
Signed-off-by: Karol Gugala <kgugala@antmicro.com>
 2019-06-18 18:30:48 +02:00
Karol Gugala c9d661d161 fuzzers: 007: run make format 
Signed-off-by: Karol Gugala <kgugala@antmicro.com>
 2019-06-18 18:30:48 +02:00
Karol Gugala 73979fdf04 fuzzers: 007: handle pin/pin and pin/prop aliases 
Signed-off-by: Karol Gugala <kgugala@antmicro.com>
 2019-06-18 18:30:48 +02:00
Karol Gugala b122f07896 fuzzers: 007: do not emit clk -> clk timing checks 
Signed-off-by: Karol Gugala <kgugala@antmicro.com>
 2019-06-18 18:30:48 +02:00
Karol Gugala 209240e77f fuzzers: 007: handle output vector pins 
Signed-off-by: Karol Gugala <kgugala@antmicro.com>
 2019-06-18 18:30:48 +02:00
Karol Gugala cdcb759299 fuzzers: 007: remove commented code 
Signed-off-by: Karol Gugala <kgugala@antmicro.com>
 2019-06-18 18:30:48 +02:00
Karol Gugala 83657adbb9 fuzzers: 007: fix clock inputs inferring 
Signed-off-by: Karol Gugala <kgugala@antmicro.com>
 2019-06-18 18:30:48 +02:00
Karol Gugala ecb4fa1289 fuzzers: 007: use timings fixup 
Signed-off-by: Karol Gugala <kgugala@antmicro.com>
 2019-06-18 18:30:48 +02:00
Karol Gugala 91e7f3910e fuzzers: 007: add timings_fixup script 
Signed-off-by: Karol Gugala <kgugala@antmicro.com>
 2019-06-18 18:30:48 +02:00
Maciej Kurc 8366e324af Code refactoring. 
Signed-off-by: Maciej Kurc <mkurc@antmicro.com>
 2019-06-18 18:30:48 +02:00
Maciej Kurc d05945ff81 Added support for aliases of pins with underscore in names. Added doctests 
Signed-off-by: Maciej Kurc <mkurc@antmicro.com>
 2019-06-18 18:30:48 +02:00
Maciej Kurc 58898bb29f Removed explicit bel suffix map. 
Signed-off-by: Maciej Kurc <mkurc@antmicro.com>
 2019-06-18 18:30:48 +02:00
Maciej Kurc 6e1efd4815 Fixed formatting 
Signed-off-by: Maciej Kurc <mkurc@antmicro.com>
 2019-06-18 18:30:48 +02:00
Maciej Kurc 4a117330f2 Fixed fuzzer 007 so it can correctly extract SR -> Q timings in FF_INIT and REG_INIT_FF 
Signed-off-by: Maciej Kurc <mkurc@antmicro.com>
 2019-06-18 18:30:48 +02:00
litghost e984015c45
Merge pull request #888 from antmicro/874_pip_seed 
050-pip-seed: Don't solve BYP_ALT|IMUX.LOGIC_OUTS_ bits
 2019-06-18 09:28:29 -07:00
litghost 1097bdb58b
Merge pull request #869 from antmicro/todo_balancing 
Implement todo lists balancing mechanism
 2019-06-17 10:01:20 -07:00
Tomasz Michalak f28cf75d5c 050-pip-seed: Don't solve BYP_ALT|IMUX.LOGIC_OUTS_ bits 
Signed-off-by: Tomasz Michalak <tmichalak@antmicro.com>
 2019-06-17 14:55:18 +02:00
Karol Gugala 278d2dba2c fuzzers: 007: do not emit sdfs for sites with no timings 
Signed-off-by: Karol Gugala <kgugala@antmicro.com>
 2019-06-13 13:32:43 +02:00
Tomasz Michalak 0fee08e577 Add generic todo list balancing mechanism 
Signed-off-by: Tomasz Michalak <tmichalak@antmicro.com>
 2019-06-12 14:26:52 +02:00
Tim Ansell bb8640bda9
Merge pull request #880 from litghost/add_back_hclk_ppips 
Add HCLK ppips.
 2019-06-12 09:29:18 +02:00
litghost d31319ccaa
Merge pull request #879 from litghost/avoid_full_dict_build 
Avoid building full speed_model dict.
 2019-06-11 14:59:41 -07:00
Keith Rothman aeaa8a3530 Add HCLK ppips. 
These were no longer generated after 946892d1b and were removed from
prjxray-db at
b13ff7f8b3 (diff-6a43cc2ab2e06b2a84b7effc16ca669e)

Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com>
 2019-06-11 14:58:15 -07:00
Keith Rothman 2ad76619ee Avoid building full speed_model dict. 
Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com>
 2019-06-11 10:32:24 -07:00
Tomasz Michalak 6fb68593ff 059-pip-byp-bounce: Add separate fuzzer for FAN_ALT.BYP_BOUNCE bits 
Signed-off-by: Tomasz Michalak <tmichalak@antmicro.com>
 2019-06-05 19:26:07 +02:00
Tomasz Michalak 14efe4d720 050-pip-seed: Don't solve FAN_ALT.BYP_BOUNCE bits 
Signed-off-by: Tomasz Michalak <tmichalak@antmicro.com>
 2019-06-05 08:24:11 +02:00
litghost 71970f9b38
Merge pull request #849 from antmicro/prjxray_stabilization_053_pip_ctrlin 
053-pip-ctrlin: Fall back to todos bigger than specified number of lines
 2019-06-04 09:35:53 -07:00
Tomasz Michalak 369362f8c8 005-tilegrid: add CFG_CENTER_MID tile base address calculation 
Signed-off-by: Tomasz Michalak <tmichalak@antmicro.com>
 2019-05-31 09:40:40 +02:00
litghost 0bddcaf908
Merge pull request #858 from litghost/timing_fuzzer 
Add wire, pip, and site pin timing information.
 2019-05-30 18:20:43 -07:00
litghost 84e168c9dc
Merge pull request #831 from antmicro/prjxray_stabilization_057_pip_bi 
057-pip-bi: Increase number of tries to find a suitable PIP INT tile
 2019-05-30 12:17:02 -07:00
Keith Rothman 0dc1317389 Add comment on magic. 
Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com>
 2019-05-30 09:18:47 -07:00
Keith Rothman e1208e1014 Add wire, pip, and site pin timing information. 
This is required for interconnect timing modelling.

Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com>
 2019-05-29 14:51:35 -07:00
Tomasz Michalak ebf8d6a1cd 053-pip-ctrlin: Fall back to todos bigger than specified number of lines 
Signed-off-by: Tomasz Michalak <tmichalak@antmicro.com>
 2019-05-29 08:35:08 +02:00
litghost e8299f6404
Merge pull request #842 from antmicro/bits_origin 
Generate db files with fuzzer name of origin
 2019-05-28 09:57:08 -07:00
Tomasz Michalak 22cdae1536 Generate db files with fuzzer name of origin 
Signed-off-by: Tomasz Michalak <tmichalak@antmicro.com>
 2019-05-27 08:46:44 +02:00
Tim Ansell ff4c80738d
Merge pull request #850 from antmicro/fuzzer_007_python3 
Make build scripts of 007 explicitly use python3
 2019-05-25 15:21:03 -07:00
Maciej Kurc 306b40eebb Changed all scripts to use explicitly python3 
Signed-off-by: Maciej Kurc <mkurc@antmicro.com>
 2019-05-24 15:05:53 +02:00
Tomasz Michalak 86057f3d17 018-clb-ram: Increase specimen count 
Signed-off-by: Tomasz Michalak <tmichalak@antmicro.com>
 2019-05-24 08:05:41 +02:00
Tomasz Michalak efb0b14b3a 057-pip-bi: Increase try count limit 
Signed-off-by: Tomasz Michalak <tmichalak@antmicro.com>
 2019-05-24 08:02:58 +02:00
Tomasz Michalak 11f5a37a06 050-pip-seed: Increase specimen count 
Signed-off-by: Tomasz Michalak <tmichalak@antmicro.com>
 2019-05-23 20:49:14 +02:00
Tomasz Michalak 58baff4f4a fuzzers: Add clean_piplists target 
Signed-off-by: Tomasz Michalak <tmichalak@antmicro.com>
 2019-05-23 15:19:16 +02:00
Karol Gugala 683b7562e5 fuzzer: 007: bel: handle multiple bit inputs 
Signed-off-by: Karol Gugala <kgugala@antmicro.com>
 2019-05-16 19:14:35 +02:00
Karol Gugala e1440a56b4 fuzzers: 007: add properties names mappings 
Signed-off-by: Karol Gugala <kgugala@antmicro.com>
 2019-05-16 14:52:58 +02:00
Karol Gugala 788e3e0855 fuzzers: 007: correctly handle input clocks and extended pin names 
Signed-off-by: Karol Gugala <kgugala@antmicro.com>
 2019-05-14 17:34:07 -07:00
Tomasz Michalak e7ce84abbe
Merge pull request #822 from antmicro/prjxray_stabilization_045_hclk_cmt_pips 
045-hclk-cmt-pips: account for hclk_cmt tiles missing from zynq7 and …
 2019-05-14 11:52:47 +02:00
Tomasz Michalak c4e062fa6e 053-pip-ctrlin: increase specimen count 
Signed-off-by: Tomasz Michalak <tmichalak@antmicro.com>
 2019-05-13 22:25:43 +02:00
Tomasz Michalak fe809d7d0d 045-hclk-cmt-pips: increase specimen count 
Signed-off-by: Tomasz Michalak <tmichalak@antmicro.com>
 2019-05-13 10:17:35 +02:00
Tomasz Michalak 7e05327c97 056-pip-rem: Delete net and cell after unsuccessful routing attempt 
Signed-off-by: Tomasz Michalak <tmichalak@antmicro.com>
 2019-05-10 11:14:10 +02:00
Tomasz Michalak b5a4e6932e run_fuzzer.py: Adjust unit names output by free tool 
Signed-off-by: Tomasz Michalak <tmichalak@antmicro.com>
 2019-05-09 09:33:22 +02:00
Tim 'mithro' Ansell fbec529926 Less verbose memory usage info. 
Signed-off-by: Tim 'mithro' Ansell <me@mith.ro>
 2019-05-08 10:09:45 +02:00