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Tweaked some glossary terms. 

Signed-off-by: Sarah Maddox <sarahmaddox@google.com>
This commit is contained in:
Sarah Maddox 2018-05-14 14:34:46 +10:00
parent 62f0ca316e
commit fc37897c35
1 changed files with 3 additions and 3 deletions
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docs/architecture/glossary.rst
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@ -33,7 +33,7 @@ Glossary
programming sequences and other commands required to load and activate same.
Block RAM
Block RAM is inbuilt, configurable memory on the FPGA chip, able to store
Block RAM is inbuilt, configurable memory on an :term:`FPGA`, able to store
more data than the :term:`flip flops <ff>`. The block RAM can function as
dual or single-port memory. Xilinx 7 series devices offer a number of 36 Kb
block RAMs, each with two independently controlled 18 Kb RAMs. The number of
@ -45,7 +45,7 @@ Glossary
Clock
A clock is a square-wave timing signal (50% on, 50% off) generated by an
external oscillator and passed into the FPGA. The clock frequency
external oscillator and passed into the :term:`FPGA`. The clock frequency
drives the sequential logic elements in the FPGA, most importantly
the :term:`flip flops <ff>`. For example, the FPGA may use a
50 megahertz clock. An FGPA can use one or more clocks and can thus have
@ -89,7 +89,7 @@ Glossary
Fabric sub region
FSR
See :term:`clock region`.
Another name for :term:`clock region`.
Flip flop
FF