From fc37897c3519be8a47616b733112a945a02a000a Mon Sep 17 00:00:00 2001 From: Sarah Maddox Date: Mon, 14 May 2018 14:34:46 +1000 Subject: [PATCH] Tweaked some glossary terms. Signed-off-by: Sarah Maddox --- docs/architecture/glossary.rst | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/docs/architecture/glossary.rst b/docs/architecture/glossary.rst index d6541c7a..24b8839f 100644 --- a/docs/architecture/glossary.rst +++ b/docs/architecture/glossary.rst @@ -33,7 +33,7 @@ Glossary programming sequences and other commands required to load and activate same. Block RAM - Block RAM is inbuilt, configurable memory on the FPGA chip, able to store + Block RAM is inbuilt, configurable memory on an :term:`FPGA`, able to store more data than the :term:`flip flops `. The block RAM can function as dual or single-port memory. Xilinx 7 series devices offer a number of 36 Kb block RAMs, each with two independently controlled 18 Kb RAMs. The number of @@ -45,7 +45,7 @@ Glossary Clock A clock is a square-wave timing signal (50% on, 50% off) generated by an - external oscillator and passed into the FPGA. The clock frequency + external oscillator and passed into the :term:`FPGA`. The clock frequency drives the sequential logic elements in the FPGA, most importantly the :term:`flip flops `. For example, the FPGA may use a 50 megahertz clock. An FGPA can use one or more clocks and can thus have @@ -89,7 +89,7 @@ Glossary Fabric sub region FSR - See :term:`clock region`. + Another name for :term:`clock region`. Flip flop FF