Added some glossary terms.

Signed-off-by: Sarah Maddox <sarahmaddox@google.com>

docs/architecture/configuration.rst

@@ -76,9 +76,9 @@ will have 36 frames.
 Block RAM content
 ^^^^^^^^^^^^^^^^^
 
-As the name says, this bus provides access to the Block RAM contents. Block RAM configuration
-data is accessed via the CLB, I/O, CLB bus. The mapping of frame words to memory locations is
-not currently understood.
+As the name says, this bus provides access to the :term:`block RAM` contents.
+Block RAM configuration data is accessed via the CLB, I/O, CLB bus. The mapping
+of frame words to memory locations is not currently understood.
 
 CFG_CLB
 ^^^^^^^

docs/architecture/glossary.rst

@@ -31,15 +31,44 @@ Glossary
     Binary data that is directly loaded into an :term:`FPGA` to perform
     configuration. Contains configuration :term:`frames <frame>` as well as
     programming sequences and other commands required to load and activate same.
+    
+  Block RAM
+    Block RAM is inbuilt, configurable memory on the FPGA chip, able to store
+    more data than the :term:`flip flops <ff>`. The block RAM can function as
+    dual or single-port memory. Xilinx 7 series devices offer a number of 36 Kb
+    block RAMs, each with two independently controlled 18 Kb RAMs. The number of
+    block RAMs available depends on the specific device.
 
   CFA
     A carry or fast adder (CFA) is a logic element on the :term:`FPGA` that
     performs fast arithmetic operations.
+    
+  Clock
+    A clock is a square-wave timing signal (50% on, 50% off) generated by an
+    external oscillator and passed into the FPGA. The clock frequency
+    drives the sequential logic elements in the FPGA, most importantly
+    the :term:`flip flops <ff>`. For example, the FPGA may use a
+    50 megahertz clock. An FGPA can use one or more clocks and can thus have
+    one or more :term:`clock domains <clock domain>`.
+
+  Clock backbone
+  Clock spine
+    In Xilinx 7 series devices, the clock backbone or clock spine divides the
+    :term:`clock regions <clock region>` on the device into two sides, the left
+    and the right side.
 
   Clock domain
-    Portion of a :term:`horizontal clock row` to one side of the global clock
-    spine. Often refers to :term:`tiles <tile>` that are associated with these
-    clocks.
+    Portion of the device controlled by one :term:`clock`. A clock domain is
+    part of a :term:`horizontal clock row` to one side of the global
+    :term:`clock spine`. The term also often refers to the
+    :term:`tiles <tile>` that are associated with these clocks.
+    
+  Clock region
+    Portion of a device including up to 12 :term:`clock domains <clock domain>`.
+    A clock region is situated to the left or right of the global clock spine,
+    and is 50 :term:`CLBs <clb>` tall on Xilinx 7 series devices. The clock
+    region includes all synchronous elements in the 50 CLBs and one I/O bank,
+    with a :term:`horizontal clock row` at its center.
 
   Column
     A term used in :term:`bitstream` configuration to denote
@@ -48,8 +77,8 @@ Glossary
     Logic columns span 50 tiles vertically and 2 tiles horizontally
     (pairs of logic tiles and interconnect tiles).
 
-  CLB
   Configurable logic block
+  CLB
     A configurable logic block (CLB) is the configurable logic unit of an
     :term:`FPGA`. Also called a **logic cell**. A CLB is a combination of basic
     logic elements (:term:`BELs <bel>`).
@@ -58,8 +87,12 @@ Glossary
     Text files containing meaningful labels for bit positions within
     :term:`segments <segment>`.
 
-  FF
+  Fabric sub region
+  FSR
+    See :term:`clock region`.
+    
   Flip flop
+  FF
     A flip flop (FF) is a logic element on the :term:`FPGA` that stores state.
 
   FPGA
@@ -94,20 +127,21 @@ Glossary
     and then convert the data from those specimens into a :term:`database`.
 
   Half
-    Portion of a device defined by a virtual line dividing the two sets of global
-    clock buffers present in a device. The two halves are referred to as
-    the top and bottom halves.
+    Portion of a device defined by a virtual line dividing the two sets of
+    global :term:`clock` buffers present in a device. The two halves are
+    referred to as the top and bottom halves.
 
   HDL
     You use a hardware definition language (HDL) to describe the behavior of an
     electronic circuit. Popular HDLs include Verilog (inspired by C) and VHDL
     (inspired by Ada).
-
+    
   Horizontal clock row
-    Portion of a device including 12 horizontal clocks and the 50 interconnect
-    and function tiles associated with them. A :term:`half` contains one or
-    more horizontal clock rows and each half may have a different number of
-    rows.
+  HROW
+    Portion of a device including 12 horizontal :term:`clocks <clock>` and the
+    50 interconnect and function tiles associated with them. A :term:`half`
+    contains one or more horizontal clock rows and each half may have a
+    different number of rows.
 
   I/O block
     One of the configurable input/output blocks that connect the :term:`FPGA`
@@ -139,8 +173,8 @@ Glossary
     hardware logic elements on the :term:`FPGA`, and then routing the signals
     between the placed elements. 
 
-  ROI
   Region of interest
+  ROI
     Region of interest (ROI) is used in *Project X-Ray* to denote a
     rectangular region on the :term:`FPGA` that is the focus of our study.
     The current region of interest is `SLICE_X12Y100:SLICE_X27Y149`
@@ -164,6 +198,9 @@ Glossary
     Portion of a :term:`tile` that contains :term:`BELs <bel>`.
     A `CLBLL_L/CLBLL_R` tile contains two `SLICEL` slices.
     A `CLBLM_L/CLBLM_R` tile contains one `SLICEL` slice and one `SLICEM` slice.
+    `SLICEL` and `SLICEM` are the most common types of slice, containing the
+    :term:`LUTs <lut>` and :term:`flip flops <ff>` that are the basic logic
+    units of the FPGA.
 
   Specimen
     A :term:`bitstream` of a (usually auto-generated) design with additional
@@ -174,7 +211,7 @@ Glossary
   Tile
     Fundamental unit of physical structure containing a single type of
     resource or function. A container for :term:`sites <site>` and
-    :term:`slices <slice>`. The whole chip is a grid of tiles.
+    :term:`slices <slice>`. The FPGA chip is a grid of tiles.
 
     The most important tile types are left and right interconnect tiles
     (`INT_L` and `INT_R`) and left and right :term:`CLB` logic/memory tiles