mirror of https://github.com/openXC7/prjxray.git
104 lines
3.9 KiB
Python
Executable File
104 lines
3.9 KiB
Python
Executable File
#!/usr/bin/env python3
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# This file is Copyright (c) 2015-2020 Florent Kermarrec <florent@enjoy-digital.fr>
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# License: BSD
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import argparse
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from migen import *
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from litex_boards.platforms import arty
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from litex.build.xilinx import VivadoProgrammer
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from litex.build.xilinx.vivado import vivado_build_args, vivado_build_argdict
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from litex.soc.cores.clock import *
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from litex.soc.integration.soc_sdram import *
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from litex.soc.integration.builder import *
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from litedram.init import get_sdram_phy_py_header
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from litedram.modules import MT41K128M16
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from litedram.phy import s7ddrphy
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# CRG ----------------------------------------------------------------------------------------------
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class _CRG(Module):
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def __init__(self, platform, sys_clk_freq):
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self.clock_domains.cd_sys = ClockDomain()
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self.clock_domains.cd_sys4x = ClockDomain(reset_less=True)
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self.clock_domains.cd_sys4x_dqs = ClockDomain(reset_less=True)
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self.clock_domains.cd_clk200 = ClockDomain()
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# # #
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self.submodules.pll = pll = S7PLL(speedgrade=-1)
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self.comb += pll.reset.eq(~platform.request("cpu_reset"))
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pll.register_clkin(platform.request("clk100"), 100e6)
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pll.create_clkout(self.cd_sys, sys_clk_freq)
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pll.create_clkout(self.cd_sys4x, 4*sys_clk_freq)
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pll.create_clkout(self.cd_sys4x_dqs, 4*sys_clk_freq, phase=90)
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pll.create_clkout(self.cd_clk200, 200e6)
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self.submodules.idelayctrl = S7IDELAYCTRL(self.cd_clk200)
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# BaseSoC ------------------------------------------------------------------------------------------
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class BaseSoC(SoCSDRAM):
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def __init__(self):
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platform = arty.Platform()
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sys_clk_freq = int(50e6)
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# SoCSDRAM ---------------------------------------------------------------------------------
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SoCSDRAM.__init__(self, platform, clk_freq=sys_clk_freq,
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ident = "Minimal Arty DDR3 Design for tests with Project X-Ray", ident_version=True,
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cpu_type = None,
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l2_size = 16,
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uart_name = "bridge")
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# CRG --------------------------------------------------------------------------------------
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self.submodules.crg = _CRG(platform, sys_clk_freq)
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# DDR3 SDRAM -------------------------------------------------------------------------------
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if not self.integrated_main_ram_size:
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self.submodules.ddrphy = s7ddrphy.A7DDRPHY(platform.request("ddram"),
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memtype = "DDR3",
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nphases = 4,
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sys_clk_freq = sys_clk_freq)
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self.add_csr("ddrphy")
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sdram_module = MT41K128M16(sys_clk_freq, "1:4")
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self.register_sdram(self.ddrphy,
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geom_settings = sdram_module.geom_settings,
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timing_settings = sdram_module.timing_settings)
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def generate_sdram_phy_py_header(self):
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f = open("sdram_init.py", "w")
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f.write(get_sdram_phy_py_header(
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self.sdram.controller.settings.phy,
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self.sdram.controller.settings.timing))
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f.close()
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# Load ---------------------------------------------------------------------------------------------
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def load():
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prog = VivadoProgrammer()
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prog.load_bitstream("build/gateware/top.bit")
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# Build --------------------------------------------------------------------------------------------
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def main():
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parser = argparse.ArgumentParser(description="Minimal Arty DDR3 Design for tests with Project X-Ray")
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parser.add_argument("--build", action="store_true", help="Build bitstream")
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parser.add_argument("--load", action="store_true", help="Load bitstream")
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args = parser.parse_args()
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if args.load:
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load()
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soc = BaseSoC()
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builder = Builder(soc, output_dir="build", csr_csv="csr.csv")
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builder.build(run=args.build)
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soc.generate_sdram_phy_py_header()
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if __name__ == "__main__":
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main()
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