Added fuzzing for chained ISERDES

Signed-off-by: Maciej Kurc <mkurc@antmicro.com>

fuzzers/035b-iob-iserdes/generate.py

@@ -19,19 +19,22 @@ data_rates = ["SDR", "DDR"]
 data_widths = [2, 3, 4, 5, 6, 7, 8, 10, 14]
 
 # Output tags
-loc_to_tile_site_map = {}
+#loc_to_tile_site_map = {}
-for params in data:
+for param_list in data:
-    loc = verilog.unquote(params["_LOC"])
+    for params in param_list:
+        loc = verilog.unquote(params["SITE_LOC"])
         loc = loc.replace("ILOGIC", "IOB")
 
         get_xy = util.create_xy_fun('IOB_')
         x, y = get_xy(loc)
 
-    loc_to_tile_site_map[loc] = params["TILE"] + ".IOB_X0Y%d" % (y % 2)
+        #loc_to_tile_site_map[loc] = params["TILE"] + ".IOB_X0Y%d" % (y % 2)
 
         # Serdes not used at all
         if not params["IS_USED"]:
 
+            segmk.add_site_tag(loc, "ISERDES.SHIFTOUT_USED", 0)
+            
             segmk.add_site_tag(loc, "ISERDES.IN_USE", 0)
 
             segmk.add_site_tag(loc, "ISERDES.MODE.MASTER", 0)
@@ -73,6 +76,11 @@ for params in data:
 
             segmk.add_site_tag(loc, "ISERDES.IN_USE", 1)
 
+            if "SHIFTOUT_USED" in params:
+                if params["CHAINED"]:
+                    value = params["SHIFTOUT_USED"]                
+                    segmk.add_site_tag(loc, "ISERDES.SHIFTOUT_USED", value)
+
             if "SERDES_MODE" in params:
                 value = verilog.unquote(params["SERDES_MODE"])
                 if value == "MASTER":
@@ -116,6 +124,7 @@ for params in data:
                         loc, "IFF.ZSRVAL_Q%d" % i, not params["SRVAL_Q%d" % i])
 
             if "IS_D_INVERTED" in params:
+                if not params["CHAINED"]:
                     segmk.add_site_tag(
                         loc, "ZINV_D", int(params["IS_D_INVERTED"] == 0))
 
@@ -163,17 +172,17 @@ for params in data:
                     segmk.add_site_tag(loc, "ISERDES.OFB_USED", 1)
 
 # Write segments and tags for later check
-with open("tags.json", "w") as fp:
+#with open("tags.json", "w") as fp:
-    tags = {
+#    tags = {
-        loc_to_tile_site_map[l]: {k: int(v)
+#        loc_to_tile_site_map[l]: {k: int(v)
-                                  for k, v in d.items()}
+#                                  for k, v in d.items()}
-        for l, d in segmk.site_tags.items()
+#        for l, d in segmk.site_tags.items()
-    }
+#    }
-    json.dump(tags, fp, sort_keys=True, indent=1)
+#    json.dump(tags, fp, sort_keys=True, indent=1)
 
 
 def bitfilter(frame_idx, bit_idx):
-    if frame_idx < 25 or frame_idx > 31:
+    if frame_idx < 26 or frame_idx > 31:
         return False
     return True
 

fuzzers/035b-iob-iserdes/generate.tcl

@@ -1,5 +1,3 @@
-set_param general.maxThreads 1
-
 create_project -force -part $::env(XRAY_PART) design design
 read_verilog top.v
 synth_design -top top
@@ -10,6 +8,7 @@ set_property BITSTREAM.GENERAL.PERFRAMECRC YES [current_design]
 set_param tcl.collectionResultDisplayLimit 0
 
 set_property IS_ENABLED 0 [get_drc_checks {NSTD-1}]
+set_property IS_ENABLED 0 [get_drc_checks {NDRV-1}]
 set_property IS_ENABLED 0 [get_drc_checks {UCIO-1}]
 set_property IS_ENABLED 0 [get_drc_checks {REQP-98}]
 set_property IS_ENABLED 0 [get_drc_checks {REQP-109}]

fuzzers/035b-iob-iserdes/top.py

@@ -47,50 +47,12 @@ def gen_sites():
 
         yield iob_tile_name, iob33m, ilogic_m, iob33s, ilogic_s
 
-
+def gen_iserdes(loc):
-def run():
-
-    # Get all [LR]IOI3 tiles
-    tiles = list(gen_sites())
-
-    # Header
-    print("// Tile count: %d" % len(tiles))
-    print("// Seed: '%s'" % os.getenv("SEED"))
-    print(
-        '''
-module top (
-  (* CLOCK_BUFFER_TYPE = "NONE" *)
-  input  wire clk1,
-  (* CLOCK_BUFFER_TYPE = "NONE" *)
-  input  wire clk2,
-  input  wire [{N}:0] di,
-  output wire [{N}:0] do
-);
-
-wire [{N}:0] di_buf;
-wire [{N}:0] do_buf;
-    '''.format(**{"N": len(tiles) - 1}))
-
-    # LOCes IOBs
-    data = []
-    for i, sites in enumerate(tiles):
-        tile_name = sites[0]
-
-        # Bottom site
-        if random.randint(0, 1):
-            iob_i = sites[1]
-            iob_o = sites[3]
-            ilogic = sites[2]
-        # Top site
-        else:
-            iob_i = sites[3]
-            iob_o = sites[1]
-            ilogic = sites[4]
 
     # Site params
     params = {
-            "_LOC":
+        "SITE_LOC":
-            verilog.quote(ilogic),
+        verilog.quote(loc),
         "IS_USED":
         int(random.randint(0, 10) > 0),  # Make it used more often
         "INIT_Q1":
@@ -159,20 +121,116 @@ wire [{N}:0] do_buf;
     if verilog.unquote(params["OFB_USED"]) == "TRUE":
         params["IOBDELAY"] = verilog.quote("NONE")
 
-        # Instantiate cell
+    return params
-        param_str = ",".join(".%s(%s)" % (k, v) for k, v in params.items())
 
+
+def run():
+
+    # Get all [LR]IOI3 tiles
+    tiles = list(gen_sites())
+
+    # Header
+    print("// Tile count: %d" % len(tiles))
+    print("// Seed: '%s'" % os.getenv("SEED"))
+    print(
+        '''
+module top (
+  (* CLOCK_BUFFER_TYPE = "NONE" *)
+  input  wire clk1,
+  (* CLOCK_BUFFER_TYPE = "NONE" *)
+  input  wire clk2,
+  input  wire [{N}:0] di,
+  output wire [{N}:0] do
+);
+
+wire [{N}:0] di_buf;
+wire [{N}:0] do_buf;
+    '''.format(**{"N": len(tiles) - 1}))
+
+    # LOCes IOBs
+    data = []
+    for i, sites in enumerate(tiles):
+        tile_name = sites[0]
+
+        # Single ISERDES
+        if random.randint(0, 5) >= 1:
+
+            # Bottom site
+            if random.randint(0, 1):
+                iob_i = sites[1]
+                iob_o = sites[3]
+                ilogic = sites[2]
+            # Top site
+            else:
+                iob_i = sites[3]
+                iob_o = sites[1]
+                ilogic = sites[4]
+
+            # Generate cell
+            params = gen_iserdes(ilogic)
+
+            # Instantiate the cell
             print('')
             print('(* LOC="%s", KEEP, DONT_TOUCH *)' % iob_i)
             print('IBUF ibuf_%03d (.I(di[%3d]), .O(di_buf[%3d]));' % (i, i, i))
             print('(* LOC="%s", KEEP, DONT_TOUCH *)' % iob_o)
             print('OBUF obuf_%03d (.I(do_buf[%3d]), .O(do[%3d]));' % (i, i, i))
-        print(
-            'iserdes_single #(%s) iserdes_%03d (.clk1(clk1), .clk2(clk2), .I(di_buf[%3d]), .O(do_buf[%3d]));'
-            % (param_str, i, i, i))
 
-        params["TILE"] = tile_name
+            param_str = ",".join(".%s(%s)" % (k, v) for k, v in params.items())
-        data.append(params)
+            print('iserdes_single #(%s) iserdes_%03d (.clk1(clk1), .clk2(clk2), .I(di_buf[%3d]), .O(do_buf[%3d]));' % (param_str, i, i, i))
+
+            params["CHAINED"] = 0
+
+            data.append([params])
+
+        # Dual ISERDES chained
+        else:
+
+            iob_i = sites[1]
+            iob_o = sites[3]
+            ilogic = [sites[2], sites[4]]
+        
+            # Generate cells
+            params_m = gen_iserdes(ilogic[0])
+            params_s = gen_iserdes(ilogic[1])
+
+            # Force relevant parameters
+            params_m["SERDES_MODE"] = verilog.quote("MASTER")
+            params_m["IS_USED"] = 1
+
+            params_m["INTERFACE_TYPE"] = verilog.quote("NETWORKING")
+            params_m["DATA_RATE"] = verilog.quote("DDR")
+            params_m["DATA_WIDTH"] = random.choice([10, 14])
+
+            params_s["SERDES_MODE"] = verilog.quote("SLAVE")
+            params_s["IS_USED"] = 1
+
+            params_s["INTERFACE_TYPE"] = params_m["INTERFACE_TYPE"]
+            params_s["DATA_RATE"] = params_m["DATA_RATE"]
+            params_s["DATA_WIDTH"] = params_m["DATA_WIDTH"]
+
+            # Instantiate cells
+            print('')
+            print('(* LOC="%s", KEEP, DONT_TOUCH *)' % iob_i)
+            print('IBUF ibuf_%03d (.I(di[%3d]), .O(di_buf[%3d]));' % (i, i, i))
+            print('(* LOC="%s", KEEP, DONT_TOUCH *)' % iob_o)
+            print('OBUF obuf_%03d (.I(do_buf[%3d]), .O(do[%3d]));' % (i, i, i))
+
+            print('wire o_%03d_m;' % i)
+            print('wire o_%03d_s;' % i)
+            print('wire [1:0] sh_%03d;' % i)
+            print('assign do_buf[%3d] = |q_%03d_m || |q_%03d_s;' % (i, i, i))
+            param_str = ",".join(".%s(%s)" % (k, v) for k, v in params_m.items())
+            print('iserdes_single #(%s) iserdes_%03d_m (.clk1(clk1), .clk2(clk2), .I(di_buf[%3d]), .O(q_%03d_m), .shiftout(sh_%03d));' % (param_str, i, i, i, i))
+            param_str = ",".join(".%s(%s)" % (k, v) for k, v in params_s.items())
+            print('iserdes_single #(%s) iserdes_%03d_s (.clk1(clk1), .clk2(clk2), .O(q_%03d_s), .shiftin(sh_%03d));' % (param_str, i, i,  i))
+
+            params_m["SHIFTOUT_USED"] = 1
+
+            params_m["CHAINED"] = 1
+            params_s["CHAINED"] = 1
+
+            data.append([params_m, params_s])
 
     # Store params
     with open("params.json", "w") as fp:
@@ -187,10 +245,12 @@ module iserdes_single(
   input  wire clk1,
   input  wire clk2,
   input  wire I,
-  output wire O
+  output wire O,
+  input  wire [1:0] shiftin,
+  output wire [1:0] shiftout
 );
 
-parameter _LOC = "";
+parameter SITE_LOC = "";
 parameter IS_USED = 1;
 parameter INTERFACE_TYPE = "NETWORKING";
 parameter DATA_RATE = "DDR";
@@ -217,13 +277,13 @@ parameter DYN_CLK_INV_EN = "FALSE";
 parameter IOBDELAY = "NONE";
 parameter OFB_USED = "FALSE";
 
-(* KEEP, DONT_TOUCH *)
 wire [7:0] x;
 
+(* KEEP, DONT_TOUCH *)
 generate if (IS_USED) begin
 
-  // Single ISERDES
+  // ISERDES
-  (* LOC=_LOC, KEEP, DONT_TOUCH *)
+  (* LOC=SITE_LOC, KEEP, DONT_TOUCH *)
   ISERDESE2 #
   (
   .INTERFACE_TYPE(INTERFACE_TYPE),
@@ -277,8 +337,10 @@ generate if (IS_USED) begin
   .Q6(x[5]),
   .Q7(x[6]),
   .Q8(x[7]),
-  .SHIFTOUT1(),
+  .SHIFTIN1(shiftin[0]),
-  .SHIFTOUT2()
+  .SHIFTIN2(shiftin[1]),
+  .SHIFTOUT1(shiftout[0]),
+  .SHIFTOUT2(shiftout[1])
   );
 
 end else begin
@@ -298,6 +360,7 @@ end endgenerate
 assign O = |x;
 
 endmodule
+
     ''')