From ea0fd9eb8ef0a5d1aa0cff03301d498e412ca1f3 Mon Sep 17 00:00:00 2001 From: Maciej Kurc Date: Mon, 22 Jul 2019 15:57:00 +0200 Subject: [PATCH] Added fuzzing for chained ISERDES Signed-off-by: Maciej Kurc --- fuzzers/035b-iob-iserdes/generate.py | 271 +++++++++++++------------- fuzzers/035b-iob-iserdes/generate.tcl | 3 +- fuzzers/035b-iob-iserdes/top.py | 249 ++++++++++++++--------- 3 files changed, 297 insertions(+), 226 deletions(-) diff --git a/fuzzers/035b-iob-iserdes/generate.py b/fuzzers/035b-iob-iserdes/generate.py index 25da34a9..70bb8b66 100644 --- a/fuzzers/035b-iob-iserdes/generate.py +++ b/fuzzers/035b-iob-iserdes/generate.py @@ -19,161 +19,170 @@ data_rates = ["SDR", "DDR"] data_widths = [2, 3, 4, 5, 6, 7, 8, 10, 14] # Output tags -loc_to_tile_site_map = {} -for params in data: - loc = verilog.unquote(params["_LOC"]) - loc = loc.replace("ILOGIC", "IOB") +#loc_to_tile_site_map = {} +for param_list in data: + for params in param_list: + loc = verilog.unquote(params["SITE_LOC"]) + loc = loc.replace("ILOGIC", "IOB") - get_xy = util.create_xy_fun('IOB_') - x, y = get_xy(loc) + get_xy = util.create_xy_fun('IOB_') + x, y = get_xy(loc) - loc_to_tile_site_map[loc] = params["TILE"] + ".IOB_X0Y%d" % (y % 2) + #loc_to_tile_site_map[loc] = params["TILE"] + ".IOB_X0Y%d" % (y % 2) - # Serdes not used at all - if not params["IS_USED"]: + # Serdes not used at all + if not params["IS_USED"]: - segmk.add_site_tag(loc, "ISERDES.IN_USE", 0) + segmk.add_site_tag(loc, "ISERDES.SHIFTOUT_USED", 0) + + segmk.add_site_tag(loc, "ISERDES.IN_USE", 0) - segmk.add_site_tag(loc, "ISERDES.MODE.MASTER", 0) - segmk.add_site_tag(loc, "ISERDES.MODE.SLAVE", 0) + segmk.add_site_tag(loc, "ISERDES.MODE.MASTER", 0) + segmk.add_site_tag(loc, "ISERDES.MODE.SLAVE", 0) - for i in iface_types: - if i == "NETWORKING": + for i in iface_types: + if i == "NETWORKING": + for j in data_rates: + for k in data_widths: + tag = "ISERDES.%s.%s.%s" % (i, j, k) + segmk.add_site_tag(loc, tag, 0) + else: + for j in data_rates: + segmk.add_site_tag(loc, "ISERDES.%s.%s.4" % (i, j), 0) + + segmk.add_site_tag(loc, "ISERDES.NUM_CE.1", 0) + segmk.add_site_tag(loc, "ISERDES.NUM_CE.2", 0) + + for i in range(1, 4 + 1): + segmk.add_site_tag(loc, "IFF.ZINIT_Q%d" % i, 0) + + for i in range(1, 4 + 1): + segmk.add_site_tag(loc, "IFF.ZSRVAL_Q%d" % i, 0) + + segmk.add_site_tag(loc, "ZINV_D", 0) + + segmk.add_site_tag(loc, "ISERDES.DYN_CLKDIV_INV_EN", 0) + segmk.add_site_tag(loc, "ISERDES.DYN_CLK_INV_EN", 0) + + segmk.add_site_tag(loc, "IFFDELMUXE3.0", 1) + segmk.add_site_tag(loc, "IFFDELMUXE3.1", 0) + segmk.add_site_tag(loc, "IDELMUXE3.0", 1) + segmk.add_site_tag(loc, "IDELMUXE3.1", 0) + + segmk.add_site_tag(loc, "ISERDES.OFB_USED", 0) + + # Serdes used + else: + + segmk.add_site_tag(loc, "ISERDES.IN_USE", 1) + + if "SHIFTOUT_USED" in params: + if params["CHAINED"]: + value = params["SHIFTOUT_USED"] + segmk.add_site_tag(loc, "ISERDES.SHIFTOUT_USED", value) + + if "SERDES_MODE" in params: + value = verilog.unquote(params["SERDES_MODE"]) + if value == "MASTER": + segmk.add_site_tag(loc, "ISERDES.MODE.MASTER", 1) + segmk.add_site_tag(loc, "ISERDES.MODE.SLAVE", 0) + if value == "SLAVE": + segmk.add_site_tag(loc, "ISERDES.MODE.MASTER", 0) + segmk.add_site_tag(loc, "ISERDES.MODE.SLAVE", 1) + + iface_type = verilog.unquote(params["INTERFACE_TYPE"]) + data_rate = verilog.unquote(params["DATA_RATE"]) + data_width = int(params["DATA_WIDTH"]) + + for i in iface_types: for j in data_rates: for k in data_widths: tag = "ISERDES.%s.%s.%s" % (i, j, k) - segmk.add_site_tag(loc, tag, 0) - else: - for j in data_rates: - segmk.add_site_tag(loc, "ISERDES.%s.%s.4" % (i, j), 0) - segmk.add_site_tag(loc, "ISERDES.NUM_CE.1", 0) - segmk.add_site_tag(loc, "ISERDES.NUM_CE.2", 0) + if i == iface_type: + if j == data_rate: + if k == data_width: + segmk.add_site_tag(loc, tag, 1) - for i in range(1, 4 + 1): - segmk.add_site_tag(loc, "IFF.ZINIT_Q%d" % i, 0) + if "NUM_CE" in params: + value = params["NUM_CE"] + if value == 1: + segmk.add_site_tag(loc, "ISERDES.NUM_CE.1", 1) + segmk.add_site_tag(loc, "ISERDES.NUM_CE.2", 0) + if value == 2: + segmk.add_site_tag(loc, "ISERDES.NUM_CE.1", 0) + segmk.add_site_tag(loc, "ISERDES.NUM_CE.2", 1) - for i in range(1, 4 + 1): - segmk.add_site_tag(loc, "IFF.ZSRVAL_Q%d" % i, 0) + for i in range(1, 4 + 1): + if ("INIT_Q%d" % i) in params: + segmk.add_site_tag( + loc, "IFF.ZINIT_Q%d" % i, not params["INIT_Q%d" % i]) - segmk.add_site_tag(loc, "ZINV_D", 0) + for i in range(1, 4 + 1): + if ("SRVAL_Q%d" % i) in params: + segmk.add_site_tag( + loc, "IFF.ZSRVAL_Q%d" % i, not params["SRVAL_Q%d" % i]) - segmk.add_site_tag(loc, "ISERDES.DYN_CLKDIV_INV_EN", 0) - segmk.add_site_tag(loc, "ISERDES.DYN_CLK_INV_EN", 0) + if "IS_D_INVERTED" in params: + if not params["CHAINED"]: + segmk.add_site_tag( + loc, "ZINV_D", int(params["IS_D_INVERTED"] == 0)) - segmk.add_site_tag(loc, "IFFDELMUXE3.0", 1) - segmk.add_site_tag(loc, "IFFDELMUXE3.1", 0) - segmk.add_site_tag(loc, "IDELMUXE3.0", 1) - segmk.add_site_tag(loc, "IDELMUXE3.1", 0) - - segmk.add_site_tag(loc, "ISERDES.OFB_USED", 0) - - # Serdes used - else: - - segmk.add_site_tag(loc, "ISERDES.IN_USE", 1) - - if "SERDES_MODE" in params: - value = verilog.unquote(params["SERDES_MODE"]) - if value == "MASTER": - segmk.add_site_tag(loc, "ISERDES.MODE.MASTER", 1) - segmk.add_site_tag(loc, "ISERDES.MODE.SLAVE", 0) - if value == "SLAVE": - segmk.add_site_tag(loc, "ISERDES.MODE.MASTER", 0) - segmk.add_site_tag(loc, "ISERDES.MODE.SLAVE", 1) - - iface_type = verilog.unquote(params["INTERFACE_TYPE"]) - data_rate = verilog.unquote(params["DATA_RATE"]) - data_width = int(params["DATA_WIDTH"]) - - for i in iface_types: - for j in data_rates: - for k in data_widths: - tag = "ISERDES.%s.%s.%s" % (i, j, k) - - if i == iface_type: - if j == data_rate: - if k == data_width: - segmk.add_site_tag(loc, tag, 1) - - if "NUM_CE" in params: - value = params["NUM_CE"] - if value == 1: - segmk.add_site_tag(loc, "ISERDES.NUM_CE.1", 1) - segmk.add_site_tag(loc, "ISERDES.NUM_CE.2", 0) - if value == 2: - segmk.add_site_tag(loc, "ISERDES.NUM_CE.1", 0) - segmk.add_site_tag(loc, "ISERDES.NUM_CE.2", 1) - - for i in range(1, 4 + 1): - if ("INIT_Q%d" % i) in params: + if "DYN_CLKDIV_INV_EN" in params: + value = verilog.unquote(params["DYN_CLKDIV_INV_EN"]) segmk.add_site_tag( - loc, "IFF.ZINIT_Q%d" % i, not params["INIT_Q%d" % i]) - - for i in range(1, 4 + 1): - if ("SRVAL_Q%d" % i) in params: + loc, "ISERDES.DYN_CLKDIV_INV_EN", int(value == "TRUE")) + if "DYN_CLK_INV_EN" in params: + value = verilog.unquote(params["DYN_CLK_INV_EN"]) segmk.add_site_tag( - loc, "IFF.ZSRVAL_Q%d" % i, not params["SRVAL_Q%d" % i]) + loc, "ISERDES.DYN_CLK_INV_EN", int(value == "TRUE")) - if "IS_D_INVERTED" in params: - segmk.add_site_tag( - loc, "ZINV_D", int(params["IS_D_INVERTED"] == 0)) + # This parameter actually controls muxes used both in ILOGIC and + # ISERDES mode. + if "IOBDELAY" in params: + value = verilog.unquote(params["IOBDELAY"]) + if value == "NONE": + #segmk.add_site_tag(loc, "IOBDELAY_NONE", 1) + segmk.add_site_tag(loc, "IFFDELMUXE3.0", 0) + segmk.add_site_tag(loc, "IFFDELMUXE3.1", 1) + segmk.add_site_tag(loc, "IDELMUXE3.0", 0) + segmk.add_site_tag(loc, "IDELMUXE3.1", 1) + if value == "IBUF": + #segmk.add_site_tag(loc, "IOBDELAY_IBUF", 1) + segmk.add_site_tag(loc, "IFFDELMUXE3.0", 0) + segmk.add_site_tag(loc, "IFFDELMUXE3.1", 1) + segmk.add_site_tag(loc, "IDELMUXE3.0", 1) + segmk.add_site_tag(loc, "IDELMUXE3.1", 0) + if value == "IFD": + #segmk.add_site_tag(loc, "IOBDELAY_IFD" , 1) + segmk.add_site_tag(loc, "IFFDELMUXE3.0", 1) + segmk.add_site_tag(loc, "IFFDELMUXE3.1", 0) + segmk.add_site_tag(loc, "IDELMUXE3.0", 0) + segmk.add_site_tag(loc, "IDELMUXE3.1", 1) + if value == "BOTH": + #segmk.add_site_tag(loc, "IOBDELAY_BOTH", 1) + segmk.add_site_tag(loc, "IFFDELMUXE3.0", 1) + segmk.add_site_tag(loc, "IFFDELMUXE3.1", 0) + segmk.add_site_tag(loc, "IDELMUXE3.0", 1) + segmk.add_site_tag(loc, "IDELMUXE3.1", 0) - if "DYN_CLKDIV_INV_EN" in params: - value = verilog.unquote(params["DYN_CLKDIV_INV_EN"]) - segmk.add_site_tag( - loc, "ISERDES.DYN_CLKDIV_INV_EN", int(value == "TRUE")) - if "DYN_CLK_INV_EN" in params: - value = verilog.unquote(params["DYN_CLK_INV_EN"]) - segmk.add_site_tag( - loc, "ISERDES.DYN_CLK_INV_EN", int(value == "TRUE")) - - # This parameter actually controls muxes used both in ILOGIC and - # ISERDES mode. - if "IOBDELAY" in params: - value = verilog.unquote(params["IOBDELAY"]) - if value == "NONE": - #segmk.add_site_tag(loc, "IOBDELAY_NONE", 1) - segmk.add_site_tag(loc, "IFFDELMUXE3.0", 0) - segmk.add_site_tag(loc, "IFFDELMUXE3.1", 1) - segmk.add_site_tag(loc, "IDELMUXE3.0", 0) - segmk.add_site_tag(loc, "IDELMUXE3.1", 1) - if value == "IBUF": - #segmk.add_site_tag(loc, "IOBDELAY_IBUF", 1) - segmk.add_site_tag(loc, "IFFDELMUXE3.0", 0) - segmk.add_site_tag(loc, "IFFDELMUXE3.1", 1) - segmk.add_site_tag(loc, "IDELMUXE3.0", 1) - segmk.add_site_tag(loc, "IDELMUXE3.1", 0) - if value == "IFD": - #segmk.add_site_tag(loc, "IOBDELAY_IFD" , 1) - segmk.add_site_tag(loc, "IFFDELMUXE3.0", 1) - segmk.add_site_tag(loc, "IFFDELMUXE3.1", 0) - segmk.add_site_tag(loc, "IDELMUXE3.0", 0) - segmk.add_site_tag(loc, "IDELMUXE3.1", 1) - if value == "BOTH": - #segmk.add_site_tag(loc, "IOBDELAY_BOTH", 1) - segmk.add_site_tag(loc, "IFFDELMUXE3.0", 1) - segmk.add_site_tag(loc, "IFFDELMUXE3.1", 0) - segmk.add_site_tag(loc, "IDELMUXE3.0", 1) - segmk.add_site_tag(loc, "IDELMUXE3.1", 0) - - if "OFB_USED" in params: - value = verilog.unquote(params["OFB_USED"]) - if value == "TRUE": - segmk.add_site_tag(loc, "ISERDES.OFB_USED", 1) + if "OFB_USED" in params: + value = verilog.unquote(params["OFB_USED"]) + if value == "TRUE": + segmk.add_site_tag(loc, "ISERDES.OFB_USED", 1) # Write segments and tags for later check -with open("tags.json", "w") as fp: - tags = { - loc_to_tile_site_map[l]: {k: int(v) - for k, v in d.items()} - for l, d in segmk.site_tags.items() - } - json.dump(tags, fp, sort_keys=True, indent=1) +#with open("tags.json", "w") as fp: +# tags = { +# loc_to_tile_site_map[l]: {k: int(v) +# for k, v in d.items()} +# for l, d in segmk.site_tags.items() +# } +# json.dump(tags, fp, sort_keys=True, indent=1) def bitfilter(frame_idx, bit_idx): - if frame_idx < 25 or frame_idx > 31: + if frame_idx < 26 or frame_idx > 31: return False return True diff --git a/fuzzers/035b-iob-iserdes/generate.tcl b/fuzzers/035b-iob-iserdes/generate.tcl index 8ba63a89..1ee1c316 100644 --- a/fuzzers/035b-iob-iserdes/generate.tcl +++ b/fuzzers/035b-iob-iserdes/generate.tcl @@ -1,5 +1,3 @@ -set_param general.maxThreads 1 - create_project -force -part $::env(XRAY_PART) design design read_verilog top.v synth_design -top top @@ -10,6 +8,7 @@ set_property BITSTREAM.GENERAL.PERFRAMECRC YES [current_design] set_param tcl.collectionResultDisplayLimit 0 set_property IS_ENABLED 0 [get_drc_checks {NSTD-1}] +set_property IS_ENABLED 0 [get_drc_checks {NDRV-1}] set_property IS_ENABLED 0 [get_drc_checks {UCIO-1}] set_property IS_ENABLED 0 [get_drc_checks {REQP-98}] set_property IS_ENABLED 0 [get_drc_checks {REQP-109}] diff --git a/fuzzers/035b-iob-iserdes/top.py b/fuzzers/035b-iob-iserdes/top.py index 8edee1d6..d5472593 100644 --- a/fuzzers/035b-iob-iserdes/top.py +++ b/fuzzers/035b-iob-iserdes/top.py @@ -47,6 +47,82 @@ def gen_sites(): yield iob_tile_name, iob33m, ilogic_m, iob33s, ilogic_s +def gen_iserdes(loc): + + # Site params + params = { + "SITE_LOC": + verilog.quote(loc), + "IS_USED": + int(random.randint(0, 10) > 0), # Make it used more often + "INIT_Q1": + random.randint(0, 1), + "INIT_Q2": + random.randint(0, 1), + "INIT_Q3": + random.randint(0, 1), + "INIT_Q4": + random.randint(0, 1), + "SRVAL_Q1": + random.randint(0, 1), + "SRVAL_Q2": + random.randint(0, 1), + "SRVAL_Q3": + random.randint(0, 1), + "SRVAL_Q4": + random.randint(0, 1), + "NUM_CE": + random.randint(1, 2), + # The following one shows negative correlation (0 - not inverted) + "IS_D_INVERTED": + random.randint(0, 1), + # No bits were found for parameters below + #"IS_OCLKB_INVERTED": random.randint(0, 1), + #"IS_OCLK_INVERTED": random.randint(0, 1), + #"IS_CLKDIVP_INVERTED": random.randint(0, 1), + #"IS_CLKDIV_INVERTED": random.randint(0, 1), + #"IS_CLKB_INVERTED": random.randint(0, 1), + #"IS_CLK_INVERTED": random.randint(0, 1), + "DYN_CLKDIV_INV_EN": + verilog.quote(random.choice(["TRUE", "FALSE"])), + "DYN_CLK_INV_EN": + verilog.quote(random.choice(["TRUE", "FALSE"])), + "IOBDELAY": + verilog.quote(random.choice(["NONE", "IBUF", "IFD", "BOTH"])), + "OFB_USED": + verilog.quote( + random.choice(["TRUE"] + ["FALSE"] * 9)), # Force more FALSEs + } + + iface_type = random.choice( + [ + "NETWORKING", "OVERSAMPLE", "MEMORY", "MEMORY_DDR3", + "MEMORY_QDR" + ]) + data_rate = random.choice(["SDR", "DDR"]) + serdes_mode = random.choice(["MASTER", "SLAVE"]) + + params["INTERFACE_TYPE"] = verilog.quote(iface_type) + params["DATA_RATE"] = verilog.quote(data_rate) + params["SERDES_MODE"] = verilog.quote(serdes_mode) + + # Networking mode + if iface_type == "NETWORKING": + data_widths = { + "SDR": [2, 3, 4, 5, 6, 7, 8], + "DDR": [4, 6, 8, 10, 14], + } + params["DATA_WIDTH"] = random.choice(data_widths[data_rate]) + + # Others + else: + params["DATA_WIDTH"] = 4 + + if verilog.unquote(params["OFB_USED"]) == "TRUE": + params["IOBDELAY"] = verilog.quote("NONE") + + return params + def run(): @@ -76,103 +152,85 @@ wire [{N}:0] do_buf; for i, sites in enumerate(tiles): tile_name = sites[0] - # Bottom site - if random.randint(0, 1): + # Single ISERDES + if random.randint(0, 5) >= 1: + + # Bottom site + if random.randint(0, 1): + iob_i = sites[1] + iob_o = sites[3] + ilogic = sites[2] + # Top site + else: + iob_i = sites[3] + iob_o = sites[1] + ilogic = sites[4] + + # Generate cell + params = gen_iserdes(ilogic) + + # Instantiate the cell + print('') + print('(* LOC="%s", KEEP, DONT_TOUCH *)' % iob_i) + print('IBUF ibuf_%03d (.I(di[%3d]), .O(di_buf[%3d]));' % (i, i, i)) + print('(* LOC="%s", KEEP, DONT_TOUCH *)' % iob_o) + print('OBUF obuf_%03d (.I(do_buf[%3d]), .O(do[%3d]));' % (i, i, i)) + + param_str = ",".join(".%s(%s)" % (k, v) for k, v in params.items()) + print('iserdes_single #(%s) iserdes_%03d (.clk1(clk1), .clk2(clk2), .I(di_buf[%3d]), .O(do_buf[%3d]));' % (param_str, i, i, i)) + + params["CHAINED"] = 0 + + data.append([params]) + + # Dual ISERDES chained + else: + iob_i = sites[1] iob_o = sites[3] - ilogic = sites[2] - # Top site - else: - iob_i = sites[3] - iob_o = sites[1] - ilogic = sites[4] + ilogic = [sites[2], sites[4]] + + # Generate cells + params_m = gen_iserdes(ilogic[0]) + params_s = gen_iserdes(ilogic[1]) - # Site params - params = { - "_LOC": - verilog.quote(ilogic), - "IS_USED": - int(random.randint(0, 10) > 0), # Make it used more often - "INIT_Q1": - random.randint(0, 1), - "INIT_Q2": - random.randint(0, 1), - "INIT_Q3": - random.randint(0, 1), - "INIT_Q4": - random.randint(0, 1), - "SRVAL_Q1": - random.randint(0, 1), - "SRVAL_Q2": - random.randint(0, 1), - "SRVAL_Q3": - random.randint(0, 1), - "SRVAL_Q4": - random.randint(0, 1), - "NUM_CE": - random.randint(1, 2), - # The following one shows negative correlation (0 - not inverted) - "IS_D_INVERTED": - random.randint(0, 1), - # No bits were found for parameters below - #"IS_OCLKB_INVERTED": random.randint(0, 1), - #"IS_OCLK_INVERTED": random.randint(0, 1), - #"IS_CLKDIVP_INVERTED": random.randint(0, 1), - #"IS_CLKDIV_INVERTED": random.randint(0, 1), - #"IS_CLKB_INVERTED": random.randint(0, 1), - #"IS_CLK_INVERTED": random.randint(0, 1), - "DYN_CLKDIV_INV_EN": - verilog.quote(random.choice(["TRUE", "FALSE"])), - "DYN_CLK_INV_EN": - verilog.quote(random.choice(["TRUE", "FALSE"])), - "IOBDELAY": - verilog.quote(random.choice(["NONE", "IBUF", "IFD", "BOTH"])), - "OFB_USED": - verilog.quote( - random.choice(["TRUE"] + ["FALSE"] * 9)), # Force more FALSEs - } + # Force relevant parameters + params_m["SERDES_MODE"] = verilog.quote("MASTER") + params_m["IS_USED"] = 1 - iface_type = random.choice( - [ - "NETWORKING", "OVERSAMPLE", "MEMORY", "MEMORY_DDR3", - "MEMORY_QDR" - ]) - data_rate = random.choice(["SDR", "DDR"]) - serdes_mode = random.choice(["MASTER", "SLAVE"]) + params_m["INTERFACE_TYPE"] = verilog.quote("NETWORKING") + params_m["DATA_RATE"] = verilog.quote("DDR") + params_m["DATA_WIDTH"] = random.choice([10, 14]) - params["INTERFACE_TYPE"] = verilog.quote(iface_type) - params["DATA_RATE"] = verilog.quote(data_rate) - params["SERDES_MODE"] = verilog.quote(serdes_mode) + params_s["SERDES_MODE"] = verilog.quote("SLAVE") + params_s["IS_USED"] = 1 - # Networking mode - if iface_type == "NETWORKING": - data_widths = { - "SDR": [2, 3, 4, 5, 6, 7, 8], - "DDR": [4, 6, 8, 10, 14], - } - params["DATA_WIDTH"] = random.choice(data_widths[data_rate]) + params_s["INTERFACE_TYPE"] = params_m["INTERFACE_TYPE"] + params_s["DATA_RATE"] = params_m["DATA_RATE"] + params_s["DATA_WIDTH"] = params_m["DATA_WIDTH"] - # Others - else: - params["DATA_WIDTH"] = 4 + # Instantiate cells + print('') + print('(* LOC="%s", KEEP, DONT_TOUCH *)' % iob_i) + print('IBUF ibuf_%03d (.I(di[%3d]), .O(di_buf[%3d]));' % (i, i, i)) + print('(* LOC="%s", KEEP, DONT_TOUCH *)' % iob_o) + print('OBUF obuf_%03d (.I(do_buf[%3d]), .O(do[%3d]));' % (i, i, i)) - if verilog.unquote(params["OFB_USED"]) == "TRUE": - params["IOBDELAY"] = verilog.quote("NONE") + print('wire o_%03d_m;' % i) + print('wire o_%03d_s;' % i) + print('wire [1:0] sh_%03d;' % i) + print('assign do_buf[%3d] = |q_%03d_m || |q_%03d_s;' % (i, i, i)) + param_str = ",".join(".%s(%s)" % (k, v) for k, v in params_m.items()) + print('iserdes_single #(%s) iserdes_%03d_m (.clk1(clk1), .clk2(clk2), .I(di_buf[%3d]), .O(q_%03d_m), .shiftout(sh_%03d));' % (param_str, i, i, i, i)) + param_str = ",".join(".%s(%s)" % (k, v) for k, v in params_s.items()) + print('iserdes_single #(%s) iserdes_%03d_s (.clk1(clk1), .clk2(clk2), .O(q_%03d_s), .shiftin(sh_%03d));' % (param_str, i, i, i)) - # Instantiate cell - param_str = ",".join(".%s(%s)" % (k, v) for k, v in params.items()) + params_m["SHIFTOUT_USED"] = 1 - print('') - print('(* LOC="%s", KEEP, DONT_TOUCH *)' % iob_i) - print('IBUF ibuf_%03d (.I(di[%3d]), .O(di_buf[%3d]));' % (i, i, i)) - print('(* LOC="%s", KEEP, DONT_TOUCH *)' % iob_o) - print('OBUF obuf_%03d (.I(do_buf[%3d]), .O(do[%3d]));' % (i, i, i)) - print( - 'iserdes_single #(%s) iserdes_%03d (.clk1(clk1), .clk2(clk2), .I(di_buf[%3d]), .O(do_buf[%3d]));' - % (param_str, i, i, i)) + params_m["CHAINED"] = 1 + params_s["CHAINED"] = 1 - params["TILE"] = tile_name - data.append(params) + data.append([params_m, params_s]) # Store params with open("params.json", "w") as fp: @@ -187,10 +245,12 @@ module iserdes_single( input wire clk1, input wire clk2, input wire I, - output wire O + output wire O, + input wire [1:0] shiftin, + output wire [1:0] shiftout ); -parameter _LOC = ""; +parameter SITE_LOC = ""; parameter IS_USED = 1; parameter INTERFACE_TYPE = "NETWORKING"; parameter DATA_RATE = "DDR"; @@ -217,13 +277,13 @@ parameter DYN_CLK_INV_EN = "FALSE"; parameter IOBDELAY = "NONE"; parameter OFB_USED = "FALSE"; -(* KEEP, DONT_TOUCH *) wire [7:0] x; +(* KEEP, DONT_TOUCH *) generate if (IS_USED) begin - // Single ISERDES - (* LOC=_LOC, KEEP, DONT_TOUCH *) + // ISERDES + (* LOC=SITE_LOC, KEEP, DONT_TOUCH *) ISERDESE2 # ( .INTERFACE_TYPE(INTERFACE_TYPE), @@ -277,8 +337,10 @@ generate if (IS_USED) begin .Q6(x[5]), .Q7(x[6]), .Q8(x[7]), - .SHIFTOUT1(), - .SHIFTOUT2() + .SHIFTIN1(shiftin[0]), + .SHIFTIN2(shiftin[1]), + .SHIFTOUT1(shiftout[0]), + .SHIFTOUT2(shiftout[1]) ); end else begin @@ -298,6 +360,7 @@ end endgenerate assign O = |x; endmodule + ''')