mirror of https://github.com/openXC7/prjxray.git
Ran make format-py
Signed-off-by: Maciej Kurc <mkurc@antmicro.com>
This commit is contained in:
Maciej Kurc
parent
a2552bf478
commit
369aa38c6a
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@ -12,8 +12,10 @@ segmk = Segmaker("design.bits")
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with open("params.json", "r") as fp:
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data = json.load(fp)
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iface_types = ["NETWORKING", "OVERSAMPLE", "MEMORY", "MEMORY_DDR3", "MEMORY_QDR"]
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data_rates = ["SDR", "DDR"]
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iface_types = [
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"NETWORKING", "OVERSAMPLE", "MEMORY", "MEMORY_DDR3", "MEMORY_QDR"
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]
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data_rates = ["SDR", "DDR"]
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data_widths = [2, 3, 4, 5, 6, 7, 8, 10, 14]
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# Output tags
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@ -33,7 +35,7 @@ for params in data:
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segmk.add_site_tag(loc, "ISERDES.IN_USE", 0)
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segmk.add_site_tag(loc, "ISERDES.MODE.MASTER", 0)
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segmk.add_site_tag(loc, "ISERDES.MODE.SLAVE", 0)
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segmk.add_site_tag(loc, "ISERDES.MODE.SLAVE", 0)
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for i in iface_types:
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if i == "NETWORKING":
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@ -48,10 +50,10 @@ for params in data:
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segmk.add_site_tag(loc, "ISERDES.NUM_CE.1", 0)
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segmk.add_site_tag(loc, "ISERDES.NUM_CE.2", 0)
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for i in range(1, 4+1):
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for i in range(1, 4 + 1):
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segmk.add_site_tag(loc, "IFF.ZINIT_Q%d" % i, 0)
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for i in range(1, 4+1):
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for i in range(1, 4 + 1):
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segmk.add_site_tag(loc, "IFF.ZSRVAL_Q%d" % i, 0)
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segmk.add_site_tag(loc, "ZINV_D", 0)
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@ -75,15 +77,15 @@ for params in data:
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value = verilog.unquote(params["SERDES_MODE"])
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if value == "MASTER":
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segmk.add_site_tag(loc, "ISERDES.MODE.MASTER", 1)
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segmk.add_site_tag(loc, "ISERDES.MODE.SLAVE", 0)
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segmk.add_site_tag(loc, "ISERDES.MODE.SLAVE", 0)
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if value == "SLAVE":
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segmk.add_site_tag(loc, "ISERDES.MODE.MASTER", 0)
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segmk.add_site_tag(loc, "ISERDES.MODE.SLAVE", 1)
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segmk.add_site_tag(loc, "ISERDES.MODE.SLAVE", 1)
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iface_type = verilog.unquote(params["INTERFACE_TYPE"])
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data_rate = verilog.unquote(params["DATA_RATE"])
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data_rate = verilog.unquote(params["DATA_RATE"])
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data_width = int(params["DATA_WIDTH"])
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for i in iface_types:
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for j in data_rates:
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for k in data_widths:
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@ -103,23 +105,28 @@ for params in data:
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segmk.add_site_tag(loc, "ISERDES.NUM_CE.1", 0)
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segmk.add_site_tag(loc, "ISERDES.NUM_CE.2", 1)
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for i in range(1, 4+1):
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for i in range(1, 4 + 1):
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if ("INIT_Q%d" % i) in params:
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segmk.add_site_tag(loc, "IFF.ZINIT_Q%d" % i, not params["INIT_Q%d" % i])
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segmk.add_site_tag(
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loc, "IFF.ZINIT_Q%d" % i, not params["INIT_Q%d" % i])
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for i in range(1, 4+1):
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for i in range(1, 4 + 1):
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if ("SRVAL_Q%d" % i) in params:
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segmk.add_site_tag(loc, "IFF.ZSRVAL_Q%d" % i, not params["SRVAL_Q%d" % i])
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segmk.add_site_tag(
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loc, "IFF.ZSRVAL_Q%d" % i, not params["SRVAL_Q%d" % i])
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if "IS_D_INVERTED" in params:
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segmk.add_site_tag(loc, "ZINV_D", int(params["IS_D_INVERTED"] == 0))
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segmk.add_site_tag(
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loc, "ZINV_D", int(params["IS_D_INVERTED"] == 0))
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if "DYN_CLKDIV_INV_EN" in params:
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value = verilog.unquote(params["DYN_CLKDIV_INV_EN"])
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segmk.add_site_tag(loc, "ISERDES.DYN_CLKDIV_INV_EN", int(value == "TRUE"))
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segmk.add_site_tag(
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loc, "ISERDES.DYN_CLKDIV_INV_EN", int(value == "TRUE"))
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if "DYN_CLK_INV_EN" in params:
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value = verilog.unquote(params["DYN_CLK_INV_EN"])
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segmk.add_site_tag(loc, "ISERDES.DYN_CLK_INV_EN", int(value == "TRUE"))
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segmk.add_site_tag(
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loc, "ISERDES.DYN_CLK_INV_EN", int(value == "TRUE"))
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# This parameter actually controls muxes used both in ILOGIC and
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# ISERDES mode.
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@ -157,7 +164,11 @@ for params in data:
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# Write segments and tags for later check
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with open("tags.json", "w") as fp:
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tags = {loc_to_tile_site_map[l]: {k: int(v) for k, v in d.items()} for l, d in segmk.site_tags.items()}
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tags = {
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loc_to_tile_site_map[l]: {k: int(v)
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for k, v in d.items()}
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for l, d in segmk.site_tags.items()
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}
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json.dump(tags, fp, sort_keys=True, indent=1)
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@ -166,5 +177,6 @@ def bitfilter(frame_idx, bit_idx):
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return False
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return True
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segmk.compile(bitfilter=bitfilter)
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segmk.write()
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@ -13,7 +13,7 @@ from prjxray.db import Database
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# =============================================================================
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def gen_sites():
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def gen_sites():
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db = Database(util.get_db_root())
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grid = db.grid()
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@ -78,44 +78,65 @@ wire [{N}:0] do_buf;
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# Bottom site
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if random.randint(0, 1):
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iob_i = sites[1]
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iob_o = sites[3]
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iob_i = sites[1]
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iob_o = sites[3]
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ilogic = sites[2]
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# Top site
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else:
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iob_i = sites[3]
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iob_o = sites[1]
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iob_i = sites[3]
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iob_o = sites[1]
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ilogic = sites[4]
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# Site params
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params = {
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"_LOC": verilog.quote(ilogic),
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"IS_USED": int(random.randint(0, 10) > 0), # Make it used more often
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"INIT_Q1": random.randint(0, 1),
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"INIT_Q2": random.randint(0, 1),
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"INIT_Q3": random.randint(0, 1),
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"INIT_Q4": random.randint(0, 1),
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"SRVAL_Q1": random.randint(0, 1),
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"SRVAL_Q2": random.randint(0, 1),
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"SRVAL_Q3": random.randint(0, 1),
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"SRVAL_Q4": random.randint(0, 1),
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"NUM_CE": random.randint(1, 2),
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"_LOC":
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verilog.quote(ilogic),
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"IS_USED":
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int(random.randint(0, 10) > 0), # Make it used more often
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"INIT_Q1":
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random.randint(0, 1),
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"INIT_Q2":
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random.randint(0, 1),
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"INIT_Q3":
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random.randint(0, 1),
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"INIT_Q4":
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random.randint(0, 1),
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"SRVAL_Q1":
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random.randint(0, 1),
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"SRVAL_Q2":
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random.randint(0, 1),
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"SRVAL_Q3":
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random.randint(0, 1),
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"SRVAL_Q4":
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random.randint(0, 1),
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"NUM_CE":
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random.randint(1, 2),
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# The following one shows negative correlation (0 - not inverted)
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"IS_D_INVERTED": random.randint(0, 1),
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"IS_D_INVERTED":
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random.randint(0, 1),
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# No bits were found for parameters below
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#"IS_OCLKB_INVERTED": random.randint(0, 1),
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#"IS_OCLK_INVERTED": random.randint(0, 1),
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#"IS_CLKDIVP_INVERTED": random.randint(0, 1),
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#"IS_CLKDIV_INVERTED": random.randint(0, 1),
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#"IS_CLKB_INVERTED": random.randint(0, 1),
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#"IS_CLK_INVERTED": random.randint(0, 1),
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"DYN_CLKDIV_INV_EN": verilog.quote(random.choice(["TRUE", "FALSE"])),
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"DYN_CLK_INV_EN": verilog.quote(random.choice(["TRUE", "FALSE"])),
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"IOBDELAY": verilog.quote(random.choice(["NONE", "IBUF", "IFD", "BOTH"])),
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"OFB_USED": verilog.quote(random.choice(["TRUE"] + ["FALSE"]*9)), # Force more FALSEs
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#"IS_OCLKB_INVERTED": random.randint(0, 1),
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#"IS_OCLK_INVERTED": random.randint(0, 1),
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#"IS_CLKDIVP_INVERTED": random.randint(0, 1),
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#"IS_CLKDIV_INVERTED": random.randint(0, 1),
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#"IS_CLKB_INVERTED": random.randint(0, 1),
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#"IS_CLK_INVERTED": random.randint(0, 1),
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"DYN_CLKDIV_INV_EN":
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verilog.quote(random.choice(["TRUE", "FALSE"])),
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"DYN_CLK_INV_EN":
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verilog.quote(random.choice(["TRUE", "FALSE"])),
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"IOBDELAY":
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verilog.quote(random.choice(["NONE", "IBUF", "IFD", "BOTH"])),
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"OFB_USED":
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verilog.quote(
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random.choice(["TRUE"] + ["FALSE"] * 9)), # Force more FALSEs
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}
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iface_type = random.choice(["NETWORKING", "OVERSAMPLE", "MEMORY", "MEMORY_DDR3", "MEMORY_QDR"])
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iface_type = random.choice(
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[
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"NETWORKING", "OVERSAMPLE", "MEMORY", "MEMORY_DDR3",
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"MEMORY_QDR"
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])
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data_rate = random.choice(["SDR", "DDR"])
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serdes_mode = random.choice(["MASTER", "SLAVE"])
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@ -138,7 +159,7 @@ wire [{N}:0] do_buf;
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if verilog.unquote(params["OFB_USED"]) == "TRUE":
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params["IOBDELAY"] = verilog.quote("NONE")
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# Instantiate cell
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# Instantiate cell
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param_str = ",".join(".%s(%s)" % (k, v) for k, v in params.items())
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print('')
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