mirror of https://github.com/openXC7/prjxray.git
Added fuzzing for chained ISERDES
Signed-off-by: Maciej Kurc <mkurc@antmicro.com>
This commit is contained in:
Maciej Kurc
parent
369aa38c6a
commit
ea0fd9eb8e
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@ -19,161 +19,170 @@ data_rates = ["SDR", "DDR"]
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data_widths = [2, 3, 4, 5, 6, 7, 8, 10, 14]
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# Output tags
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loc_to_tile_site_map = {}
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for params in data:
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loc = verilog.unquote(params["_LOC"])
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loc = loc.replace("ILOGIC", "IOB")
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#loc_to_tile_site_map = {}
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for param_list in data:
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for params in param_list:
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loc = verilog.unquote(params["SITE_LOC"])
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loc = loc.replace("ILOGIC", "IOB")
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get_xy = util.create_xy_fun('IOB_')
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x, y = get_xy(loc)
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get_xy = util.create_xy_fun('IOB_')
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x, y = get_xy(loc)
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loc_to_tile_site_map[loc] = params["TILE"] + ".IOB_X0Y%d" % (y % 2)
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#loc_to_tile_site_map[loc] = params["TILE"] + ".IOB_X0Y%d" % (y % 2)
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# Serdes not used at all
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if not params["IS_USED"]:
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# Serdes not used at all
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if not params["IS_USED"]:
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segmk.add_site_tag(loc, "ISERDES.IN_USE", 0)
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segmk.add_site_tag(loc, "ISERDES.SHIFTOUT_USED", 0)
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segmk.add_site_tag(loc, "ISERDES.IN_USE", 0)
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segmk.add_site_tag(loc, "ISERDES.MODE.MASTER", 0)
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segmk.add_site_tag(loc, "ISERDES.MODE.SLAVE", 0)
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segmk.add_site_tag(loc, "ISERDES.MODE.MASTER", 0)
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segmk.add_site_tag(loc, "ISERDES.MODE.SLAVE", 0)
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for i in iface_types:
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if i == "NETWORKING":
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for i in iface_types:
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if i == "NETWORKING":
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for j in data_rates:
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for k in data_widths:
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tag = "ISERDES.%s.%s.%s" % (i, j, k)
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segmk.add_site_tag(loc, tag, 0)
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else:
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for j in data_rates:
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segmk.add_site_tag(loc, "ISERDES.%s.%s.4" % (i, j), 0)
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segmk.add_site_tag(loc, "ISERDES.NUM_CE.1", 0)
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segmk.add_site_tag(loc, "ISERDES.NUM_CE.2", 0)
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for i in range(1, 4 + 1):
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segmk.add_site_tag(loc, "IFF.ZINIT_Q%d" % i, 0)
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for i in range(1, 4 + 1):
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segmk.add_site_tag(loc, "IFF.ZSRVAL_Q%d" % i, 0)
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segmk.add_site_tag(loc, "ZINV_D", 0)
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segmk.add_site_tag(loc, "ISERDES.DYN_CLKDIV_INV_EN", 0)
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segmk.add_site_tag(loc, "ISERDES.DYN_CLK_INV_EN", 0)
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segmk.add_site_tag(loc, "IFFDELMUXE3.0", 1)
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segmk.add_site_tag(loc, "IFFDELMUXE3.1", 0)
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segmk.add_site_tag(loc, "IDELMUXE3.0", 1)
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segmk.add_site_tag(loc, "IDELMUXE3.1", 0)
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segmk.add_site_tag(loc, "ISERDES.OFB_USED", 0)
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# Serdes used
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else:
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segmk.add_site_tag(loc, "ISERDES.IN_USE", 1)
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if "SHIFTOUT_USED" in params:
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if params["CHAINED"]:
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value = params["SHIFTOUT_USED"]
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segmk.add_site_tag(loc, "ISERDES.SHIFTOUT_USED", value)
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if "SERDES_MODE" in params:
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value = verilog.unquote(params["SERDES_MODE"])
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if value == "MASTER":
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segmk.add_site_tag(loc, "ISERDES.MODE.MASTER", 1)
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segmk.add_site_tag(loc, "ISERDES.MODE.SLAVE", 0)
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if value == "SLAVE":
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segmk.add_site_tag(loc, "ISERDES.MODE.MASTER", 0)
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segmk.add_site_tag(loc, "ISERDES.MODE.SLAVE", 1)
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iface_type = verilog.unquote(params["INTERFACE_TYPE"])
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data_rate = verilog.unquote(params["DATA_RATE"])
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data_width = int(params["DATA_WIDTH"])
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for i in iface_types:
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for j in data_rates:
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for k in data_widths:
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tag = "ISERDES.%s.%s.%s" % (i, j, k)
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segmk.add_site_tag(loc, tag, 0)
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else:
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for j in data_rates:
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segmk.add_site_tag(loc, "ISERDES.%s.%s.4" % (i, j), 0)
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segmk.add_site_tag(loc, "ISERDES.NUM_CE.1", 0)
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segmk.add_site_tag(loc, "ISERDES.NUM_CE.2", 0)
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if i == iface_type:
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if j == data_rate:
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if k == data_width:
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segmk.add_site_tag(loc, tag, 1)
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for i in range(1, 4 + 1):
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segmk.add_site_tag(loc, "IFF.ZINIT_Q%d" % i, 0)
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if "NUM_CE" in params:
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value = params["NUM_CE"]
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if value == 1:
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segmk.add_site_tag(loc, "ISERDES.NUM_CE.1", 1)
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segmk.add_site_tag(loc, "ISERDES.NUM_CE.2", 0)
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if value == 2:
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segmk.add_site_tag(loc, "ISERDES.NUM_CE.1", 0)
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segmk.add_site_tag(loc, "ISERDES.NUM_CE.2", 1)
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for i in range(1, 4 + 1):
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segmk.add_site_tag(loc, "IFF.ZSRVAL_Q%d" % i, 0)
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for i in range(1, 4 + 1):
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if ("INIT_Q%d" % i) in params:
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segmk.add_site_tag(
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loc, "IFF.ZINIT_Q%d" % i, not params["INIT_Q%d" % i])
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segmk.add_site_tag(loc, "ZINV_D", 0)
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for i in range(1, 4 + 1):
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if ("SRVAL_Q%d" % i) in params:
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segmk.add_site_tag(
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loc, "IFF.ZSRVAL_Q%d" % i, not params["SRVAL_Q%d" % i])
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segmk.add_site_tag(loc, "ISERDES.DYN_CLKDIV_INV_EN", 0)
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segmk.add_site_tag(loc, "ISERDES.DYN_CLK_INV_EN", 0)
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if "IS_D_INVERTED" in params:
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if not params["CHAINED"]:
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segmk.add_site_tag(
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loc, "ZINV_D", int(params["IS_D_INVERTED"] == 0))
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segmk.add_site_tag(loc, "IFFDELMUXE3.0", 1)
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segmk.add_site_tag(loc, "IFFDELMUXE3.1", 0)
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segmk.add_site_tag(loc, "IDELMUXE3.0", 1)
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segmk.add_site_tag(loc, "IDELMUXE3.1", 0)
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segmk.add_site_tag(loc, "ISERDES.OFB_USED", 0)
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# Serdes used
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else:
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segmk.add_site_tag(loc, "ISERDES.IN_USE", 1)
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if "SERDES_MODE" in params:
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value = verilog.unquote(params["SERDES_MODE"])
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if value == "MASTER":
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segmk.add_site_tag(loc, "ISERDES.MODE.MASTER", 1)
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segmk.add_site_tag(loc, "ISERDES.MODE.SLAVE", 0)
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if value == "SLAVE":
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segmk.add_site_tag(loc, "ISERDES.MODE.MASTER", 0)
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segmk.add_site_tag(loc, "ISERDES.MODE.SLAVE", 1)
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iface_type = verilog.unquote(params["INTERFACE_TYPE"])
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data_rate = verilog.unquote(params["DATA_RATE"])
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data_width = int(params["DATA_WIDTH"])
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for i in iface_types:
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for j in data_rates:
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for k in data_widths:
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tag = "ISERDES.%s.%s.%s" % (i, j, k)
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if i == iface_type:
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if j == data_rate:
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if k == data_width:
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segmk.add_site_tag(loc, tag, 1)
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if "NUM_CE" in params:
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value = params["NUM_CE"]
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if value == 1:
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segmk.add_site_tag(loc, "ISERDES.NUM_CE.1", 1)
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segmk.add_site_tag(loc, "ISERDES.NUM_CE.2", 0)
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if value == 2:
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segmk.add_site_tag(loc, "ISERDES.NUM_CE.1", 0)
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segmk.add_site_tag(loc, "ISERDES.NUM_CE.2", 1)
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for i in range(1, 4 + 1):
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if ("INIT_Q%d" % i) in params:
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if "DYN_CLKDIV_INV_EN" in params:
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value = verilog.unquote(params["DYN_CLKDIV_INV_EN"])
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segmk.add_site_tag(
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loc, "IFF.ZINIT_Q%d" % i, not params["INIT_Q%d" % i])
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for i in range(1, 4 + 1):
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if ("SRVAL_Q%d" % i) in params:
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loc, "ISERDES.DYN_CLKDIV_INV_EN", int(value == "TRUE"))
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if "DYN_CLK_INV_EN" in params:
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value = verilog.unquote(params["DYN_CLK_INV_EN"])
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segmk.add_site_tag(
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loc, "IFF.ZSRVAL_Q%d" % i, not params["SRVAL_Q%d" % i])
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loc, "ISERDES.DYN_CLK_INV_EN", int(value == "TRUE"))
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if "IS_D_INVERTED" in params:
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segmk.add_site_tag(
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loc, "ZINV_D", int(params["IS_D_INVERTED"] == 0))
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# This parameter actually controls muxes used both in ILOGIC and
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# ISERDES mode.
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if "IOBDELAY" in params:
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value = verilog.unquote(params["IOBDELAY"])
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if value == "NONE":
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#segmk.add_site_tag(loc, "IOBDELAY_NONE", 1)
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segmk.add_site_tag(loc, "IFFDELMUXE3.0", 0)
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segmk.add_site_tag(loc, "IFFDELMUXE3.1", 1)
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segmk.add_site_tag(loc, "IDELMUXE3.0", 0)
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segmk.add_site_tag(loc, "IDELMUXE3.1", 1)
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if value == "IBUF":
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#segmk.add_site_tag(loc, "IOBDELAY_IBUF", 1)
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segmk.add_site_tag(loc, "IFFDELMUXE3.0", 0)
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segmk.add_site_tag(loc, "IFFDELMUXE3.1", 1)
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segmk.add_site_tag(loc, "IDELMUXE3.0", 1)
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segmk.add_site_tag(loc, "IDELMUXE3.1", 0)
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if value == "IFD":
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#segmk.add_site_tag(loc, "IOBDELAY_IFD" , 1)
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segmk.add_site_tag(loc, "IFFDELMUXE3.0", 1)
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segmk.add_site_tag(loc, "IFFDELMUXE3.1", 0)
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segmk.add_site_tag(loc, "IDELMUXE3.0", 0)
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segmk.add_site_tag(loc, "IDELMUXE3.1", 1)
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if value == "BOTH":
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#segmk.add_site_tag(loc, "IOBDELAY_BOTH", 1)
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segmk.add_site_tag(loc, "IFFDELMUXE3.0", 1)
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segmk.add_site_tag(loc, "IFFDELMUXE3.1", 0)
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segmk.add_site_tag(loc, "IDELMUXE3.0", 1)
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segmk.add_site_tag(loc, "IDELMUXE3.1", 0)
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if "DYN_CLKDIV_INV_EN" in params:
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value = verilog.unquote(params["DYN_CLKDIV_INV_EN"])
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segmk.add_site_tag(
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loc, "ISERDES.DYN_CLKDIV_INV_EN", int(value == "TRUE"))
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if "DYN_CLK_INV_EN" in params:
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value = verilog.unquote(params["DYN_CLK_INV_EN"])
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segmk.add_site_tag(
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loc, "ISERDES.DYN_CLK_INV_EN", int(value == "TRUE"))
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# This parameter actually controls muxes used both in ILOGIC and
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# ISERDES mode.
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if "IOBDELAY" in params:
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value = verilog.unquote(params["IOBDELAY"])
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if value == "NONE":
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#segmk.add_site_tag(loc, "IOBDELAY_NONE", 1)
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segmk.add_site_tag(loc, "IFFDELMUXE3.0", 0)
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segmk.add_site_tag(loc, "IFFDELMUXE3.1", 1)
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segmk.add_site_tag(loc, "IDELMUXE3.0", 0)
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segmk.add_site_tag(loc, "IDELMUXE3.1", 1)
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if value == "IBUF":
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#segmk.add_site_tag(loc, "IOBDELAY_IBUF", 1)
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segmk.add_site_tag(loc, "IFFDELMUXE3.0", 0)
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segmk.add_site_tag(loc, "IFFDELMUXE3.1", 1)
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segmk.add_site_tag(loc, "IDELMUXE3.0", 1)
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segmk.add_site_tag(loc, "IDELMUXE3.1", 0)
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if value == "IFD":
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#segmk.add_site_tag(loc, "IOBDELAY_IFD" , 1)
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segmk.add_site_tag(loc, "IFFDELMUXE3.0", 1)
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segmk.add_site_tag(loc, "IFFDELMUXE3.1", 0)
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segmk.add_site_tag(loc, "IDELMUXE3.0", 0)
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segmk.add_site_tag(loc, "IDELMUXE3.1", 1)
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if value == "BOTH":
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#segmk.add_site_tag(loc, "IOBDELAY_BOTH", 1)
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segmk.add_site_tag(loc, "IFFDELMUXE3.0", 1)
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segmk.add_site_tag(loc, "IFFDELMUXE3.1", 0)
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segmk.add_site_tag(loc, "IDELMUXE3.0", 1)
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segmk.add_site_tag(loc, "IDELMUXE3.1", 0)
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if "OFB_USED" in params:
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value = verilog.unquote(params["OFB_USED"])
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if value == "TRUE":
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segmk.add_site_tag(loc, "ISERDES.OFB_USED", 1)
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if "OFB_USED" in params:
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value = verilog.unquote(params["OFB_USED"])
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if value == "TRUE":
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segmk.add_site_tag(loc, "ISERDES.OFB_USED", 1)
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# Write segments and tags for later check
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with open("tags.json", "w") as fp:
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tags = {
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loc_to_tile_site_map[l]: {k: int(v)
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for k, v in d.items()}
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for l, d in segmk.site_tags.items()
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}
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json.dump(tags, fp, sort_keys=True, indent=1)
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#with open("tags.json", "w") as fp:
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# tags = {
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# loc_to_tile_site_map[l]: {k: int(v)
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# for k, v in d.items()}
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# for l, d in segmk.site_tags.items()
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# }
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# json.dump(tags, fp, sort_keys=True, indent=1)
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def bitfilter(frame_idx, bit_idx):
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if frame_idx < 25 or frame_idx > 31:
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if frame_idx < 26 or frame_idx > 31:
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return False
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return True
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@ -1,5 +1,3 @@
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set_param general.maxThreads 1
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create_project -force -part $::env(XRAY_PART) design design
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read_verilog top.v
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synth_design -top top
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@ -10,6 +8,7 @@ set_property BITSTREAM.GENERAL.PERFRAMECRC YES [current_design]
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set_param tcl.collectionResultDisplayLimit 0
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set_property IS_ENABLED 0 [get_drc_checks {NSTD-1}]
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set_property IS_ENABLED 0 [get_drc_checks {NDRV-1}]
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set_property IS_ENABLED 0 [get_drc_checks {UCIO-1}]
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set_property IS_ENABLED 0 [get_drc_checks {REQP-98}]
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set_property IS_ENABLED 0 [get_drc_checks {REQP-109}]
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@ -47,6 +47,82 @@ def gen_sites():
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yield iob_tile_name, iob33m, ilogic_m, iob33s, ilogic_s
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def gen_iserdes(loc):
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# Site params
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params = {
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"SITE_LOC":
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verilog.quote(loc),
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"IS_USED":
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int(random.randint(0, 10) > 0), # Make it used more often
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"INIT_Q1":
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random.randint(0, 1),
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"INIT_Q2":
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random.randint(0, 1),
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"INIT_Q3":
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random.randint(0, 1),
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"INIT_Q4":
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random.randint(0, 1),
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"SRVAL_Q1":
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random.randint(0, 1),
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"SRVAL_Q2":
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random.randint(0, 1),
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"SRVAL_Q3":
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random.randint(0, 1),
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"SRVAL_Q4":
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random.randint(0, 1),
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"NUM_CE":
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random.randint(1, 2),
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# The following one shows negative correlation (0 - not inverted)
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"IS_D_INVERTED":
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random.randint(0, 1),
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# No bits were found for parameters below
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#"IS_OCLKB_INVERTED": random.randint(0, 1),
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#"IS_OCLK_INVERTED": random.randint(0, 1),
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#"IS_CLKDIVP_INVERTED": random.randint(0, 1),
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#"IS_CLKDIV_INVERTED": random.randint(0, 1),
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#"IS_CLKB_INVERTED": random.randint(0, 1),
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#"IS_CLK_INVERTED": random.randint(0, 1),
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"DYN_CLKDIV_INV_EN":
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verilog.quote(random.choice(["TRUE", "FALSE"])),
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"DYN_CLK_INV_EN":
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verilog.quote(random.choice(["TRUE", "FALSE"])),
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"IOBDELAY":
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verilog.quote(random.choice(["NONE", "IBUF", "IFD", "BOTH"])),
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"OFB_USED":
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verilog.quote(
|
||||
random.choice(["TRUE"] + ["FALSE"] * 9)), # Force more FALSEs
|
||||
}
|
||||
|
||||
iface_type = random.choice(
|
||||
[
|
||||
"NETWORKING", "OVERSAMPLE", "MEMORY", "MEMORY_DDR3",
|
||||
"MEMORY_QDR"
|
||||
])
|
||||
data_rate = random.choice(["SDR", "DDR"])
|
||||
serdes_mode = random.choice(["MASTER", "SLAVE"])
|
||||
|
||||
params["INTERFACE_TYPE"] = verilog.quote(iface_type)
|
||||
params["DATA_RATE"] = verilog.quote(data_rate)
|
||||
params["SERDES_MODE"] = verilog.quote(serdes_mode)
|
||||
|
||||
# Networking mode
|
||||
if iface_type == "NETWORKING":
|
||||
data_widths = {
|
||||
"SDR": [2, 3, 4, 5, 6, 7, 8],
|
||||
"DDR": [4, 6, 8, 10, 14],
|
||||
}
|
||||
params["DATA_WIDTH"] = random.choice(data_widths[data_rate])
|
||||
|
||||
# Others
|
||||
else:
|
||||
params["DATA_WIDTH"] = 4
|
||||
|
||||
if verilog.unquote(params["OFB_USED"]) == "TRUE":
|
||||
params["IOBDELAY"] = verilog.quote("NONE")
|
||||
|
||||
return params
|
||||
|
||||
|
||||
def run():
|
||||
|
||||
|
|
@ -76,103 +152,85 @@ wire [{N}:0] do_buf;
|
|||
for i, sites in enumerate(tiles):
|
||||
tile_name = sites[0]
|
||||
|
||||
# Bottom site
|
||||
if random.randint(0, 1):
|
||||
# Single ISERDES
|
||||
if random.randint(0, 5) >= 1:
|
||||
|
||||
# Bottom site
|
||||
if random.randint(0, 1):
|
||||
iob_i = sites[1]
|
||||
iob_o = sites[3]
|
||||
ilogic = sites[2]
|
||||
# Top site
|
||||
else:
|
||||
iob_i = sites[3]
|
||||
iob_o = sites[1]
|
||||
ilogic = sites[4]
|
||||
|
||||
# Generate cell
|
||||
params = gen_iserdes(ilogic)
|
||||
|
||||
# Instantiate the cell
|
||||
print('')
|
||||
print('(* LOC="%s", KEEP, DONT_TOUCH *)' % iob_i)
|
||||
print('IBUF ibuf_%03d (.I(di[%3d]), .O(di_buf[%3d]));' % (i, i, i))
|
||||
print('(* LOC="%s", KEEP, DONT_TOUCH *)' % iob_o)
|
||||
print('OBUF obuf_%03d (.I(do_buf[%3d]), .O(do[%3d]));' % (i, i, i))
|
||||
|
||||
param_str = ",".join(".%s(%s)" % (k, v) for k, v in params.items())
|
||||
print('iserdes_single #(%s) iserdes_%03d (.clk1(clk1), .clk2(clk2), .I(di_buf[%3d]), .O(do_buf[%3d]));' % (param_str, i, i, i))
|
||||
|
||||
params["CHAINED"] = 0
|
||||
|
||||
data.append([params])
|
||||
|
||||
# Dual ISERDES chained
|
||||
else:
|
||||
|
||||
iob_i = sites[1]
|
||||
iob_o = sites[3]
|
||||
ilogic = sites[2]
|
||||
# Top site
|
||||
else:
|
||||
iob_i = sites[3]
|
||||
iob_o = sites[1]
|
||||
ilogic = sites[4]
|
||||
ilogic = [sites[2], sites[4]]
|
||||
|
||||
# Generate cells
|
||||
params_m = gen_iserdes(ilogic[0])
|
||||
params_s = gen_iserdes(ilogic[1])
|
||||
|
||||
# Site params
|
||||
params = {
|
||||
"_LOC":
|
||||
verilog.quote(ilogic),
|
||||
"IS_USED":
|
||||
int(random.randint(0, 10) > 0), # Make it used more often
|
||||
"INIT_Q1":
|
||||
random.randint(0, 1),
|
||||
"INIT_Q2":
|
||||
random.randint(0, 1),
|
||||
"INIT_Q3":
|
||||
random.randint(0, 1),
|
||||
"INIT_Q4":
|
||||
random.randint(0, 1),
|
||||
"SRVAL_Q1":
|
||||
random.randint(0, 1),
|
||||
"SRVAL_Q2":
|
||||
random.randint(0, 1),
|
||||
"SRVAL_Q3":
|
||||
random.randint(0, 1),
|
||||
"SRVAL_Q4":
|
||||
random.randint(0, 1),
|
||||
"NUM_CE":
|
||||
random.randint(1, 2),
|
||||
# The following one shows negative correlation (0 - not inverted)
|
||||
"IS_D_INVERTED":
|
||||
random.randint(0, 1),
|
||||
# No bits were found for parameters below
|
||||
#"IS_OCLKB_INVERTED": random.randint(0, 1),
|
||||
#"IS_OCLK_INVERTED": random.randint(0, 1),
|
||||
#"IS_CLKDIVP_INVERTED": random.randint(0, 1),
|
||||
#"IS_CLKDIV_INVERTED": random.randint(0, 1),
|
||||
#"IS_CLKB_INVERTED": random.randint(0, 1),
|
||||
#"IS_CLK_INVERTED": random.randint(0, 1),
|
||||
"DYN_CLKDIV_INV_EN":
|
||||
verilog.quote(random.choice(["TRUE", "FALSE"])),
|
||||
"DYN_CLK_INV_EN":
|
||||
verilog.quote(random.choice(["TRUE", "FALSE"])),
|
||||
"IOBDELAY":
|
||||
verilog.quote(random.choice(["NONE", "IBUF", "IFD", "BOTH"])),
|
||||
"OFB_USED":
|
||||
verilog.quote(
|
||||
random.choice(["TRUE"] + ["FALSE"] * 9)), # Force more FALSEs
|
||||
}
|
||||
# Force relevant parameters
|
||||
params_m["SERDES_MODE"] = verilog.quote("MASTER")
|
||||
params_m["IS_USED"] = 1
|
||||
|
||||
iface_type = random.choice(
|
||||
[
|
||||
"NETWORKING", "OVERSAMPLE", "MEMORY", "MEMORY_DDR3",
|
||||
"MEMORY_QDR"
|
||||
])
|
||||
data_rate = random.choice(["SDR", "DDR"])
|
||||
serdes_mode = random.choice(["MASTER", "SLAVE"])
|
||||
params_m["INTERFACE_TYPE"] = verilog.quote("NETWORKING")
|
||||
params_m["DATA_RATE"] = verilog.quote("DDR")
|
||||
params_m["DATA_WIDTH"] = random.choice([10, 14])
|
||||
|
||||
params["INTERFACE_TYPE"] = verilog.quote(iface_type)
|
||||
params["DATA_RATE"] = verilog.quote(data_rate)
|
||||
params["SERDES_MODE"] = verilog.quote(serdes_mode)
|
||||
params_s["SERDES_MODE"] = verilog.quote("SLAVE")
|
||||
params_s["IS_USED"] = 1
|
||||
|
||||
# Networking mode
|
||||
if iface_type == "NETWORKING":
|
||||
data_widths = {
|
||||
"SDR": [2, 3, 4, 5, 6, 7, 8],
|
||||
"DDR": [4, 6, 8, 10, 14],
|
||||
}
|
||||
params["DATA_WIDTH"] = random.choice(data_widths[data_rate])
|
||||
params_s["INTERFACE_TYPE"] = params_m["INTERFACE_TYPE"]
|
||||
params_s["DATA_RATE"] = params_m["DATA_RATE"]
|
||||
params_s["DATA_WIDTH"] = params_m["DATA_WIDTH"]
|
||||
|
||||
# Others
|
||||
else:
|
||||
params["DATA_WIDTH"] = 4
|
||||
# Instantiate cells
|
||||
print('')
|
||||
print('(* LOC="%s", KEEP, DONT_TOUCH *)' % iob_i)
|
||||
print('IBUF ibuf_%03d (.I(di[%3d]), .O(di_buf[%3d]));' % (i, i, i))
|
||||
print('(* LOC="%s", KEEP, DONT_TOUCH *)' % iob_o)
|
||||
print('OBUF obuf_%03d (.I(do_buf[%3d]), .O(do[%3d]));' % (i, i, i))
|
||||
|
||||
if verilog.unquote(params["OFB_USED"]) == "TRUE":
|
||||
params["IOBDELAY"] = verilog.quote("NONE")
|
||||
print('wire o_%03d_m;' % i)
|
||||
print('wire o_%03d_s;' % i)
|
||||
print('wire [1:0] sh_%03d;' % i)
|
||||
print('assign do_buf[%3d] = |q_%03d_m || |q_%03d_s;' % (i, i, i))
|
||||
param_str = ",".join(".%s(%s)" % (k, v) for k, v in params_m.items())
|
||||
print('iserdes_single #(%s) iserdes_%03d_m (.clk1(clk1), .clk2(clk2), .I(di_buf[%3d]), .O(q_%03d_m), .shiftout(sh_%03d));' % (param_str, i, i, i, i))
|
||||
param_str = ",".join(".%s(%s)" % (k, v) for k, v in params_s.items())
|
||||
print('iserdes_single #(%s) iserdes_%03d_s (.clk1(clk1), .clk2(clk2), .O(q_%03d_s), .shiftin(sh_%03d));' % (param_str, i, i, i))
|
||||
|
||||
# Instantiate cell
|
||||
param_str = ",".join(".%s(%s)" % (k, v) for k, v in params.items())
|
||||
params_m["SHIFTOUT_USED"] = 1
|
||||
|
||||
print('')
|
||||
print('(* LOC="%s", KEEP, DONT_TOUCH *)' % iob_i)
|
||||
print('IBUF ibuf_%03d (.I(di[%3d]), .O(di_buf[%3d]));' % (i, i, i))
|
||||
print('(* LOC="%s", KEEP, DONT_TOUCH *)' % iob_o)
|
||||
print('OBUF obuf_%03d (.I(do_buf[%3d]), .O(do[%3d]));' % (i, i, i))
|
||||
print(
|
||||
'iserdes_single #(%s) iserdes_%03d (.clk1(clk1), .clk2(clk2), .I(di_buf[%3d]), .O(do_buf[%3d]));'
|
||||
% (param_str, i, i, i))
|
||||
params_m["CHAINED"] = 1
|
||||
params_s["CHAINED"] = 1
|
||||
|
||||
params["TILE"] = tile_name
|
||||
data.append(params)
|
||||
data.append([params_m, params_s])
|
||||
|
||||
# Store params
|
||||
with open("params.json", "w") as fp:
|
||||
|
|
@ -187,10 +245,12 @@ module iserdes_single(
|
|||
input wire clk1,
|
||||
input wire clk2,
|
||||
input wire I,
|
||||
output wire O
|
||||
output wire O,
|
||||
input wire [1:0] shiftin,
|
||||
output wire [1:0] shiftout
|
||||
);
|
||||
|
||||
parameter _LOC = "";
|
||||
parameter SITE_LOC = "";
|
||||
parameter IS_USED = 1;
|
||||
parameter INTERFACE_TYPE = "NETWORKING";
|
||||
parameter DATA_RATE = "DDR";
|
||||
|
|
@ -217,13 +277,13 @@ parameter DYN_CLK_INV_EN = "FALSE";
|
|||
parameter IOBDELAY = "NONE";
|
||||
parameter OFB_USED = "FALSE";
|
||||
|
||||
(* KEEP, DONT_TOUCH *)
|
||||
wire [7:0] x;
|
||||
|
||||
(* KEEP, DONT_TOUCH *)
|
||||
generate if (IS_USED) begin
|
||||
|
||||
// Single ISERDES
|
||||
(* LOC=_LOC, KEEP, DONT_TOUCH *)
|
||||
// ISERDES
|
||||
(* LOC=SITE_LOC, KEEP, DONT_TOUCH *)
|
||||
ISERDESE2 #
|
||||
(
|
||||
.INTERFACE_TYPE(INTERFACE_TYPE),
|
||||
|
|
@ -277,8 +337,10 @@ generate if (IS_USED) begin
|
|||
.Q6(x[5]),
|
||||
.Q7(x[6]),
|
||||
.Q8(x[7]),
|
||||
.SHIFTOUT1(),
|
||||
.SHIFTOUT2()
|
||||
.SHIFTIN1(shiftin[0]),
|
||||
.SHIFTIN2(shiftin[1]),
|
||||
.SHIFTOUT1(shiftout[0]),
|
||||
.SHIFTOUT2(shiftout[1])
|
||||
);
|
||||
|
||||
end else begin
|
||||
|
|
@ -298,6 +360,7 @@ end endgenerate
|
|||
assign O = |x;
|
||||
|
||||
endmodule
|
||||
|
||||
''')
|
||||
|
||||
|
||||
|
|
|
|||
Loading…
Reference in New Issue