Revert "Whitespace"

fuzzers/011-clb-ffconfig/README.md

@@ -34,7 +34,7 @@ Configures whether a storage element is synchronous or asynchronous.
 
 Scope: entire site (not individual FFs)
 
-| FFSYNC | Reset        | Applicable prims          |
+| FFSYNC | Reset        | Applicable prims          | 
 |--------|--------------|---------------------------|
 |0       | Synchronous  | FDPE, FDCE, LDCE, LDPE    |
 |1       | Asynchronous | FDSE, FDRE                |

fuzzers/011-clb-ffconfig/generate.py

@@ -58,7 +58,7 @@ with open("design.txt", "r") as f:
         puts $fp "$type $tile $grid_x $grid_y $ff $bel_type $used $usedstr"
 
         CLBLM_L CLBLM_L_X10Y137 30 13 SLICE_X13Y137/AFF REG_INIT 1 FDRE
-        CLBLM_L CLBLM_L_X10Y137 30 13 SLICE_X12Y137/D5FF FF_INIT 0
+        CLBLM_L CLBLM_L_X10Y137 30 13 SLICE_X12Y137/D5FF FF_INIT 0 
         '''
         line = line.split()
         tile_type = line[0]

fuzzers/013-clb-ncy0/minitest/top.v

@@ -94,7 +94,7 @@ module clb_NCY0_O5 (input clk, input [7:0] din, output [7:0] dout);
     always @(*) begin
         s = din[7:4];
         s[N] = o6;
-
+        
         di = {din[3:0]};
         di[N] = o5;
     end

fuzzers/015-clb-nffmux/top.py

@@ -143,7 +143,7 @@ module myLUT8 (input clk, input [7:0] din,
         .O6(lutno6[1]));
 
     generate if (ALUT_SRL != 0) begin
-
+    
     (* LOC=LOC, BEL="A6LUT", KEEP, DONT_TOUCH *)
 	SRLC32E #(
 		.INIT(64'h8000_1CE0_0000_0001)
@@ -158,7 +158,7 @@ module myLUT8 (input clk, input [7:0] din,
     assign lutno5[0] = din[6];
 
     end else begin
-
+	
     (* LOC=LOC, BEL="A6LUT", KEEP, DONT_TOUCH *)
 	LUT6_2 #(
 		.INIT(64'h8000_1CE0_0000_0001)

fuzzers/016-clb-noutmux/minitest/top.v

@@ -51,7 +51,7 @@ module roi(input clk, input [255:0] din, output [255:0] dout);
             clb_NOUTMUX_XOR     (.clk(clk), .din(din[  56 +: 8]), .dout(dout[ 56 +: 8 ]));
     //ok
     clb_NOUTMUX_B5Q #(.LOC("SLICE_X18Y105"), .N(N))
-            clb_NOUTMUX_B5Q     (.clk(clk), .din(din[  48 +: 8]), .dout(dout[ 48 +: 8 ]));
+            clb_NOUTMUX_B5Q     (.clk(clk), .din(din[  48 +: 8]), .dout(dout[ 48 +: 8 ]));    
 endmodule
 
 module myLUT8 (input clk, input [7:0] din,

fuzzers/016-clb-noutmux/top.py

@@ -147,7 +147,7 @@ module myLUT8 (input clk, input [7:0] din,
 		.O6(lutno6[1]));
 
     generate if (ALUT_SRL != 0) begin
-
+    
     (* LOC=LOC, BEL="A6LUT", KEEP, DONT_TOUCH *)
 	SRLC32E #(
 		.INIT(64'h8000_1CE0_0000_0001)
@@ -162,7 +162,7 @@ module myLUT8 (input clk, input [7:0] din,
     assign lutno5[0] = din[6];
 
     end else begin
-
+	
     (* LOC=LOC, BEL="A6LUT", KEEP, DONT_TOUCH *)
 	LUT6_2 #(
 		.INIT(64'h8000_1CE0_0000_0001)

fuzzers/018-clb-ram/minitest/README.md

@@ -1,12 +1,12 @@
 # CLB_RAM Minitest
 
 ## Purpose
-SLICEM RAM test
-LUT6 => 64 bits
-Focus on 64 bit
-32 probably uses same O5/O6 stuff
-128 probably uses same MUX stuff
-Why isn't there a 256?
+SLICEM RAM test  
+LUT6 => 64 bits  
+Focus on 64 bit  
+32 probably uses same O5/O6 stuff  
+128 probably uses same MUX stuff  
+Why isn't there a 256?  
 
 ## Result
 ```

fuzzers/019-clb-ndi1mux/minitest/README.md

@@ -1,18 +1,18 @@
 # CLB_nDI1MUX Minitest
 
 ## Purpose
-Trying to set SLICEM LUT DI1 inputs
-These exist for LUTA, LUTB, and LUTC only
-Can either be an external signal, another LUT's data input, or another LUT's carry
-Note: mux input pattern is irregular
+Trying to set SLICEM LUT DI1 inputs  
+These exist for LUTA, LUTB, and LUTC only  
+Can either be an external signal, another LUT's data input, or another LUT's carry  
+Note: mux input pattern is irregular  
 
 ## Result
-The following bits are set for NI but not NMC31:
+The following bits are set for NI but not NMC31:  
 ```
 bit 00_00 ADI1MUX.AI
 bit 00_20 BDI1MUX.BI
 bit 01_43 BDI1MUX.CI
 ```
-Additionally, test with unknown DI mux bits don't appear near NI bits
-There is something strange going on
+Additionally, test with unknown DI mux bits don't appear near NI bits  
+There is something strange going on  
 

fuzzers/030-iob/minitest/README.md

@@ -22,8 +22,8 @@ DRIVE     38_64    38_66    38_72    38_74    39_65    39_73
 LVCMOS25
 DRIVE     38_64    38_66    38_72    38_74    39_65    39_73
 4           X        X                                   X
-8                             X
-12
+8                             X                 
+12                                            
 16                                     X        X        X
 
 LVCMOS33

fuzzers/030-iob/minitest/top.v

@@ -145,7 +145,7 @@ endmodule
 */
 
 /*
-ERROR: [DRC REQP-1581] obuf_loaded: OBUFT roi/dut pin O drives one or more invalid loads. The loads are: dout_shr[1]_i_1
+ERROR: [DRC REQP-1581] obuf_loaded: OBUFT roi/dut pin O drives one or more invalid loads. The loads are: dout_shr[1]_i_1 
 ERROR: [Place 30-69] Instance roi/dut (OBUFT) is unplaced after IO placer
 hmm
 Abandoning verilog approach

fuzzers/059-pip-byp-bounce/README.md

@@ -1,4 +1,4 @@
-Fuzzer for the FAN_ALT*.BYP_BOUNCE PIPs
+Fuzzer for the FAN_ALT*.BYP_BOUNCE PIPs 
 ---------------------------------------
 
 This fuzzer solves the FAN_ALT.BYP_BOUNCE PIPs which were occasionally solved incorrectly in 050-pip-seed or 056-pip-rem.

fuzzers/074-dump_all/cleanup_site_pins.py

@@ -51,7 +51,7 @@ def find_origin_coordinate(sites):
 def create_site_pin_to_wire_maps(tile_name, nodes):
     """ Create a map from site_pin names to nodes.
 
-  Create a mapping from site pins to tile local wires.  For each node that is
+  Create a mapping from site pins to tile local wires.  For each node that is 
   attached to a site pin, there should only be 1 tile local wire.
 
   """