mirror of https://github.com/openXC7/prjxray.git
184 lines
3.8 KiB
Verilog
184 lines
3.8 KiB
Verilog
/*
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IOBUF
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Not a primitive?
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Looks like it has an OBUFT
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Output buffer family:
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OBUF
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OBUFDS
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OBUFT
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OBUFTDS
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*/
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`ifndef ROI
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ERROR: must set ROI
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`endif
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module top(input clk, stb, di, output do);
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localparam integer DIN_N = 256;
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localparam integer DOUT_N = 256;
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reg [DIN_N-1:0] din;
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wire [DOUT_N-1:0] dout;
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reg [DIN_N-1:0] din_shr;
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reg [DOUT_N-1:0] dout_shr;
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always @(posedge clk) begin
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din_shr <= {din_shr, di};
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dout_shr <= {dout_shr, din_shr[DIN_N-1]};
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if (stb) begin
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din <= din_shr;
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dout_shr <= dout;
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end
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end
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assign do = dout_shr[DOUT_N-1];
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`ROI
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roi (
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.clk(clk),
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.din(din),
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.dout(dout)
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);
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endmodule
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module roi_io_a(input clk, input [255:0] din, output [255:0] dout);
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assign dout[0] = din[0] & din[1];
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IOBUF_INTERMDISABLE #(
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.DRIVE(12),
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.IBUF_LOW_PWR("TRUE"),
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.IOSTANDARD("DEFAULT"),
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.SLEW("SLOW"),
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.USE_IBUFDISABLE("TRUE")
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) IOBUF_INTERMDISABLE_inst (
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.O(1'b0),
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.IO(1'bz),
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.I(dout[8]),
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.IBUFDISABLE(1'b0),
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.INTERMDISABLE(1'b0),
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.T(1'b1));
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endmodule
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module roi_io_b(input clk, input [255:0] din, output [255:0] dout);
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assign dout[0] = din[0] & din[1];
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wire onet;
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IOBUF_INTERMDISABLE #(
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.DRIVE(12),
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.IBUF_LOW_PWR("FALSE"),
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.IOSTANDARD("DEFAULT"),
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.SLEW("SLOW"),
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.USE_IBUFDISABLE("FALSE")
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) IOBUF_INTERMDISABLE_inst (
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.O(onet),
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.IO(1'bz),
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.I(dout[8]),
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.IBUFDISABLE(1'b0),
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.INTERMDISABLE(1'b0),
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.T(1'b1));
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PULLUP PULLUP_inst (
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.O(onet)
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);
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IOBUF_INTERMDISABLE #(
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.DRIVE(12),
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.IBUF_LOW_PWR("FALSE"),
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.IOSTANDARD("DEFAULT"),
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.SLEW("SLOW"),
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.USE_IBUFDISABLE("FALSE")
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) i2 (
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.O(),
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.IO(1'bz),
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.I(dout[8]),
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.IBUFDISABLE(1'b0),
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.INTERMDISABLE(1'b0),
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.T(1'b1));
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endmodule
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/*
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For some reason this doesn't diff
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Was this optimized out?
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ERROR: [Place 30-69] Instance roi/dut/OBUFT (OBUFT) is unplaced after IO placer
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ERROR: [Place 30-68] Instance roi/dut/OBUFT (OBUFT) is not placed
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*/
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/*
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module roi_prop_a(input clk, input [255:0] din, output [255:0] dout);
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assign dout[0] = din[0] & din[1];
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//(* LOC="D19", KEEP, DONT_TOUCH *)
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(* KEEP, DONT_TOUCH *)
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IOBUF #(
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.DRIVE(8),
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.IBUF_LOW_PWR("TRUE"),
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.IOSTANDARD("DEFAULT"),
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.SLEW("SLOW")
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) dut (
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.O(dout[1]),
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.I(din[0]),
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.T(din[1]));
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endmodule
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module roi_prop_b(input clk, input [255:0] din, output [255:0] dout);
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assign dout[0] = din[0] & din[1];
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//(* LOC="D19", KEEP, DONT_TOUCH *)
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(* KEEP, DONT_TOUCH *)
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IOBUF #(
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.DRIVE(12),
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.IBUF_LOW_PWR("TRUE"),
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.IOSTANDARD("DEFAULT"),
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.SLEW("SLOW")
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) dut (
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.O(dout[1]),
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.I(din[0]),
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.T(din[1]));
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endmodule
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*/
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/*
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ERROR: [DRC REQP-1581] obuf_loaded: OBUFT roi/dut pin O drives one or more invalid loads. The loads are: dout_shr[1]_i_1
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ERROR: [Place 30-69] Instance roi/dut (OBUFT) is unplaced after IO placer
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hmm
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Abandoning verilog approach
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tcl seems to work well, just use it directly
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*/
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module roi_prop_a(input clk, input [255:0] din, output [255:0] dout);
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(* LOC="D19", KEEP, DONT_TOUCH *)
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//(* KEEP, DONT_TOUCH *)
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OBUFT #(
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.DRIVE(8),
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.IOSTANDARD("DEFAULT"),
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.SLEW("SLOW")
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) dut (
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//.O(dout[1]),
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.O(),
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.I(din[0]),
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.T(din[1]));
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endmodule
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module roi_prop_b(input clk, input [255:0] din, output [255:0] dout);
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(* LOC="D19", KEEP, DONT_TOUCH *)
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//(* KEEP, DONT_TOUCH *)
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(* KEEP, DONT_TOUCH *)
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OBUFT #(
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.DRIVE(12),
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.IOSTANDARD("DEFAULT"),
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.SLEW("SLOW")
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) dut (
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//.O(dout[1]),
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.O(),
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.I(din[0]),
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.T(din[1]));
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endmodule
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