mirror of https://github.com/openXC7/prjxray.git
Changed folder name for the 'database development process' of the docs and updated the index.rst page accordingly.
Also a few minor changes as requested by @mithro regarding the content itself and rearranged the paragraphs. Signed-off-by: Davide <davide.toldo@stud.tu-darmstadt.de>
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Overview
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Overview
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=========
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=========
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SymbiFlow/symbiflow-arch-defs
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^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
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This is where we describe the logical components in a device to VPR.
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* VtR stands for `Verilog to Routing <https://verilogtorouting.org/>`_,
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* VPR stands for VtR Place and Route.
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* VtR also has its own synthesis tool called ODIN-II, but we are using `Yosys <https://github.com/YosysHQ/yosys>`_ instead of that.
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SymbiFlow/prjxray/fuzzers/
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SymbiFlow/prjxray/fuzzers/
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^^^^^^^^^^^^^^^^^^^^^^^^^^^
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^^^^^^^^^^^^^^^^^^^^^^^^^^^
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Fuzzers are things that generate a design, feed it to Vivado, and look at the resulting bitstream to make some conclusion.
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Fuzzers are things that generate a design, feed it to Vivado, and look at the resulting bitstream to make some conclusion.
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@ -16,16 +25,11 @@ By looking at all the resulting specimens, you can correlate which bits in which
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Looking at the implemented design in Vivado with "Show Routing Resources" turned on is quite helpful in understanding what all choices exist.
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Looking at the implemented design in Vivado with "Show Routing Resources" turned on is quite helpful in understanding what all choices exist.
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SymbiFlow/symbiflow-arch-defs
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^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
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This is where we describe the logical components in a device to VPR.
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VPR stands for place and route software.
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SymbiFlow/prjxray/tools/
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SymbiFlow/prjxray/tools/
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^^^^^^^^^^^^^^^^^^^^^^^^^^^
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^^^^^^^^^^^^^^^^^^^^^^^^^^^
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Here, you can find various programs to work with bitstreams, mainly to assist building fuzzers.
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Here, you can find various programs to work with bitstreams, mainly to assist building fuzzers.
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SymbiFlow/minitests/roi_harness
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SymbiFlow/prjxray/minitests/roi_harness
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^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
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^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
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Shows how to use a bunch of tools together to patch an existing bitstream with hand-crafted FASM (FPGA assembler).
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Shows how to use a bunch of tools together to patch an existing bitstream with hand-crafted FASM (FPGA assembler).
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@ -26,4 +26,4 @@ to develop a free and open Verilog to bitstream toolchain for these devices.
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:maxdepth: 2
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:maxdepth: 2
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:caption: Database Development Process
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:caption: Database Development Process
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database development process/overview
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db_dev_process/overview
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