mirror of https://github.com/openXC7/prjxray.git
36 lines
1.9 KiB
ReStructuredText
36 lines
1.9 KiB
ReStructuredText
Overview
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=========
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SymbiFlow/symbiflow-arch-defs
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^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
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This is where we describe the logical components in a device to VPR.
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* VtR stands for `Verilog to Routing <https://verilogtorouting.org/>`_,
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* VPR stands for VtR Place and Route.
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* VtR also has its own synthesis tool called ODIN-II, but we are using `Yosys <https://github.com/YosysHQ/yosys>`_ instead of that.
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SymbiFlow/prjxray/fuzzers/
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^^^^^^^^^^^^^^^^^^^^^^^^^^^
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Fuzzers are things that generate a design, feed it to Vivado, and look at the resulting bitstream to make some conclusion.
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This is how the contents of the database are generated.
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The general idea behind fuzzers is to pick some element in the device (say a block RAM or IOB) to target.
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If you picked the IOB (no one is working on that yet), you'd write a design that is implemented in a specific IOB.
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Then you'd create a program that creates variations of the design (called specimens) that vary the design parameters, for example, changing the configuration of a single pin.
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A lot of this program is TCL that runs inside Vivado to change the design parameters, because it is a bit faster to load in one Verilog model and use TCL to replicate it with varying inputs instead of having different models and loading them individually.
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By looking at all the resulting specimens, you can correlate which bits in which frame correspond to a particular choice in the design.
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Looking at the implemented design in Vivado with "Show Routing Resources" turned on is quite helpful in understanding what all choices exist.
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SymbiFlow/prjxray/tools/
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^^^^^^^^^^^^^^^^^^^^^^^^^^^
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Here, you can find various programs to work with bitstreams, mainly to assist building fuzzers.
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SymbiFlow/prjxray/minitests/roi_harness
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^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
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Shows how to use a bunch of tools together to patch an existing bitstream with hand-crafted FASM (FPGA assembler).
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