diff --git a/docs/database development process/overview.rst b/docs/db_dev_process/overview.rst
similarity index 82%
rename from docs/database development process/overview.rst
rename to docs/db_dev_process/overview.rst
index 35f56b82..08e26a8d 100644
--- a/docs/database development process/overview.rst
+++ b/docs/db_dev_process/overview.rst
@@ -1,6 +1,15 @@
Overview
=========
+SymbiFlow/symbiflow-arch-defs
+^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
+This is where we describe the logical components in a device to VPR.
+
+* VtR stands for `Verilog to Routing `_,
+* VPR stands for VtR Place and Route.
+* VtR also has its own synthesis tool called ODIN-II, but we are using `Yosys `_ instead of that.
+
+
SymbiFlow/prjxray/fuzzers/
^^^^^^^^^^^^^^^^^^^^^^^^^^^
Fuzzers are things that generate a design, feed it to Vivado, and look at the resulting bitstream to make some conclusion.
@@ -16,16 +25,11 @@ By looking at all the resulting specimens, you can correlate which bits in which
Looking at the implemented design in Vivado with "Show Routing Resources" turned on is quite helpful in understanding what all choices exist.
-SymbiFlow/symbiflow-arch-defs
-^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
-This is where we describe the logical components in a device to VPR.
-VPR stands for place and route software.
-
SymbiFlow/prjxray/tools/
^^^^^^^^^^^^^^^^^^^^^^^^^^^
Here, you can find various programs to work with bitstreams, mainly to assist building fuzzers.
-SymbiFlow/minitests/roi_harness
-^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
+SymbiFlow/prjxray/minitests/roi_harness
+^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
Shows how to use a bunch of tools together to patch an existing bitstream with hand-crafted FASM (FPGA assembler).
diff --git a/docs/index.rst b/docs/index.rst
index b03a7a24..0a607e3c 100644
--- a/docs/index.rst
+++ b/docs/index.rst
@@ -26,4 +26,4 @@ to develop a free and open Verilog to bitstream toolchain for these devices.
:maxdepth: 2
:caption: Database Development Process
- database development process/overview
+ db_dev_process/overview