From a2d7149d30f19e42a2a4740c7641edeeb1dee151 Mon Sep 17 00:00:00 2001 From: John McMaster Date: Mon, 11 Dec 2017 13:21:45 -0800 Subject: [PATCH] clb_ram: NDI1MUX tests. Need to split out into dedicated test... Signed-off-by: John McMaster Signed-off-by: Tim 'mithro' Ansell --- minitests/clb_ram/.gitignore | 8 + minitests/clb_ram/runme.sh | 2 + minitests/clb_ram/top.v | 445 ++++++++++++++++++++++++----------- 3 files changed, 317 insertions(+), 138 deletions(-) create mode 100644 minitests/clb_ram/.gitignore diff --git a/minitests/clb_ram/.gitignore b/minitests/clb_ram/.gitignore new file mode 100644 index 00000000..82a01aa0 --- /dev/null +++ b/minitests/clb_ram/.gitignore @@ -0,0 +1,8 @@ +/.Xil +/design/ +/design.bit +/design.bits +/design.dcp +/usage_statistics_webtalk.* +/vivado* +/design.txt diff --git a/minitests/clb_ram/runme.sh b/minitests/clb_ram/runme.sh index 536f2346..7810c911 100755 --- a/minitests/clb_ram/runme.sh +++ b/minitests/clb_ram/runme.sh @@ -5,3 +5,5 @@ set -ex vivado -mode batch -source runme.tcl ${XRAY_BITREAD} -F $XRAY_ROI_FRAMES -o design.bits -z -y design.bit #${XRAY_SEGPRINT} design.bits SLICE_X16Y100 SLICE_X16Y101 SLICE_X16Y102 SLICE_X16Y103 +test -z $(fgrep CRITICAL vivado.log) + diff --git a/minitests/clb_ram/top.v b/minitests/clb_ram/top.v index 7ef5f1d9..a0daa02b 100644 --- a/minitests/clb_ram/top.v +++ b/minitests/clb_ram/top.v @@ -1,8 +1,15 @@ /* -RAM64M 64-Deep by 4-bit Wide Multi Port Random Access Memory (Select RAM) -RAM64X1D 64-Deep by 1-Wide Dual Port Static Synchronous RAM -RAM64X1S 64-Deep by 1-Wide Static Synchronous RAM -RAM64X1S_1 64-Deep by 1-Wide Static Synchronous RAM with Negative-Edge Clock +SLICEM at the following: +SLICE_XxY* +Where Y any value +x + Always even (ie 100, 102, 104, etc) + In our ROI + x = 6, 8, 10, 12, 14 + +SRL16E: LOC + BEL +SRLC32E: LOC + BEL +RAM64X1S: LOCs but doesn't BEL */ module top(input clk, stb, di, output do); @@ -34,69 +41,205 @@ module top(input clk, stb, di, output do); endmodule module roi(input clk, input [255:0] din, output [255:0] dout); + //ok + my_NDI1MUX_NMC31 #(.LOC("SLICE_X6Y100")) + my_NDI1MUX_NMC31(.clk(clk), .din(din[ 0 +: 8]), .dout(dout[ 0 +: 8])); /* - my_RAM64M #(.LOC("SLICE_X6Y100")) - my_RAM64M(.clk(clk), .din(din[ 0 +: 8]), .dout(dout[ 0 +: 8])); - my_RAM64X1S #(.LOC("SLICE_X6Y101")) - my_RAM64X1S(.clk(clk), .din(din[ 8 +: 8]), .dout(dout[ 8 +: 8])); - my_RAM64X1S_1 #(.LOC("SLICE_X6Y102")) - my_RAM64X1S_1(.clk(clk), .din(din[ 16 +: 8]), .dout(dout[ 16 +: 8])); - my_RAM64X2S #(.LOC("SLICE_X6Y103")) - my_RAM64X2S(.clk(clk), .din(din[ 24 +: 8]), .dout(dout[ 24 +: 8])); - my_RAM64X1D #(.LOC("SLICE_X6Y104")) - my_RAM64X1D(.clk(clk), .din(din[ 32 +: 8]), .dout(dout[ 32 +: 8])); - my_RAM128X1D #(.LOC("SLICE_X6Y105")) - my_RAM128X1D(.clk(clk), .din(din[ 40 +: 8]), .dout(dout[ 40 +: 8])); - */ - - /* - my_BDI1MUX_AI #(.LOC("SLICE_X6Y100"), .BEL("A6LUT")) - my_BDI1MUX_AI(.clk(clk), .din(din[ 0 +: 8]), .dout(dout[ 0 +: 8])); - my_BDI1MUX_BDI1 #(.LOC("SLICE_X6Y101"), .BELO("B6LUT"), .BELI("A6LUT")) - my_BDI1MUX_BDI1(.clk(clk), .din(din[ 8 +: 8]), .dout(dout[ 8 +: 8])); - my_BDI1MUX_BMC31 #(.LOC("SLICE_X6Y102"), .BELO("B6LUT"), .BELI("A6LUT")) - my_BDI1MUX_BMC31(.clk(clk), .din(din[ 16 +: 8]), .dout(dout[ 16 +: 8])); - */ - - /* - //BEL isn't taking effect - my_BDI1MUX_AI #(.LOC("SLICE_X6Y100"), .BEL("A6LUT")) - c0(.clk(clk), .din(din[ 0 +: 8]), .dout(dout[ 0 +: 8])); - my_BDI1MUX_AI #(.LOC("SLICE_X6Y101"), .BEL("B6LUT")) - c1(.clk(clk), .din(din[ 8 +: 8]), .dout(dout[ 8 +: 8])); - my_BDI1MUX_AI #(.LOC("SLICE_X6Y102"), .BEL("C6LUT")) - c2(.clk(clk), .din(din[ 16 +: 8]), .dout(dout[ 16 +: 8])); - my_BDI1MUX_AI #(.LOC("SLICE_X6Y103"), .BEL("D6LUT")) - c3(.clk(clk), .din(din[ 24 +: 8]), .dout(dout[ 24 +: 8])); + //Can't find a valid solution + my_NDI1MUX_NDI1 #(.LOC("SLICE_X6Y101")) + my_NDI1MUX_NDI1(.clk(clk), .din(din[ 8 +: 32]), .dout(dout[ 8 +: 8])); */ + my_NDI1MUX_NI #(.LOC("SLICE_X6Y102")) + my_NDI1MUX_NI(.clk(clk), .din(din[ 40 +: 8]), .dout(dout[ 40 +: 8])); + - /* - //BEL works - //No unknown bits - my_SRL16E #(.LOC("SLICE_X6Y100"), .BEL("A6LUT")) - c0(.clk(clk), .din(din[ 0 +: 8]), .dout(dout[ 0 +: 8])); - my_SRL16E #(.LOC("SLICE_X6Y101"), .BEL("B6LUT")) - c1(.clk(clk), .din(din[ 8 +: 8]), .dout(dout[ 8 +: 8])); - my_SRL16E #(.LOC("SLICE_X6Y102"), .BEL("C6LUT")) - c2(.clk(clk), .din(din[ 16 +: 8]), .dout(dout[ 16 +: 8])); - my_SRL16E #(.LOC("SLICE_X6Y103"), .BEL("D6LUT")) - c3(.clk(clk), .din(din[ 24 +: 8]), .dout(dout[ 24 +: 8])); + //ok + my_BDI1MUX_AI #(.LOC("SLICE_X8Y100"), .BEL("A6LUT")) + my_BDI1MUX_AI(.clk(clk), .din(din[ 64 +: 8]), .dout(dout[ 64 +: 8])); + */ + /* + //bad + my_BDI1MUX_BDI1 #(.LOC("SLICE_X8Y101"), .BELO("C6LUT"), .BELI("A6LUT")) + my_BDI1MUX_BDI1(.clk(clk), .din(din[ 72 +: 8]), .dout(dout[ 72 +: 8])); + */ + /* + //ok + my_BDI1MUX_BMC31 #(.LOC("SLICE_X8Y102"), .BELO("B6LUT"), .BELI("A6LUT")) + my_BDI1MUX_BMC31(.clk(clk), .din(din[ 80 +: 8]), .dout(dout[ 80 +: 8])); */ - - //BEL works - my_SRLC32E #(.LOC("SLICE_X6Y100"), .BEL("A6LUT")) - c0(.clk(clk), .din(din[ 0 +: 8]), .dout(dout[ 0 +: 8])); - my_SRLC32E #(.LOC("SLICE_X6Y101"), .BEL("B6LUT")) - c1(.clk(clk), .din(din[ 8 +: 8]), .dout(dout[ 8 +: 8])); - my_SRLC32E #(.LOC("SLICE_X6Y102"), .BEL("C6LUT")) - c2(.clk(clk), .din(din[ 16 +: 8]), .dout(dout[ 16 +: 8])); - my_SRLC32E #(.LOC("SLICE_X6Y103"), .BEL("D6LUT")) - c3(.clk(clk), .din(din[ 24 +: 8]), .dout(dout[ 24 +: 8])); endmodule -module my_SRLC32E (input clk, input [7:0] din, output [7:0] dout); +/**************************************************************************** +Tries to set all three muxes at once +****************************************************************************/ + +module my_NDI1MUX_NMC31 (input clk, input [7:0] din, output [7:0] dout); + parameter LOC = "SLICE_X6Y100"; + wire [3:0] q31; + + (* LOC=LOC, BEL="D6LUT" *) + SRLC32E #( + .INIT(32'h00000000), + .IS_CLK_INVERTED(1'b0) + ) lutd ( + .Q(dout[0]), + .Q31(q31[3]), + .A(din[4:0]), + .CE(din[5]), + .CLK(din[6]), + .D(din[7])); + (* LOC=LOC, BEL="C6LUT" *) + SRLC32E #( + .INIT(32'h00000000), + .IS_CLK_INVERTED(1'b0) + ) lutc ( + .Q(dout[1]), + .Q31(q31[2]), + .A(din[4:0]), + .CE(din[5]), + .CLK(din[6]), + //.D(din[7])); + .D(q31[3])); + (* LOC=LOC, BEL="B6LUT" *) + SRLC32E #( + .INIT(32'h00000000), + .IS_CLK_INVERTED(1'b0) + ) lutb ( + .Q(dout[2]), + .Q31(q31[1]), + .A(din[4:0]), + .CE(din[5]), + .CLK(din[6]), + //.D(din[7])); + .D(q31[2])); + (* LOC=LOC, BEL="A6LUT" *) + SRLC32E #( + .INIT(32'h00000000), + .IS_CLK_INVERTED(1'b0) + ) luta ( + .Q(dout[3]), + .Q31(q31[0]), + .A(din[4:0]), + .CE(din[5]), + .CLK(din[6]), + //.D(din[7])); + .D(q31[1])); +endmodule + +/* +//Cannot loc instance 'roi/my_NDI1MUX_NDI1/lutc' at site SLICE_X6Y100, +//Bel does not match with the valid locations at which this inst can be placed + +module my_NDI1MUX_NDI1 (input clk, input [31:0] din, output [7:0] dout); + parameter LOC = "SLICE_X6Y100"; + wire [3:0] q31; + + (* LOC=LOC, BEL="D6LUT" *) + SRLC32E #( + .INIT(32'h00000000), + .IS_CLK_INVERTED(1'b0) + ) lutd ( + .Q(dout[0]), + .Q31(q31[3]), + .A(din[4:0]), + .CE(din[5]), + .CLK(din[6]), + .D(din[7])); + (* LOC=LOC, BEL="C6LUT" *) + SRLC32E #( + .INIT(32'h00000000), + .IS_CLK_INVERTED(1'b0) + ) lutc ( + .Q(dout[1]), + .Q31(q31[2]), + .A(din[12:8]), + .CE(din[5]), + .CLK(din[6]), + .D(din[15])); + (* LOC=LOC, BEL="B6LUT" *) + SRLC32E #( + .INIT(32'h00000000), + .IS_CLK_INVERTED(1'b0) + ) lutb ( + .Q(dout[2]), + .Q31(q31[1]), + .A(din[20:16]), + .CE(din[5]), + .CLK(din[6]), + //.D(din[23])); + .D(q31[2])); + (* LOC=LOC, BEL="A6LUT" *) + SRLC32E #( + .INIT(32'h00000000), + .IS_CLK_INVERTED(1'b0) + ) luta ( + .Q(dout[3]), + .Q31(q31[0]), + .A(din[28:24]), + .CE(din[5]), + .CLK(din[6]), + //.D(din[31])); + .D(q31[2])); +endmodule +*/ + + +module my_NDI1MUX_NI (input clk, input [7:0] din, output [7:0] dout); + parameter LOC = "SLICE_X6Y100"; + + (* LOC=LOC, BEL="D6LUT" *) + SRLC32E #( + .INIT(32'h00000000), + .IS_CLK_INVERTED(1'b0) + ) lutd ( + .Q(dout[0]), + .Q31(), + .A(din[4:0]), + .CE(din[5]), + .CLK(din[6]), + .D(din[7])); + (* LOC=LOC, BEL="C6LUT" *) + SRLC32E #( + .INIT(32'h00000000), + .IS_CLK_INVERTED(1'b0) + ) lutc ( + .Q(dout[1]), + .Q31(), + .A(din[4:0]), + .CE(din[5]), + .CLK(din[6]), + .D(din[7])); + (* LOC=LOC, BEL="B6LUT" *) + SRLC32E #( + .INIT(32'h00000000), + .IS_CLK_INVERTED(1'b0) + ) lutb ( + .Q(dout[2]), + .Q31(), + .A(din[4:0]), + .CE(din[5]), + .CLK(din[6]), + .D(din[7])); + (* LOC=LOC, BEL="A6LUT" *) + SRLC32E #( + .INIT(32'h00000000), + .IS_CLK_INVERTED(1'b0) + ) luta ( + .Q(dout[3]), + .Q31(), + .A(din[4:0]), + .CE(din[5]), + .CLK(din[6]), + .D(din[7])); +endmodule + +/**************************************************************************** +Individual mux tests +****************************************************************************/ + +module my_BDI1MUX_AI (input clk, input [7:0] din, output [7:0] dout); parameter LOC = ""; parameter BEL="A6LUT"; @@ -115,89 +258,13 @@ module my_SRLC32E (input clk, input [7:0] din, output [7:0] dout); .D(din[7])); endmodule -module my_SRL16E (input clk, input [7:0] din, output [7:0] dout); - parameter LOC = ""; - parameter BEL="A6LUT"; - - (* LOC=LOC, BEL=BEL *) - SRL16E #( - ) SRL16E ( - .Q(dout[0]), - .A0(din[0]), - .A1(din[1]), - .A2(din[2]), - .A3(din[3]), - .CE(din[4]), - .CLK(din[5]), - .D(din[6])); -endmodule - - - -module my_BDI1MUX_AI (input clk, input [7:0] din, output [7:0] dout); - parameter LOC = ""; - parameter BEL="A6LUT"; - - (* LOC=LOC, BEL=BEL *) - RAM64X1S #( - ) RAM64X1S ( - .O(dout[0]), - .A0(din[0]), - .A1(din[1]), - .A2(din[2]), - .A3(din[3]), - .A4(din[4]), - .A5(din[5]), - .D(din[6]), - .WCLK(clk), - .WE(din[0])); -endmodule - -//bad -//Ended in D6LUT and A6LUT -/* -module my_BDI1MUX_BDI1 (input clk, input [7:0] din, output [7:0] dout); - parameter LOC = ""; - parameter BELO="B6LUT"; - parameter BELI="A6LUT"; - - wire da = din[6]; - - (* LOC=LOC, BEL=BELO *) - RAM64X1S #( - ) lutb ( - .O(dout[0]), - .A0(din[0]), - .A1(din[1]), - .A2(din[2]), - .A3(din[3]), - .A4(din[4]), - .A5(din[5]), - .D(da), - .WCLK(clk), - .WE(din[0])); - (* LOC=LOC, BEL=BELI *) - RAM64X1S #( - ) luta ( - .O(dout[1]), - .A0(din[0]), - .A1(din[1]), - .A2(din[2]), - .A3(din[3]), - .A4(din[4]), - .A5(din[5]), - .D(da), - .WCLK(clk), - .WE(din[0])); -endmodule -*/ -//Lets try CMC31 chaining instead module my_BDI1MUX_BDI1 (input clk, input [7:0] din, output [7:0] dout); parameter LOC = ""; parameter BELO="C6LUT"; parameter BELI="A6LUT"; - wire da = din[6]; + wire mc31c; + //wire da = din[6]; (* LOC=LOC, BEL=BELO *) SRLC32E #( @@ -220,7 +287,7 @@ module my_BDI1MUX_BDI1 (input clk, input [7:0] din, output [7:0] dout); .A(din[4:0]), .CE(din[5]), .CLK(din[6]), - .D(da)); + .D(mc31c)); endmodule //ok @@ -258,6 +325,87 @@ endmodule + + + + + + +/* +Old stuff +This is original file, move mux test out and restore this +*/ + + + + + + + + + + + /* + //BEL works + my_SRLC32E #(.LOC("SLICE_X6Y100"), .BEL("A6LUT")) + c0(.clk(clk), .din(din[ 0 +: 8]), .dout(dout[ 0 +: 8])); + my_SRLC32E #(.LOC("SLICE_X6Y101"), .BEL("B6LUT")) + c1(.clk(clk), .din(din[ 8 +: 8]), .dout(dout[ 8 +: 8])); + my_SRLC32E #(.LOC("SLICE_X6Y102"), .BEL("C6LUT")) + c2(.clk(clk), .din(din[ 16 +: 8]), .dout(dout[ 16 +: 8])); + my_SRLC32E #(.LOC("SLICE_X6Y103"), .BEL("D6LUT")) + c3(.clk(clk), .din(din[ 24 +: 8]), .dout(dout[ 24 +: 8])); + */ + +module my_SRLC32E (input clk, input [7:0] din, output [7:0] dout); + parameter LOC = ""; + parameter BEL="A6LUT"; + + wire mc31c; + + (* LOC=LOC, BEL=BEL *) + SRLC32E #( + .INIT(32'h00000000), + .IS_CLK_INVERTED(1'b0) + ) lut ( + .Q(dout[0]), + .Q31(mc31c), + .A(din[4:0]), + .CE(din[5]), + .CLK(din[6]), + .D(din[7])); +endmodule + + /* + //BEL works + //No unknown bits + my_SRL16E #(.LOC("SLICE_X6Y100"), .BEL("A6LUT")) + c0(.clk(clk), .din(din[ 0 +: 8]), .dout(dout[ 0 +: 8])); + my_SRL16E #(.LOC("SLICE_X6Y101"), .BEL("B6LUT")) + c1(.clk(clk), .din(din[ 8 +: 8]), .dout(dout[ 8 +: 8])); + my_SRL16E #(.LOC("SLICE_X6Y102"), .BEL("C6LUT")) + c2(.clk(clk), .din(din[ 16 +: 8]), .dout(dout[ 16 +: 8])); + my_SRL16E #(.LOC("SLICE_X6Y103"), .BEL("D6LUT")) + c3(.clk(clk), .din(din[ 24 +: 8]), .dout(dout[ 24 +: 8])); + */ + +module my_SRL16E (input clk, input [7:0] din, output [7:0] dout); + parameter LOC = ""; + parameter BEL="A6LUT"; + + (* LOC=LOC, BEL=BEL *) + SRL16E #( + ) SRL16E ( + .Q(dout[0]), + .A0(din[0]), + .A1(din[1]), + .A2(din[2]), + .A3(din[3]), + .CE(din[4]), + .CLK(din[5]), + .D(din[6])); +endmodule + module my_RAM64M (input clk, input [7:0] din, output [7:0] dout); parameter LOC = ""; parameter BEL="A6LUT"; @@ -282,6 +430,27 @@ module my_RAM64M (input clk, input [7:0] din, output [7:0] dout); endmodule +/* +RAM64M 64-Deep by 4-bit Wide Multi Port Random Access Memory (Select RAM) +RAM64X1D 64-Deep by 1-Wide Dual Port Static Synchronous RAM +RAM64X1S 64-Deep by 1-Wide Static Synchronous RAM +RAM64X1S_1 64-Deep by 1-Wide Static Synchronous RAM with Negative-Edge Clock +*/ + + /* + my_RAM64M #(.LOC("SLICE_X6Y100")) + my_RAM64M(.clk(clk), .din(din[ 0 +: 8]), .dout(dout[ 0 +: 8])); + my_RAM64X1S #(.LOC("SLICE_X6Y101")) + my_RAM64X1S(.clk(clk), .din(din[ 8 +: 8]), .dout(dout[ 8 +: 8])); + my_RAM64X1S_1 #(.LOC("SLICE_X6Y102")) + my_RAM64X1S_1(.clk(clk), .din(din[ 16 +: 8]), .dout(dout[ 16 +: 8])); + my_RAM64X2S #(.LOC("SLICE_X6Y103")) + my_RAM64X2S(.clk(clk), .din(din[ 24 +: 8]), .dout(dout[ 24 +: 8])); + my_RAM64X1D #(.LOC("SLICE_X6Y104")) + my_RAM64X1D(.clk(clk), .din(din[ 32 +: 8]), .dout(dout[ 32 +: 8])); + my_RAM128X1D #(.LOC("SLICE_X6Y105")) + my_RAM128X1D(.clk(clk), .din(din[ 40 +: 8]), .dout(dout[ 40 +: 8])); + */ module my_RAM64X1S (input clk, input [7:0] din, output [7:0] dout); parameter LOC = "";