diff --git a/minitests/litex/uart_ddr/arty/README.md b/minitests/litex/uart_ddr/arty/README.md
index ad84a751..f480e92f 100644
--- a/minitests/litex/uart_ddr/arty/README.md
+++ b/minitests/litex/uart_ddr/arty/README.md
@@ -1,13 +1,22 @@
 # LiteX UART DDR minitest
 
-
-
 This test aims at providing a minimal DDR design.
 The design is tested with a python script that provides memory control signals to the DDR controller
 using an UART bridge.
 
 The script performs the calbiration process, therfore it looks for the bitslip as well as the delay values.
 
+### Litex environment
+
+The litex module used is LiteDRAM, which should be checked-out at the correct commit:
+
+    | Repo URL | SHA |
+    |    ---   | --- |
+    | <https://github.com/antmicro/litex>         | 3350d33  |
+    | <https://github.com/enjoy-digital/litedram> | d8f3feb  |
+    | <https://github.com/m-labs/migen>           | d11565a  |
+
+
 ### Implementation
 
 There are two different ways to test this design:
diff --git a/minitests/litex/uart_ddr/arty/scripts/Makefile b/minitests/litex/uart_ddr/arty/scripts/Makefile
index 430e7589..173f0676 100644
--- a/minitests/litex/uart_ddr/arty/scripts/Makefile
+++ b/minitests/litex/uart_ddr/arty/scripts/Makefile
@@ -1,5 +1,6 @@
 litex/litex/tools/litex_client.py:
 	git clone https://github.com/enjoy-digital/litex.git
+	cd litex && git checkout 3350d33 && cd ../
 
 test_dram: litex/litex/tools/litex_client.py
 	./test_sdram.py