From 8a7e7664f8943e0e5dc50bf5d7e5f3e1ff10cef4 Mon Sep 17 00:00:00 2001 From: Alessandro Comodi Date: Mon, 3 Feb 2020 17:17:35 +0100 Subject: [PATCH] uart_ddr: checking out litex at specific commits Signed-off-by: Alessandro Comodi --- minitests/litex/uart_ddr/arty/README.md | 13 +++++++++++-- minitests/litex/uart_ddr/arty/scripts/Makefile | 1 + 2 files changed, 12 insertions(+), 2 deletions(-) diff --git a/minitests/litex/uart_ddr/arty/README.md b/minitests/litex/uart_ddr/arty/README.md index ad84a751..f480e92f 100644 --- a/minitests/litex/uart_ddr/arty/README.md +++ b/minitests/litex/uart_ddr/arty/README.md @@ -1,13 +1,22 @@ # LiteX UART DDR minitest - - This test aims at providing a minimal DDR design. The design is tested with a python script that provides memory control signals to the DDR controller using an UART bridge. The script performs the calbiration process, therfore it looks for the bitslip as well as the delay values. +### Litex environment + +The litex module used is LiteDRAM, which should be checked-out at the correct commit: + + | Repo URL | SHA | + | --- | --- | + | | 3350d33 | + | | d8f3feb | + | | d11565a | + + ### Implementation There are two different ways to test this design: diff --git a/minitests/litex/uart_ddr/arty/scripts/Makefile b/minitests/litex/uart_ddr/arty/scripts/Makefile index 430e7589..173f0676 100644 --- a/minitests/litex/uart_ddr/arty/scripts/Makefile +++ b/minitests/litex/uart_ddr/arty/scripts/Makefile @@ -1,5 +1,6 @@ litex/litex/tools/litex_client.py: git clone https://github.com/enjoy-digital/litex.git + cd litex && git checkout 3350d33 && cd ../ test_dram: litex/litex/tools/litex_client.py ./test_sdram.py