mirror of https://github.com/openXC7/prjxray.git
fixedpnr: fix latch INV/INIT polarity
Signed-off-by: John McMaster <JohnDMcMaster@gmail.com> Signed-off-by: Tim 'mithro' Ansell <mithro@mithis.com>
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@ -7,4 +7,17 @@ for ff in fdre fdse fdce fdce_inv fdpe ldce ldpe; do
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${XRAY_SEGPRINT} -z design_$ff.bits >design_$ff.seg
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${XRAY_SEGPRINT} -z design_$ff.bits >design_$ff.seg
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done
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done
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diff -u design_fdre.bits design_fdse.bits
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# Clock inverter bit
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diff design_fdce.seg design_fdce_inv.seg || true
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# Bits set on FF's are a superset of FDPE
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# FDSE has the most bits set
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diff design_fdpe.seg design_fdse.seg || true
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diff design_fdpe.seg design_fdce.seg || true
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diff design_fdpe.seg design_fdre.seg || true
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# the latch bit
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diff design_fdpe.seg design_ldpe.seg || true
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# LDPE has one more bit pair set than LDCE
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# This is the same pair FDRE/LDCE have
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diff design_ldpe.seg design_ldce.seg || true
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@ -1,7 +1,8 @@
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module top(input clk, ce, sr, d, output q);
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module top(input clk, ce, sr, d, output q);
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(* LOC="SLICE_X16Y100", BEL="AFF", DONT_TOUCH *)
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(* LOC="SLICE_X16Y100", BEL="AFF", DONT_TOUCH *)
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LDCE ff (
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//Keep inverter off
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LDCE_1 ff (
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.G(clk),
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.G(clk),
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.GE(ce),
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.GE(ce),
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.CLR(sr),
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.CLR(sr),
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@ -1,7 +1,8 @@
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module top(input clk, ce, sr, d, output q);
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module top(input clk, ce, sr, d, output q);
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(* LOC="SLICE_X16Y100", BEL="AFF", DONT_TOUCH *)
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(* LOC="SLICE_X16Y100", BEL="AFF", DONT_TOUCH *)
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LDPE ff (
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//Keep inverter off
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LDPE_1 ff (
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.G(clk),
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.G(clk),
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.GE(ce),
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.GE(ce),
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.PRE(sr),
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.PRE(sr),
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