mirror of https://github.com/openXC7/prjxray.git
ffprim: fix remaining issues
Signed-off-by: John McMaster <JohnDMcMaster@gmail.com> Signed-off-by: Tim 'mithro' Ansell <mithro@mithis.com>
This commit is contained in:
John McMaster
Tim 'mithro' Ansell
parent
1e2041c447
commit
ee3613e047
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@ -10,31 +10,53 @@ More research needed
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CLB.SLICE_X0.AFF.FF_INV_CLK 00_51
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CLB.SLICE_X0.FF_FDCE 00_21 00_24 00_25 00_26 00_29 00_35 29_01 29_12 30_01 30_03
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CLB.SLICE_X0.FF_FDPE 00_21 00_24 00_25 00_26 00_29 00_35 29_01 30_01
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CLB.SLICE_X0.FF_FDRE 00_21 00_24 00_25 00_26 00_29 29_01 29_12 30_01 30_03
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CLB.SLICE_X0.FF_FDSE 00_21 00_24 00_25 00_26 00_29 00_35 29_01 30_01
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CLB.SLICE_X0.FF_USED 00_21 00_24 00_25 00_26 00_29 29_01 30_01
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CLB.SLICE_X1.AFF.FF_INV_CLK <0 candidates>
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CLB.SLICE_X1.FF_FDCE 00_21 00_24 00_25 00_26 00_29 29_01 30_01 30_04 30_15
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CLB.SLICE_X1.FF_FDPE 00_21 00_24 00_25 00_26 00_29 29_01 30_01
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CLB.SLICE_X1.FF_FDRE 00_21 00_24 00_25 00_26 00_29 00_31 29_01 30_01 30_04 30_15
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CLB.SLICE_X1.FF_FDSE 00_21 00_24 00_25 00_26 00_29 00_31 29_01 30_01
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CLB.SLICE_X1.FF_USED 00_21 00_24 00_25 00_26 00_29 29_01 30_01
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FSYNC LATCH ZRESET
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Sample 00_48 30_32 30_12
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FDPE
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FDSE X
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FDRE X X
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FDCE X
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LDCE X X
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LDPE X
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Following bits are always present with a FF
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00_21
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00_24
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00_25
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00_26
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00_29
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29_01
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30_01
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Interesting bits are then
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CLB.SLICE_X0.FF_FDCE 00_35 29_12 30_03
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CLB.SLICE_X0.FF_FDPE 00_35
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CLB.SLICE_X0.FF_FDSE 00_35
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CLB.SLICE_X0.FF_FDRE 29_12 30_03
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CLB.SLICE_X0.A5FF.ZINIT 31_06
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CLB.SLICE_X0.A5FF.ZRESET 01_07
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CLB.SLICE_X0.AFF.ZINIT 31_03
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CLB.SLICE_X0.AFF.ZRESET 30_12
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CLB.SLICE_X0.B5FF.ZINIT 31_22
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CLB.SLICE_X0.B5FF.ZRESET 01_19
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CLB.SLICE_X0.BFF.ZINIT 31_28
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CLB.SLICE_X0.BFF.ZRESET 30_30
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CLB.SLICE_X0.C5FF.ZINIT 31_41
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CLB.SLICE_X0.C5FF.ZRESET 01_47
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CLB.SLICE_X0.CFF.ZINIT 31_33
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CLB.SLICE_X0.CFF.ZRESET 30_33
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CLB.SLICE_X0.CLKINV 01_51
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CLB.SLICE_X0.D5FF.ZINIT 31_51
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CLB.SLICE_X0.D5FF.ZRESET 01_55
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CLB.SLICE_X0.DFF.ZINIT 31_58
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CLB.SLICE_X0.DFF.ZRESET 30_50
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CLB.SLICE_X0.FFSYNC 00_48
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CLB.SLICE_X0.LATCH 30_32
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CLB.SLICE_X1.A5FF.ZINIT 31_05
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CLB.SLICE_X1.A5FF.ZRESET 01_03
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CLB.SLICE_X1.AFF.ZINIT 31_04
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CLB.SLICE_X1.AFF.ZRESET 31_15
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CLB.SLICE_X1.B5FF.ZINIT 31_23
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CLB.SLICE_X1.B5FF.ZRESET 00_16
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CLB.SLICE_X1.BFF.ZINIT 31_29
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CLB.SLICE_X1.BFF.ZRESET 31_30
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CLB.SLICE_X1.C5FF.ZINIT 31_42
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CLB.SLICE_X1.C5FF.ZRESET 00_44
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CLB.SLICE_X1.CFF.ZINIT 31_34
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CLB.SLICE_X1.CFF.ZRESET 30_34
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CLB.SLICE_X1.CLKINV 00_52
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CLB.SLICE_X1.D5FF.ZINIT 31_52
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CLB.SLICE_X1.D5FF.ZRESET 00_56
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CLB.SLICE_X1.DFF.ZINIT 31_59
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CLB.SLICE_X1.DFF.ZRESET 31_50
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CLB.SLICE_X1.FFSYNC 01_31
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CLB.SLICE_X1.LATCH 31_32
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@ -1,5 +1,14 @@
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#!/usr/bin/env python3
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'''
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FDCE Primitive: D Flip-Flop with Clock Enable and Asynchronous Clear
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FDPE Primitive: D Flip-Flop with Clock Enable and Asynchronous Preset
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FDRE Primitive: D Flip-Flop with Clock Enable and Synchronous Reset
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FDSE Primitive: D Flip-Flop with Clock Enable and Synchronous Set
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LDCE Primitive: Transparent Data Latch with Asynchronous Clear and Gate Enable
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LDPE Primitive: Transparent Data Latch with Asynchronous Preset and Gate Enable
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'''
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from prims import *
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import sys, re
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@ -18,6 +27,29 @@ def ones(l):
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ret.append(x + '_1')
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return ret
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def loadtop():
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'''
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i,prim,loc,bel
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0,FDPE,SLICE_X12Y100,C5FF
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1,FDPE,SLICE_X15Y100,A5FF
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2,FDPE_1,SLICE_X16Y100,B5FF
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3,LDCE_1,SLICE_X17Y100,BFF
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'''
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f = open('top.txt', 'r')
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f.readline()
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ret = {}
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for l in f:
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i,prim,loc,bel,init = l.split(",")
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i = int(i)
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init = int(init)
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ret[loc] = (i,prim,loc,bel,init)
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return ret
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top = loadtop()
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def vs2i(s):
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return {"1'b0": 0, "1'b1": 1}[s]
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print("Loading tags from design.txt")
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with open("design.txt", "r") as f:
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for line in f:
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@ -33,6 +65,7 @@ with open("design.txt", "r") as f:
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grid_x = line[2]
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grid_y = line[3]
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# Other code uses BEL name
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# SLICE_X12Y137/D5FF
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site_ff_name = line[4]
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site, ff_name = site_ff_name.split('/')
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ff_type = line[5]
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@ -46,68 +79,42 @@ with open("design.txt", "r") as f:
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# 1'b1
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# cinv = int(line[9][-1])
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cinv = int(line[9])
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init = vs2i(line[10])
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#init = int(line[10])
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# A B C D
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which = ff_name[0]
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# Reduced test for now
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#if ff_name != 'AFF':
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# continue
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# LUT6 vs LUT5 FF
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is5 = '5' in ff_name
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#segmk.addtag(site, "FF_USED", used)
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if 1:
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# If unused mark all primitives as not present
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# Otherwise mark the primitive we are using
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if used:
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segmk.addtag(site, "%s.%s" % (ff_name, cel_prim), 1)
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if used:
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segmk.addtag(site, "%s.ZINIT" % ff_name, 1 ^ init)
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# CLKINV turns out to be more complicated than origianlly thought
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if isff(cel_prim):
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segmk.addtag(site, "CLKINV", cinv)
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else:
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for ffprim in ffprims:
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# FF's don't do 5's
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if isff(ffprim) or (isl(ffprim) and not is5):
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segmk.addtag(site, "%s.%s" % (ff_name, ffprim), 0)
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segmk.addtag(site, "CLKINV", 1 ^ cinv)
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# Theory:
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# FDPE represents none of the FF specific bits used
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# FDRE has all of the bits used
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if 0:
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# If unused mark all primitives as not present
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# Otherwise mark the primitive we are using
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# Should yield 3 bits
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if used:
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if cel_prim == 'FDPE':
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segmk.addtag(site, "%s.PRIM" % ff_name, 0)
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if cel_prim == 'FDRE':
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segmk.addtag(site, "%s.PRIM" % ff_name, 1)
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# FF specific test
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# Theory: FDSE and FDCE are the most and least encoded FF's
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if 1:
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# If unused mark all primitives as not present
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# Otherwise mark the primitive we are using
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# Should yield 3 bits
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if used and isff(cel_prim):
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# PRIM1 is now FFSYNC
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#segmk.addtag(site, "%s.PRIM1" % ff_name,
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# cel_prim in ('FDSE', 'FDRE'))
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segmk.addtag(site, "%s.PRIM2" % ff_name,
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cel_prim in ('FDCE', 'FDRE'))
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# Theory: there are some common enable bits
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'''
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00_48 30_32 30_12 31_03
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FDPE
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FDSE X
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FDRE X X X
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FDCE X X
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LDCE X X X
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LDPE X
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00_48 is shared between all X0 FFs
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'''
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if 1 and used:
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# Synchronous vs asynchronous FF
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# Unlike most bits, shared between all CLB FFs
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segmk.addtag(site, "FFSYNC",
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cel_prim in ('FDSE', 'FDRE'))
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# Latch bit
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# Only applies to LUT6 (non-5) FF's
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if not is5:
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segmk.addtag(site, "LATCH", isl(cel_prim))
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'''
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On name:
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The primitives you listed have a control input to set the FF value to zero (clear/reset),
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the other three primitives have a control input that sets the FF value to one.
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Z => inversion
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'''
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segmk.addtag(site, "%s.ZRESET" % ff_name,
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cel_prim in ('FDRE', 'FDCE', 'LDCE'))
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segmk.compile()
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segmk.write()
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@ -41,6 +41,7 @@ foreach ff $ffs {
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set bel_type [get_property TYPE $ff]
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set used [get_property IS_USED $ff]
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set usedstr ""
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if $used {
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set ffc [get_cells -of_objects $ff]
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set cell_bel [get_property BEL $ffc]
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@ -52,7 +53,10 @@ foreach ff $ffs {
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# Latches have gate pin
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set cpin [get_pins -of_objects $ffc -filter {REF_PIN_NAME == C || REF_PIN_NAME == G}]
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set cinv [get_property IS_INVERTED $cpin]
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set usedstr "$cell_bel $ref_name $cinv"
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set init [get_property INIT $ffc]
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set usedstr "$cell_bel $ref_name $cinv $init"
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}
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puts $fp "$type $tile $grid_x $grid_y $ff $bel_type $used $usedstr"
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}
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@ -7,6 +7,7 @@ def ones(l):
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ret.append(x + '_1')
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return ret
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# The complete primitive sets
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ffprims_fall = ones([
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'FD',
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'FDC',
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@ -19,12 +20,6 @@ ffprims_fall = ones([
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'FDS',
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'FDSE',
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])
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ffprims_f = [
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'FDRE',
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'FDSE',
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'FDCE',
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'FDPE',
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]
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ffprims_lall = ones([
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'LDC',
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'LDCE',
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@ -32,6 +27,14 @@ ffprims_lall = ones([
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'LDPE',
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'LDP',
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])
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# Base primitives
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ffprims_f = [
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'FDRE',
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'FDSE',
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'FDCE',
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'FDPE',
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]
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ffprims_l = [
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'LDCE',
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'LDPE',
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@ -16,6 +16,9 @@ print('//SLICEY: %s' % str(SLICEY))
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print('//SLICEN: %s' % str(SLICEN))
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print('//Requested CLBs: %s' % str(CLBN))
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f = open("top.txt", "w")
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f.write("i,prim,loc,bel,init\n")
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def gen_slices():
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for slicey in range(*SLICEY):
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for slicex in range(*SLICEX):
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@ -57,7 +60,7 @@ endmodule
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slices = gen_slices()
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print('module roi(input clk, input [%d:0] din, output [%d:0] dout);' % (DIN_N - 1, DOUT_N - 1))
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for i in range(CLBN):
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ffprim = random.choice(ffprims)
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ffprim = random.choice(ones(ffprims))
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# clb_FD clb_FD (.clk(clk), .din(din[ 0 +: 4]), .dout(dout[ 0]));
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# clb_FD_1 clb_FD_1 (.clk(clk), .din(din[ 4 +: 4]), .dout(dout[ 1]));
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loc = next(slices)
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@ -66,10 +69,12 @@ for i in range(CLBN):
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bel = random.choice(ff_bels)
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else:
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bel = random.choice(ff_bels_ffl)
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init = random.choice((0, 1))
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#bel = "AFF"
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print(' clb_%s' % ffprim)
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print(' #(.LOC("%s"), .BEL("%s"))' % (loc, bel))
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print(' #(.LOC("%s"), .BEL("%s"), .INIT(%d))' % (loc, bel, init))
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print(' clb_%d (.clk(clk), .din(din[ %d +: 4]), .dout(dout[ %d]));' % (i, 4 * i, 1 * i))
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f.write("%d,%s,%s,%s,%d\n" % (i, ffprim, loc, bel, init))
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print('''endmodule
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// ---------------------------------------------------------------------
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@ -80,7 +85,8 @@ print('''
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module clb_FD (input clk, input [3:0] din, output dout);
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parameter LOC="SLICE_X16Y100";
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parameter BEL="AFF";
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(* LOC=LOC, BEL=BEL, KEEP, DONT_TOUCH *)
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parameter INIT=1'b0;
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(* LOC=LOC, BEL=BEL, KEEP, DONT_TOUCH, INIT=INIT *)
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FD ff (
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.C(clk),
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.Q(dout),
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@ -91,7 +97,8 @@ module clb_FD (input clk, input [3:0] din, output dout);
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module clb_FD_1 (input clk, input [3:0] din, output dout);
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parameter LOC="SLICE_X16Y101";
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parameter BEL="AFF";
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(* LOC=LOC, BEL=BEL, KEEP, DONT_TOUCH *)
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parameter INIT=1'b0;
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(* LOC=LOC, BEL=BEL, KEEP, DONT_TOUCH, INIT=INIT *)
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FD_1 ff (
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.C(clk),
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.Q(dout),
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@ -102,7 +109,8 @@ module clb_FD_1 (input clk, input [3:0] din, output dout);
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module clb_FDC (input clk, input [3:0] din, output dout);
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parameter LOC="SLICE_X16Y102";
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parameter BEL="AFF";
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(* LOC=LOC, BEL=BEL, KEEP, DONT_TOUCH *)
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parameter INIT=1'b0;
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(* LOC=LOC, BEL=BEL, KEEP, DONT_TOUCH, INIT=INIT *)
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FDC ff (
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.C(clk),
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.Q(dout),
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@ -114,7 +122,8 @@ module clb_FDC (input clk, input [3:0] din, output dout);
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module clb_FDC_1 (input clk, input [3:0] din, output dout);
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parameter LOC="SLICE_X16Y103";
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parameter BEL="AFF";
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(* LOC=LOC, BEL=BEL, KEEP, DONT_TOUCH *)
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parameter INIT=1'b0;
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(* LOC=LOC, BEL=BEL, KEEP, DONT_TOUCH, INIT=INIT *)
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FDC_1 ff (
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.C(clk),
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.Q(dout),
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@ -126,7 +135,8 @@ module clb_FDC_1 (input clk, input [3:0] din, output dout);
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module clb_FDCE (input clk, input [3:0] din, output dout);
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parameter LOC="SLICE_X16Y104";
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parameter BEL="AFF";
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(* LOC=LOC, BEL=BEL, KEEP, DONT_TOUCH *)
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parameter INIT=1'b0;
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(* LOC=LOC, BEL=BEL, KEEP, DONT_TOUCH, INIT=INIT *)
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FDCE ff (
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.C(clk),
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.Q(dout),
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@ -139,7 +149,8 @@ module clb_FDCE (input clk, input [3:0] din, output dout);
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module clb_FDCE_1 (input clk, input [3:0] din, output dout);
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parameter LOC="SLICE_X16Y105";
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parameter BEL="AFF";
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(* LOC=LOC, BEL=BEL, KEEP, DONT_TOUCH *)
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parameter INIT=1'b0;
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(* LOC=LOC, BEL=BEL, KEEP, DONT_TOUCH, INIT=INIT *)
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FDCE_1 ff (
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.C(clk),
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.Q(dout),
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@ -152,7 +163,8 @@ module clb_FDCE_1 (input clk, input [3:0] din, output dout);
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module clb_FDE (input clk, input [3:0] din, output dout);
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parameter LOC="SLICE_X16Y106";
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parameter BEL="AFF";
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(* LOC=LOC, BEL=BEL, KEEP, DONT_TOUCH *)
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parameter INIT=1'b0;
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(* LOC=LOC, BEL=BEL, KEEP, DONT_TOUCH, INIT=INIT *)
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FDE ff (
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.C(clk),
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.Q(dout),
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@ -164,7 +176,8 @@ module clb_FDE (input clk, input [3:0] din, output dout);
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module clb_FDE_1 (input clk, input [3:0] din, output dout);
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parameter LOC="SLICE_X16Y107";
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parameter BEL="AFF";
|
||||
(* LOC=LOC, BEL=BEL, KEEP, DONT_TOUCH *)
|
||||
parameter INIT=1'b0;
|
||||
(* LOC=LOC, BEL=BEL, KEEP, DONT_TOUCH, INIT=INIT *)
|
||||
FDE_1 ff (
|
||||
.C(clk),
|
||||
.Q(dout),
|
||||
|
|
@ -176,7 +189,8 @@ module clb_FDE_1 (input clk, input [3:0] din, output dout);
|
|||
module clb_FDP (input clk, input [3:0] din, output dout);
|
||||
parameter LOC="SLICE_X16Y108";
|
||||
parameter BEL="AFF";
|
||||
(* LOC=LOC, BEL=BEL, KEEP, DONT_TOUCH *)
|
||||
parameter INIT=1'b0;
|
||||
(* LOC=LOC, BEL=BEL, KEEP, DONT_TOUCH, INIT=INIT *)
|
||||
FDP ff (
|
||||
.C(clk),
|
||||
.Q(dout),
|
||||
|
|
@ -188,7 +202,8 @@ module clb_FDP (input clk, input [3:0] din, output dout);
|
|||
module clb_FDP_1 (input clk, input [3:0] din, output dout);
|
||||
parameter LOC="SLICE_X16Y109";
|
||||
parameter BEL="AFF";
|
||||
(* LOC=LOC, BEL=BEL, KEEP, DONT_TOUCH *)
|
||||
parameter INIT=1'b0;
|
||||
(* LOC=LOC, BEL=BEL, KEEP, DONT_TOUCH, INIT=INIT *)
|
||||
FDP_1 ff (
|
||||
.C(clk),
|
||||
.Q(dout),
|
||||
|
|
@ -200,7 +215,8 @@ module clb_FDP_1 (input clk, input [3:0] din, output dout);
|
|||
module clb_FDPE (input clk, input [3:0] din, output dout);
|
||||
parameter LOC="SLICE_X16Y110";
|
||||
parameter BEL="AFF";
|
||||
(* LOC=LOC, BEL=BEL, KEEP, DONT_TOUCH *)
|
||||
parameter INIT=1'b0;
|
||||
(* LOC=LOC, BEL=BEL, KEEP, DONT_TOUCH, INIT=INIT *)
|
||||
FDPE ff (
|
||||
.C(clk),
|
||||
.Q(dout),
|
||||
|
|
@ -213,7 +229,8 @@ module clb_FDPE (input clk, input [3:0] din, output dout);
|
|||
module clb_FDPE_1 (input clk, input [3:0] din, output dout);
|
||||
parameter LOC="SLICE_X16Y111";
|
||||
parameter BEL="AFF";
|
||||
(* LOC=LOC, BEL=BEL, KEEP, DONT_TOUCH *)
|
||||
parameter INIT=1'b0;
|
||||
(* LOC=LOC, BEL=BEL, KEEP, DONT_TOUCH, INIT=INIT *)
|
||||
FDPE_1 ff (
|
||||
.C(clk),
|
||||
.Q(dout),
|
||||
|
|
@ -226,7 +243,8 @@ module clb_FDPE_1 (input clk, input [3:0] din, output dout);
|
|||
module clb_FDR (input clk, input [3:0] din, output dout);
|
||||
parameter LOC="SLICE_X16Y112";
|
||||
parameter BEL="AFF";
|
||||
(* LOC=LOC, BEL=BEL, KEEP, DONT_TOUCH *)
|
||||
parameter INIT=1'b0;
|
||||
(* LOC=LOC, BEL=BEL, KEEP, DONT_TOUCH, INIT=INIT *)
|
||||
FDR ff (
|
||||
.C(clk),
|
||||
.Q(dout),
|
||||
|
|
@ -238,7 +256,8 @@ module clb_FDR (input clk, input [3:0] din, output dout);
|
|||
module clb_FDR_1 (input clk, input [3:0] din, output dout);
|
||||
parameter LOC="SLICE_X16Y113";
|
||||
parameter BEL="AFF";
|
||||
(* LOC=LOC, BEL=BEL, KEEP, DONT_TOUCH *)
|
||||
parameter INIT=1'b0;
|
||||
(* LOC=LOC, BEL=BEL, KEEP, DONT_TOUCH, INIT=INIT *)
|
||||
FDR_1 ff (
|
||||
.C(clk),
|
||||
.Q(dout),
|
||||
|
|
@ -250,7 +269,8 @@ module clb_FDR_1 (input clk, input [3:0] din, output dout);
|
|||
module clb_FDRE (input clk, input [3:0] din, output dout);
|
||||
parameter LOC="SLICE_X16Y114";
|
||||
parameter BEL="AFF";
|
||||
(* LOC=LOC, BEL=BEL, KEEP, DONT_TOUCH *)
|
||||
parameter INIT=1'b0;
|
||||
(* LOC=LOC, BEL=BEL, KEEP, DONT_TOUCH, INIT=INIT *)
|
||||
FDRE ff (
|
||||
.C(clk),
|
||||
.Q(dout),
|
||||
|
|
@ -263,7 +283,8 @@ module clb_FDRE (input clk, input [3:0] din, output dout);
|
|||
module clb_FDRE_1 (input clk, input [3:0] din, output dout);
|
||||
parameter LOC="SLICE_X16Y115";
|
||||
parameter BEL="AFF";
|
||||
(* LOC=LOC, BEL=BEL, KEEP, DONT_TOUCH *)
|
||||
parameter INIT=1'b0;
|
||||
(* LOC=LOC, BEL=BEL, KEEP, DONT_TOUCH, INIT=INIT *)
|
||||
FDRE_1 ff (
|
||||
.C(clk),
|
||||
.Q(dout),
|
||||
|
|
@ -276,7 +297,8 @@ module clb_FDRE_1 (input clk, input [3:0] din, output dout);
|
|||
module clb_FDS (input clk, input [3:0] din, output dout);
|
||||
parameter LOC="SLICE_X16Y116";
|
||||
parameter BEL="AFF";
|
||||
(* LOC=LOC, BEL=BEL, KEEP, DONT_TOUCH *)
|
||||
parameter INIT=1'b0;
|
||||
(* LOC=LOC, BEL=BEL, KEEP, DONT_TOUCH, INIT=INIT *)
|
||||
FDS ff (
|
||||
.C(clk),
|
||||
.Q(dout),
|
||||
|
|
@ -288,7 +310,8 @@ module clb_FDS (input clk, input [3:0] din, output dout);
|
|||
module clb_FDS_1 (input clk, input [3:0] din, output dout);
|
||||
parameter LOC="SLICE_X16Y117";
|
||||
parameter BEL="AFF";
|
||||
(* LOC=LOC, BEL=BEL, KEEP, DONT_TOUCH *)
|
||||
parameter INIT=1'b0;
|
||||
(* LOC=LOC, BEL=BEL, KEEP, DONT_TOUCH, INIT=INIT *)
|
||||
FDS_1 ff (
|
||||
.C(clk),
|
||||
.Q(dout),
|
||||
|
|
@ -300,7 +323,8 @@ module clb_FDS_1 (input clk, input [3:0] din, output dout);
|
|||
module clb_FDSE (input clk, input [3:0] din, output dout);
|
||||
parameter LOC="SLICE_X16Y118";
|
||||
parameter BEL="AFF";
|
||||
(* LOC=LOC, BEL=BEL, KEEP, DONT_TOUCH *)
|
||||
parameter INIT=1'b0;
|
||||
(* LOC=LOC, BEL=BEL, KEEP, DONT_TOUCH, INIT=INIT *)
|
||||
FDSE ff (
|
||||
.C(clk),
|
||||
.Q(dout),
|
||||
|
|
@ -313,7 +337,8 @@ module clb_FDSE (input clk, input [3:0] din, output dout);
|
|||
module clb_FDSE_1 (input clk, input [3:0] din, output dout);
|
||||
parameter LOC="SLICE_X16Y119";
|
||||
parameter BEL="AFF";
|
||||
(* LOC=LOC, BEL=BEL, KEEP, DONT_TOUCH *)
|
||||
parameter INIT=1'b0;
|
||||
(* LOC=LOC, BEL=BEL, KEEP, DONT_TOUCH, INIT=INIT *)
|
||||
FDSE_1 ff (
|
||||
.C(clk),
|
||||
.Q(dout),
|
||||
|
|
@ -328,7 +353,8 @@ module clb_FDSE_1 (input clk, input [3:0] din, output dout);
|
|||
module clb_LDC (input clk, input [3:0] din, output dout);
|
||||
parameter LOC="SLICE_X16Y120";
|
||||
parameter BEL="AFF";
|
||||
(* LOC=LOC, BEL=BEL, KEEP, DONT_TOUCH *)
|
||||
parameter INIT=1'b0;
|
||||
(* LOC=LOC, BEL=BEL, KEEP, DONT_TOUCH, INIT=INIT *)
|
||||
LDC ff (
|
||||
.G(~clk),
|
||||
.Q(dout),
|
||||
|
|
@ -339,7 +365,8 @@ module clb_LDC (input clk, input [3:0] din, output dout);
|
|||
module clb_LDC_1 (input clk, input [3:0] din, output dout);
|
||||
parameter LOC="SLICE_X16Y121";
|
||||
parameter BEL="AFF";
|
||||
(* LOC=LOC, BEL=BEL, KEEP, DONT_TOUCH *)
|
||||
parameter INIT=1'b0;
|
||||
(* LOC=LOC, BEL=BEL, KEEP, DONT_TOUCH, INIT=INIT *)
|
||||
LDC_1 ff (
|
||||
.G(~clk),
|
||||
.Q(dout),
|
||||
|
|
@ -351,7 +378,8 @@ module clb_LDC_1 (input clk, input [3:0] din, output dout);
|
|||
module clb_LDCE (input clk, input [3:0] din, output dout);
|
||||
parameter LOC="SLICE_X16Y122";
|
||||
parameter BEL="AFF";
|
||||
(* LOC=LOC, BEL=BEL, KEEP, DONT_TOUCH *)
|
||||
parameter INIT=1'b0;
|
||||
(* LOC=LOC, BEL=BEL, KEEP, DONT_TOUCH, INIT=INIT *)
|
||||
LDCE ff (
|
||||
.G(~clk),
|
||||
//NOTE: diagram shows two outputs. Error?
|
||||
|
|
@ -364,7 +392,8 @@ module clb_LDCE (input clk, input [3:0] din, output dout);
|
|||
module clb_LDCE_1 (input clk, input [3:0] din, output dout);
|
||||
parameter LOC="SLICE_X16Y123";
|
||||
parameter BEL="AFF";
|
||||
(* LOC=LOC, BEL=BEL, KEEP, DONT_TOUCH *)
|
||||
parameter INIT=1'b0;
|
||||
(* LOC=LOC, BEL=BEL, KEEP, DONT_TOUCH, INIT=INIT *)
|
||||
LDCE_1 ff (
|
||||
.G(~clk),
|
||||
//NOTE: diagram shows two outputs. Error?
|
||||
|
|
@ -378,7 +407,8 @@ module clb_LDCE_1 (input clk, input [3:0] din, output dout);
|
|||
module clb_LDE (input clk, input [3:0] din, output dout);
|
||||
parameter LOC="SLICE_X16Y124";
|
||||
parameter BEL="AFF";
|
||||
(* LOC=LOC, BEL=BEL, KEEP, DONT_TOUCH *)
|
||||
parameter INIT=1'b0;
|
||||
(* LOC=LOC, BEL=BEL, KEEP, DONT_TOUCH, INIT=INIT *)
|
||||
LDE ff (
|
||||
.G(~clk),
|
||||
.Q(dout),
|
||||
|
|
@ -389,7 +419,8 @@ module clb_LDE (input clk, input [3:0] din, output dout);
|
|||
module clb_LDE_1 (input clk, input [3:0] din, output dout);
|
||||
parameter LOC="SLICE_X16Y125";
|
||||
parameter BEL="AFF";
|
||||
(* LOC=LOC, BEL=BEL, KEEP, DONT_TOUCH *)
|
||||
parameter INIT=1'b0;
|
||||
(* LOC=LOC, BEL=BEL, KEEP, DONT_TOUCH, INIT=INIT *)
|
||||
LDE_1 ff (
|
||||
.G(~clk),
|
||||
.Q(dout),
|
||||
|
|
@ -401,7 +432,8 @@ module clb_LDE_1 (input clk, input [3:0] din, output dout);
|
|||
module clb_LDP (input clk, input [3:0] din, output dout);
|
||||
parameter LOC="SLICE_X16Y126";
|
||||
parameter BEL="AFF";
|
||||
(* LOC=LOC, BEL=BEL, KEEP, DONT_TOUCH *)
|
||||
parameter INIT=1'b0;
|
||||
(* LOC=LOC, BEL=BEL, KEEP, DONT_TOUCH, INIT=INIT *)
|
||||
LDP ff (
|
||||
.G(~clk),
|
||||
.Q(dout),
|
||||
|
|
@ -412,7 +444,8 @@ module clb_LDP (input clk, input [3:0] din, output dout);
|
|||
module clb_LDP_1 (input clk, input [3:0] din, output dout);
|
||||
parameter LOC="SLICE_X16Y127";
|
||||
parameter BEL="AFF";
|
||||
(* LOC=LOC, BEL=BEL, KEEP, DONT_TOUCH *)
|
||||
parameter INIT=1'b0;
|
||||
(* LOC=LOC, BEL=BEL, KEEP, DONT_TOUCH, INIT=INIT *)
|
||||
LDP_1 ff (
|
||||
.G(~clk),
|
||||
.Q(dout),
|
||||
|
|
@ -424,7 +457,8 @@ module clb_LDP_1 (input clk, input [3:0] din, output dout);
|
|||
module clb_LDPE (input clk, input [3:0] din, output dout);
|
||||
parameter LOC="SLICE_X16Y128";
|
||||
parameter BEL="AFF";
|
||||
(* LOC=LOC, BEL=BEL, KEEP, DONT_TOUCH *)
|
||||
parameter INIT=1'b0;
|
||||
(* LOC=LOC, BEL=BEL, KEEP, DONT_TOUCH, INIT=INIT *)
|
||||
LDPE ff (
|
||||
.G(~clk),
|
||||
.Q(dout),
|
||||
|
|
@ -436,7 +470,8 @@ module clb_LDPE (input clk, input [3:0] din, output dout);
|
|||
module clb_LDPE_1 (input clk, input [3:0] din, output dout);
|
||||
parameter LOC="SLICE_X16Y129";
|
||||
parameter BEL="AFF";
|
||||
(* LOC=LOC, BEL=BEL, KEEP, DONT_TOUCH *)
|
||||
parameter INIT=1'b0;
|
||||
(* LOC=LOC, BEL=BEL, KEEP, DONT_TOUCH, INIT=INIT *)
|
||||
LDPE_1 ff (
|
||||
.G(~clk),
|
||||
.Q(dout),
|
||||
|
|
|
|||
Loading…
Reference in New Issue