diff --git a/minitests/fixedpnr/runme.sh b/minitests/fixedpnr/runme.sh
index c2f1fb47..54e8e623 100755
--- a/minitests/fixedpnr/runme.sh
+++ b/minitests/fixedpnr/runme.sh
@@ -7,4 +7,17 @@ for ff in fdre fdse fdce fdce_inv fdpe ldce ldpe; do
     ${XRAY_SEGPRINT} -z design_$ff.bits >design_$ff.seg
 done
 
-diff -u design_fdre.bits design_fdse.bits
+# Clock inverter bit
+diff design_fdce.seg design_fdce_inv.seg || true
+# Bits set on FF's are a superset of FDPE
+# FDSE has the most bits set
+diff design_fdpe.seg design_fdse.seg || true
+diff design_fdpe.seg design_fdce.seg || true
+diff design_fdpe.seg design_fdre.seg || true
+
+# the latch bit
+diff design_fdpe.seg design_ldpe.seg || true
+# LDPE has one more bit pair set than LDCE
+# This is the same pair FDRE/LDCE have
+diff design_ldpe.seg design_ldce.seg || true
+
diff --git a/minitests/fixedpnr/top_ldce.v b/minitests/fixedpnr/top_ldce.v
index d1708512..a283c108 100644
--- a/minitests/fixedpnr/top_ldce.v
+++ b/minitests/fixedpnr/top_ldce.v
@@ -1,7 +1,8 @@
 
 module top(input clk, ce, sr, d, output q);
 	(* LOC="SLICE_X16Y100", BEL="AFF", DONT_TOUCH *)
-	LDCE ff (
+	//Keep inverter off
+	LDCE_1 ff (
 		.G(clk),
 		.GE(ce),
 		.CLR(sr),
diff --git a/minitests/fixedpnr/top_ldpe.v b/minitests/fixedpnr/top_ldpe.v
index b068a09f..43c5e8d3 100644
--- a/minitests/fixedpnr/top_ldpe.v
+++ b/minitests/fixedpnr/top_ldpe.v
@@ -1,7 +1,8 @@
 
 module top(input clk, ce, sr, d, output q);
 	(* LOC="SLICE_X16Y100", BEL="AFF", DONT_TOUCH *)
-	LDPE ff (
+	//Keep inverter off
+	LDPE_1 ff (
 		.G(clk),
 		.GE(ce),
 		.PRE(sr),