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tilegrid: fix BRAM CLB_IO_CLK height 

Signed-off-by: John McMaster <johndmcmaster@gmail.com>
This commit is contained in:
John McMaster 2018-10-23 23:23:45 -07:00
parent 6d24fdbaff
commit 671a55705f
1 changed files with 1 additions and 1 deletions
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2
fuzzers/005-tilegrid/generate.py
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@ -486,7 +486,7 @@ def db_add_bits(database, segments):
("CLBLM", "CLB_IO_CLK"): (36, 2, 2),
("HCLK", "CLB_IO_CLK"): (26, 1, 1),
("INT", "CLB_IO_CLK"): (28, 2, 2),
("BRAM", "CLB_IO_CLK"): (28, 2, None),
("BRAM", "CLB_IO_CLK"): (28, 10, None),
("BRAM", "BLOCK_RAM"): (128, 10, None),
("DSP", "CLB_IO_CLK"): (28, 2, 10),
("INT_INTERFACE", "CLB_IO_CLK"): (28, 2, None),