mirror of https://github.com/openXC7/prjxray.git
bram-config: baseline workflow
Signed-off-by: John McMaster <johndmcmaster@gmail.com>
This commit is contained in:
John McMaster
parent
136221fa6f
commit
6d24fdbaff
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@ -0,0 +1,2 @@
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/specimen_[0-9][0-9][0-9]/
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/seg_clbl[lm].segbits
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@ -0,0 +1,20 @@
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N := 1
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SPECIMENS := $(addprefix specimen_,$(shell seq -f '%03.0f' $(N)))
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SPECIMENS_OK := $(addsuffix /OK,$(SPECIMENS))
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database: $(SPECIMENS_OK)
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${XRAY_SEGMATCH} -o seg_bramx.block_ram.segbits $(addsuffix /segdata_bram_[lr].txt,$(SPECIMENS))
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pushdb:
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${XRAY_MERGEDB} bram_l.block_ram seg_bramx.block_ram.segbits
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${XRAY_MERGEDB} bram_r.block_ram seg_bramx.block_ram.segbits
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$(SPECIMENS_OK):
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bash generate.sh $(subst /OK,,$@)
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touch $@
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clean:
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rm -rf specimen_[0-9][0-9][0-9]/ seg_*.segbits vivado*.log vivado_*.str vivado*.jou design *.bits *.dcp *.bit top.v
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.PHONY: database pushdb clean
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@ -0,0 +1,2 @@
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Solves for BRAM configuration bits (18K vs 36K, etc)
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@ -0,0 +1,34 @@
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#!/usr/bin/env python3
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import json
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from prjxray.segmaker import Segmaker
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from prjxray import verilog
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segmk = Segmaker("design.bits", verbose=True)
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print("Loading tags")
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f = open('params.jl', 'r')
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f.readline()
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for l in f:
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j = json.loads(l)
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ps = j['params']
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assert j['module'] == 'my_RAMB36E1'
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site = verilog.unquote(ps['LOC'])
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ks = [
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'IS_CLKARDCLK_INVERTED',
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'IS_CLKBWRCLK_INVERTED',
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'IS_ENARDEN_INVERTED',
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'IS_ENBWREN_INVERTED',
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'IS_RSTRAMARSTRAM_INVERTED',
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'IS_RSTRAMB_INVERTED',
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'IS_RSTREGARSTREG_INVERTED',
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'IS_RSTREGB_INVERTED',
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]
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for k in ks:
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segmk.add_site_tag(site, k, verilog.parsei(ps[k]))
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segmk.compile()
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segmk.write()
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@ -0,0 +1,16 @@
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#!/bin/bash
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set -ex
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source ${XRAY_GENHEADER}
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python3 ../top.py >top.v
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vivado -mode batch -source ../generate.tcl
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test -z "$(fgrep CRITICAL vivado.log)"
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for x in design*.bit; do
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${XRAY_BITREAD} -F $XRAY_ROI_FRAMES -o ${x}s -z -y $x
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done
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python3 ../generate.py
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@ -0,0 +1,26 @@
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create_project -force -part $::env(XRAY_PART) design design
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read_verilog top.v
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synth_design -top top
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set_property -dict "PACKAGE_PIN $::env(XRAY_PIN_00) IOSTANDARD LVCMOS33" [get_ports clk]
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set_property -dict "PACKAGE_PIN $::env(XRAY_PIN_01) IOSTANDARD LVCMOS33" [get_ports stb]
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set_property -dict "PACKAGE_PIN $::env(XRAY_PIN_02) IOSTANDARD LVCMOS33" [get_ports di]
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set_property -dict "PACKAGE_PIN $::env(XRAY_PIN_03) IOSTANDARD LVCMOS33" [get_ports do]
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create_pblock roi
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set_property EXCLUDE_PLACEMENT 1 [get_pblocks roi]
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add_cells_to_pblock [get_pblocks roi] [get_cells roi]
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resize_pblock [get_pblocks roi] -add "$::env(XRAY_ROI)"
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set_property CFGBVS VCCO [current_design]
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set_property CONFIG_VOLTAGE 3.3 [current_design]
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set_property BITSTREAM.GENERAL.PERFRAMECRC YES [current_design]
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set_property CLOCK_DEDICATED_ROUTE FALSE [get_nets clk_IBUF]
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place_design
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route_design
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write_checkpoint -force design.dcp
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write_bitstream -force design.bit
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@ -0,0 +1,266 @@
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import os
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import random
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random.seed(int(os.getenv("SEED"), 16))
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from prjxray import util
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from prjxray import verilog
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import sys
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import json
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def gen_bram18():
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# yield "RAMB18_X%dY%d" % (x, y)
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for _tile_name, site_name, _site_type in util.get_roi().gen_sites(
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['RAMB18E1']):
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yield site_name
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def gen_bram36():
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#yield "RAMB36_X%dY%d" % (x, y)
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for _tile_name, site_name, _site_type in util.get_roi().gen_sites(
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['RAMBFIFO36E1']):
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yield site_name
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def gen_brams():
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'''
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Correctly assign a site to either bram36 or 2x bram18
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'''
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#for _tile_name, site_name, _site_type in util.get_roi().gen_tiles():
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for site in gen_bram36():
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yield ('RAMBFIFO36E1', site)
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brams = list(gen_brams())
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DUTN = len(brams)
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DIN_N = DUTN * 8
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DOUT_N = DUTN * 8
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verilog.top_harness(DIN_N, DOUT_N)
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f = open('params.jl', 'w')
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f.write('module,loc,params\n')
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print(
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'module roi(input clk, input [%d:0] din, output [%d:0] dout);' %
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(DIN_N - 1, DOUT_N - 1))
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def vrandbit():
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if random.randint(0, 1):
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return "1'b1"
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else:
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return "1'b0"
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for loci, (site_type, site) in enumerate(brams):
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def place_bram18():
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assert 0, 'FIXME'
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def place_bram36():
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ports = {
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'clk': 'clk',
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'din': 'din[ %d +: 8]' % (8 * loci, ),
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'dout': 'dout[ %d +: 8]' % (8 * loci, ),
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}
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params = {
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'LOC': verilog.quote(site),
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'IS_CLKARDCLK_INVERTED': vrandbit(),
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'IS_CLKBWRCLK_INVERTED': vrandbit(),
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'IS_ENARDEN_INVERTED': vrandbit(),
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'IS_ENBWREN_INVERTED': vrandbit(),
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'IS_RSTRAMARSTRAM_INVERTED': vrandbit(),
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'IS_RSTRAMB_INVERTED': vrandbit(),
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'IS_RSTREGARSTREG_INVERTED': vrandbit(),
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'IS_RSTREGB_INVERTED': vrandbit(),
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'RAM_MODE': '"TDP"',
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'WRITE_MODE_A': '"WRITE_FIRST"',
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'WRITE_MODE_B': '"WRITE_FIRST"',
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}
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return ('my_RAMB36E1', ports, params)
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modname, ports, params = {
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'RAMB18E1': place_bram18,
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'RAMBFIFO36E1': place_bram36,
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}[site_type]()
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verilog.instance(modname, 'inst_%u' % loci, ports, params=params)
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j = {'module': modname, 'i': loci, 'params': params}
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f.write('%s\n' % (json.dumps(j)))
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print('')
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'''
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def randbits(n):
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return ''.join([random.choice(('0', '1')) for _x in range(n)])
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loci = 0
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def make(module, gen_locs, pdatan, datan):
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global loci
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for loci, loc in enumerate(gen_locs()):
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if loci >= DUTN:
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break
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pdata = randbits(pdatan * 0x100)
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data = randbits(datan * 0x100)
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print(' %s #(' % module)
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for i in range(pdatan):
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print(
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" .INITP_%02X(256'b%s)," %
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(i, pdata[i * 256:(i + 1) * 256]))
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for i in range(datan):
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print(
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" .INIT_%02X(256'b%s)," %
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(i, data[i * 256:(i + 1) * 256]))
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print(' .LOC("%s"))' % (loc, ))
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print(
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' inst_%d (.clk(clk), .din(din[ %d +: 8]), .dout(dout[ %d +: 8]));'
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% (loci, 8 * loci, 8 * loci))
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f.write('%s,%s,%s,%s\n' % (module, loc, pdata, data))
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print('')
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loci += 1
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assert loci == DUTN
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#make('my_RAMB18E1', gen_bram18, 0x08, 0x40)
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make('my_RAMB36E1', gen_bram36, 0x10, 0x80)
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'''
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f.close()
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print(
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'''endmodule
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// ---------------------------------------------------------------------
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''')
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# RAMB18E1
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print(
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'''
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module my_RAMB18E1 (input clk, input [7:0] din, output [7:0] dout);
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parameter LOC = "";
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''')
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print('''\
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(* LOC=LOC *)
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RAMB18E1 #(''')
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for i in range(8):
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print(" .INITP_%02X(256'b0)," % (i, ))
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print('')
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for i in range(0x40):
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print(" .INIT_%02X(256'b0)," % (i, ))
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print('')
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print(
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'''
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.IS_CLKARDCLK_INVERTED(1'b0),
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.IS_CLKBWRCLK_INVERTED(1'b0),
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.IS_ENARDEN_INVERTED(1'b0),
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.IS_ENBWREN_INVERTED(1'b0),
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.IS_RSTRAMARSTRAM_INVERTED(1'b0),
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.IS_RSTRAMB_INVERTED(1'b0),
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.IS_RSTREGARSTREG_INVERTED(1'b0),
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.IS_RSTREGB_INVERTED(1'b0),
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.RAM_MODE("TDP"),
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.WRITE_MODE_A("WRITE_FIRST"),
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.WRITE_MODE_B("WRITE_FIRST"),
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.SIM_DEVICE("VIRTEX6")
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) ram (
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.CLKARDCLK(din[0]),
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.CLKBWRCLK(din[1]),
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.ENARDEN(din[2]),
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.ENBWREN(din[3]),
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.REGCEAREGCE(din[4]),
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.REGCEB(din[5]),
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.RSTRAMARSTRAM(din[6]),
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.RSTRAMB(din[7]),
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.RSTREGARSTREG(din[0]),
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.RSTREGB(din[1]),
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.ADDRARDADDR(din[2]),
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.ADDRBWRADDR(din[3]),
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.DIADI(din[4]),
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.DIBDI(din[5]),
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.DIPADIP(din[6]),
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.DIPBDIP(din[7]),
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.WEA(din[0]),
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.WEBWE(din[1]),
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.DOADO(dout[0]),
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.DOBDO(dout[1]),
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.DOPADOP(dout[2]),
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.DOPBDOP(dout[3]));
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endmodule
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''')
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print(
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'''
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module my_RAMB36E1 (input clk, input [7:0] din, output [7:0] dout);
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parameter LOC = "";
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parameter IS_CLKARDCLK_INVERTED = 1'b0;
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parameter IS_CLKBWRCLK_INVERTED = 1'b0;
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parameter IS_ENARDEN_INVERTED = 1'b0;
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parameter IS_ENBWREN_INVERTED = 1'b0;
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parameter IS_RSTRAMARSTRAM_INVERTED = 1'b0;
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parameter IS_RSTRAMB_INVERTED = 1'b0;
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parameter IS_RSTREGARSTREG_INVERTED = 1'b0;
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parameter IS_RSTREGB_INVERTED = 1'b0;
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parameter RAM_MODE = "TDP";
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parameter WRITE_MODE_A = "WRITE_FIRST";
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parameter WRITE_MODE_B = "WRITE_FIRST";
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''')
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print('')
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print('''\
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(* LOC=LOC *)
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RAMB36E1 #(''')
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for i in range(16):
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print(" .INITP_%02X(256'b0)," % (i, ))
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print('')
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for i in range(0x80):
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print(" .INIT_%02X(256'b0)," % (i, ))
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print('')
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print(
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'''
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.IS_CLKARDCLK_INVERTED(1'b0),
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.IS_CLKBWRCLK_INVERTED(1'b0),
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.IS_ENARDEN_INVERTED(1'b0),
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.IS_ENBWREN_INVERTED(1'b0),
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.IS_RSTRAMARSTRAM_INVERTED(1'b0),
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.IS_RSTRAMB_INVERTED(1'b0),
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.IS_RSTREGARSTREG_INVERTED(1'b0),
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.IS_RSTREGB_INVERTED(1'b0),
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.RAM_MODE("TDP"),
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.WRITE_MODE_A("WRITE_FIRST"),
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.WRITE_MODE_B("WRITE_FIRST"),
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.SIM_DEVICE("VIRTEX6")
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) ram (
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.CLKARDCLK(din[0]),
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.CLKBWRCLK(din[1]),
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.ENARDEN(din[2]),
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.ENBWREN(din[3]),
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.REGCEAREGCE(din[4]),
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.REGCEB(din[5]),
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.RSTRAMARSTRAM(din[6]),
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.RSTRAMB(din[7]),
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.RSTREGARSTREG(din[0]),
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.RSTREGB(din[1]),
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.ADDRARDADDR(din[2]),
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.ADDRBWRADDR(din[3]),
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.DIADI(din[4]),
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.DIBDI(din[5]),
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.DIPADIP(din[6]),
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.DIPBDIP(din[7]),
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.WEA(din[0]),
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.WEBWE(din[1]),
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.DOADO(dout[0]),
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.DOBDO(dout[1]),
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.DOPADOP(dout[2]),
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.DOPBDOP(dout[3]));
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endmodule
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''')
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@ -122,6 +122,8 @@ class Segmaker:
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self.addtag('SLICE_X13Y101', 'CLB.SLICE_X0.AFF.DMUX.CY', 1)
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Indicates that the SLICE_X13Y101 site has an element called 'CLB.SLICE_X0.AFF.DMUX.CY'
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'''
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if '"' in site:
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raise ValueError("Invalid site: %s" % site)
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self.site_tags.setdefault(site, dict())[name] = value
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def add_tile_tag(self, tile, name, value):
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@ -130,6 +132,7 @@ class Segmaker:
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def compile(self, bitfilter=None):
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print("Compiling segment data.")
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tags_used = set()
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sites_used = set()
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tile_types_found = set()
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self.segments_by_type = dict()
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@ -241,6 +244,7 @@ class Segmaker:
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tag = tag.replace(".SLICEM.", ".")
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tag = tag.replace(".SLICEL.", ".")
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segments[segname]["tags"][tag] = value
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sites_used.add(site)
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tile_type = tiledata["type"]
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tile_types_found.add(tile_type)
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@ -279,8 +283,15 @@ class Segmaker:
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add_site_tags()
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if self.verbose:
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ntags = recurse_sum(self.site_tags) + recurse_sum(self.tile_tags)
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n_site_tags = recurse_sum(self.site_tags)
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n_tile_tags = recurse_sum(self.tile_tags)
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ntags = n_site_tags + n_tile_tags
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print("Used %u / %u tags" % (len(tags_used), ntags))
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print("Tag sites: %u" % (n_site_tags,))
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if n_site_tags:
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print(' Ex: %s' % list(self.site_tags.keys())[0])
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print("Tag tiles: %u" % (n_tile_tags,))
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print("Used %u sites" % len(sites_used))
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print("Grid DB had %u tile types" % len(tile_types_found))
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assert ntags and ntags == len(tags_used)
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|
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@ -48,4 +48,22 @@ def instance(mod, name, ports, params={}, sort=True):
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for i, (portk, portv) in enumerate(tosort(ports.items())):
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comma = '' if i == len(ports) - 1 else ','
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print(' .%s(%s)%s' % (portk, portv, comma))
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print(' ));')
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print(' );')
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def quote(s):
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return '"' + s + '"'
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def unquote(s):
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assert s[0] == '"' and s[-1] == '"'
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return s[1:-1]
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||||
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def parsei(s):
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if s == "1'b0":
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return 0
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elif s == "1'b1":
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return 1
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else:
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assert 0, 'FIXME'
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|
|
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@ -12,6 +12,7 @@ test $# = 1 || exit 1
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test ! -e "$SPECN"
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SPECN=$1
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rm -rf "$SPECN"
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mkdir "$SPECN"
|
||||
cd "$SPECN"
|
||||
|
||||
|
|
|
|||
Loading…
Reference in New Issue