From 671a55705f91fab4be1e3bc11ec6d5c45113ef69 Mon Sep 17 00:00:00 2001 From: John McMaster Date: Tue, 23 Oct 2018 23:23:45 -0700 Subject: [PATCH] tilegrid: fix BRAM CLB_IO_CLK height Signed-off-by: John McMaster --- fuzzers/005-tilegrid/generate.py | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/fuzzers/005-tilegrid/generate.py b/fuzzers/005-tilegrid/generate.py index 7221971a..77ab5a50 100644 --- a/fuzzers/005-tilegrid/generate.py +++ b/fuzzers/005-tilegrid/generate.py @@ -486,7 +486,7 @@ def db_add_bits(database, segments): ("CLBLM", "CLB_IO_CLK"): (36, 2, 2), ("HCLK", "CLB_IO_CLK"): (26, 1, 1), ("INT", "CLB_IO_CLK"): (28, 2, 2), - ("BRAM", "CLB_IO_CLK"): (28, 2, None), + ("BRAM", "CLB_IO_CLK"): (28, 10, None), ("BRAM", "BLOCK_RAM"): (128, 10, None), ("DSP", "CLB_IO_CLK"): (28, 2, 10), ("INT_INTERFACE", "CLB_IO_CLK"): (28, 2, None),