mirror of https://github.com/openXC7/prjxray.git
152 lines
4.8 KiB
Tcl
152 lines
4.8 KiB
Tcl
source "$::env(XRAY_DIR)/utils/utils.tcl"
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proc create_design {} {
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create_project -force -part $::env(XRAY_PART) design design
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read_verilog $::env(SRC_DIR)/top.v
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synth_design -top top -flatten_hierarchy none
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set_property -dict "PACKAGE_PIN $::env(XRAY_PIN_00) IOSTANDARD LVCMOS33" [get_ports di]
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set_property -dict "PACKAGE_PIN $::env(XRAY_PIN_01) IOSTANDARD LVCMOS33" [get_ports do]
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set_property CFGBVS VCCO [current_design]
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set_property CONFIG_VOLTAGE 3.3 [current_design]
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set_property BITSTREAM.GENERAL.PERFRAMECRC YES [current_design]
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}
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proc place_and_route_design {} {
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place_design
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route_design
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write_checkpoint -force design.dcp
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}
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proc dump_tile_timings {tile timing_fp config_fp pins_fp tile_pins_fp} {
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set properties [list "DELAY" "FAST_MAX" "FAST_MIN" "SLOW_MAX" "SLOW_MIN"]
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set timing_line {}
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set config_line {}
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set pins_line {}
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set tile_pins_line {}
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lappend timing_line [get_property TYPE $tile]
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lappend config_line [get_property TYPE $tile]
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lappend pins_line [get_property TYPE $tile]
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lappend tile_pins_line [get_property TYPE $tile]
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set sites [get_sites -of_objects [get_tiles $tile]]
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lappend tile_pins_line [llength $sites]
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lappend timing_line [llength $sites]
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lappend config_line [llength $sites]
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lappend pins_line [llength $sites]
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foreach site $sites {
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set site_type [get_property SITE_TYPE $site]
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lappend tile_pins_line $site_type
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lappend pins_line $site_type
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lappend timing_line $site_type
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lappend config_line $site_type
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# dump site pins
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set site_pins [get_site_pins -of_objects [get_sites $site]]
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lappend tile_pins_line [llength $site_pins]
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foreach pin $site_pins {
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set direction [get_property DIRECTION $pin]
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set is_part_of_bus [get_property IS_PART_OF_BUS $pin]
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regexp {\/(.*)$} $pin -> pin
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lappend tile_pins_line $pin $direction $is_part_of_bus
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}
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# dump bel pins, speed_models and configs
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set bels [get_bels -of_objects $site]
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lappend pins_line [llength $bels]
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lappend timing_line [llength $bels]
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lappend config_line [llength $bels]
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foreach bel $bels {
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set speed_models [get_speed_models -of_objects $bel]
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set bel_type [get_property TYPE $bel]
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set bel_configs [list_property $bel CONFIG*]
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set bel_pins [get_bel_pins -of_objects [get_bels $bel]]
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lappend pins_line $bel_type
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lappend pins_line [llength $bel_pins]
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foreach pin $bel_pins {
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set direction [get_property DIRECTION $pin]
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set is_clock [get_property IS_CLOCK $pin]
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set is_part_of_bus [get_property IS_PART_OF_BUS $pin]
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regexp {\/.*\/(.*)$} $pin -> pin
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lappend pins_line $pin $direction $is_clock $is_part_of_bus
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}
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lappend config_line $bel_type
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lappend config_line [llength $bel_configs]
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foreach config $bel_configs {
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set config_vals [get_property $config $bel]
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lappend config_line $config
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lappend config_line [llength $config_vals]
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foreach val $config_vals {
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lappend config_line $val
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}
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}
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lappend timing_line "$bel_type"
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lappend timing_line [llength $speed_models]
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foreach speed_model $speed_models {
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lappend timing_line $speed_model
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foreach property $properties {
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set value [get_property $property $speed_model]
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lappend timing_line "$property:$value"
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}
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}
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}
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}
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puts $tile_pins_fp $tile_pins_line
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puts $pins_fp $pins_line
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puts $timing_fp $timing_line
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puts $config_fp $config_line
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}
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proc dump {} {
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set types [get_tile_types]
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set timing_fp [open "bel_timings.txt" w]
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set property_fp [open "bel_properties.txt" w]
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set pins_fp [open "bel_pins.txt" w]
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set tile_pins_fp [open "tile_pins.txt" w]
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foreach type $types {
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set tile [randsample_list 1 [get_tiles -filter "TYPE == $type"]]
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dump_tile_timings $tile $timing_fp $property_fp $pins_fp $tile_pins_fp
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}
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set other_site_types [list ISERDESE2 OSERDESE2]
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foreach site_type $other_site_types {
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set cell [create_cell -reference $site_type test]
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place_design
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set tile [get_tiles -of [get_sites -of $cell]]
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dump_tile_timings $tile $timing_fp $property_fp $pins_fp $tile_pins_fp
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unplace_cell $cell
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remove_cell $cell
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}
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close $pins_fp
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close $timing_fp
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close $property_fp
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}
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proc run {} {
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create_design
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place_and_route_design
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dump
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write_bitstream -force design.bit
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}
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run
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