uart-ddr: addressed review comments and fixed file locations

Signed-off-by: Alessandro Comodi <acomodi@antmicro.com>

minitests/litex/uart_ddr/arty/src.vivado/Makefile

@@ -1,6 +1,6 @@
 PART = xc7a35tcsg324-1
 BIT2FASM_ARGS = --part "$(XRAY_DIR)/database/artix7/$(PART)" --verbose
-SOURCES = ../verilog/mem.init ../verilog/mem_1.init ../verilog/top.v
+SOURCES = ../generated/mem.init ../generated/mem_1.init ../generated/top.v ../generated/top.xdc
 
 all: top.fasm top.bits segprint.log
 
@@ -14,7 +14,7 @@ clean:
 
 .PHONY: all clean
 
-top.bit: $(VIVADO) $(SOURCES) top.xdc top.tcl
+top.bit: $(VIVADO) $(SOURCES) top.tcl
 	mkdir -p build
 	cd build && $(XRAY_VIVADO) -mode batch -source ../top.tcl -nojournal -tempDir build -log vivado.log -verbose
 	cp build/*.bit ./

minitests/litex/uart_ddr/arty/src.vivado/top.tcl

@@ -1,6 +1,6 @@
 create_project -force -name top -part xc7a35ticsg324-1L
-add_files {../../verilog/top.v}
+add_files {../../generated/top.v}
-read_xdc ../top.xdc
+read_xdc ../../generated/top.xdc
 synth_design -top top -part xc7a35ticsg324-1L
 report_timing_summary -file top_timing_synth.rpt
 report_utilization -hierarchical -file top_utilization_hierarchical_synth.rpt

minitests/litex/uart_ddr/arty/src.yosys/Makefile

@@ -1,7 +1,7 @@
 export XRAY_PART = xc7a35tcsg324-1
 export XRAY_PART_YAML = $(XRAY_DATABASE_DIR)/$(XRAY_DATABASE)/$(XRAY_PART)/part.yaml
 YOSYS = $(XRAY_DIR)/third_party/yosys/yosys
-SOURCES = ../verilog/mem.init ../verilog/mem_1.init ../verilog/top.v
+SOURCES = ../generated/mem.init ../generated/mem_1.init ../generated/top.v ../generated/top.xdc
 PORT ?= /dev/ttyUSB1
 
 all: top.f2b.bit
@@ -24,7 +24,7 @@ $(YOSYS):
 top.edif: $(YOSYS) synth.ys $(SOURCES)
 	$(YOSYS) -s synth.ys -l yosys.log
 
-top.bit: $(VIVADO) top.edif top.xdc top.tcl
+top.bit: $(VIVADO) top.edif top.tcl
 	mkdir -p build
 	cd build && $(XRAY_VIVADO) -mode batch -source ../top.tcl -nojournal -tempDir build -log vivado.log -verbose
 	python3 $(XRAY_DIR)/minitests/timing/clean_json5.py < build/iobuf_report.json5 > build/iobuf_report.json

minitests/litex/uart_ddr/arty/src.yosys/mem.init

@@ -1 +1 @@
-../verilog/mem.init
+../generated/mem.init

minitests/litex/uart_ddr/arty/src.yosys/mem_1.init

@@ -1 +1 @@
-../verilog/mem_1.init
+../generated/mem_1.init

minitests/litex/uart_ddr/arty/src.yosys/missing_bit_report.py

@@ -1,81 +0,0 @@
-""" Generates a missing feature/bit report for LiteX design.
-
-This script is fairly fragile, because it depends on the specific observation
-that all of the remaining bits appear to either belong to HCLK_IOI or IOI3
-tiles.  A more general version of this script could be created, but that was
-not the point of this script.
-
-"""
-from fasm import parse_fasm_filename
-
-
-def main():
-    fasm_file = 'top.fasm'
-    fasm_model = list(parse_fasm_filename(fasm_file))
-
-    unknown_bits = {
-        'HCLK_IOI': {},
-        'IOI3': {},
-    }
-
-    total_unknown = 0
-    for l in fasm_model:
-        if l.annotations is None:
-            continue
-
-        annotations = {}
-        for annotation in l.annotations:
-            annotations[annotation.name] = annotation.value
-
-        if 'unknown_bit' not in annotations:
-            continue
-
-        total_unknown += 1
-
-        frame, word, bit = annotations['unknown_bit'].split('_')
-
-        frame = int(frame, 16)
-        word = int(word)
-        bit = int(bit)
-
-        frame_offset = frame % 0x80
-        base_frame = frame - frame_offset
-
-        # All remaining LiteX bits appear to be in this one IO bank, so limit
-        # the tool this this one IO bank.
-        assert base_frame == 0x00401580, hex(frame)
-
-        SIZE = 4
-        INITIAL_OFFSET = -2
-
-        if word == 50:
-            group = 'HCLK_IOI'
-            offset = 45
-        elif word < 50:
-            group = 'IOI3'
-            offset = ((word - INITIAL_OFFSET) // SIZE) * SIZE + INITIAL_OFFSET
-        else:
-            group = 'IOI3'
-            word -= 1
-            offset = ((word - INITIAL_OFFSET) // SIZE) * SIZE + INITIAL_OFFSET
-            offset += 1
-            word += 1
-
-        bit = '{}_{:02d}'.format(
-            frame_offset,
-            (word - offset) * 32 + bit,
-        )
-
-        if bit not in unknown_bits[group]:
-            unknown_bits[group][bit] = 0
-        unknown_bits[group][bit] += 1
-
-    print('Total unknown bits: {}'.format(total_unknown))
-    for group in unknown_bits:
-        print('Group {} (count = {}):'.format(group, len(unknown_bits[group])))
-        for bit in sorted(unknown_bits[group]):
-            print('  {} (count = {})'.format(bit, unknown_bits[group][bit]))
-
-
-if __name__ == "__main__":
-    main()

minitests/litex/uart_ddr/arty/src.yosys/synth.ys

@@ -1,2 +1,2 @@
-read_verilog ../verilog/top.v
+read_verilog ../generated/top.v
 synth_xilinx -edif top.edif

minitests/litex/uart_ddr/arty/src.yosys/top.tcl

@@ -29,7 +29,7 @@ proc write_iobuf_report {filename} {
 }
 
 create_project -force -name top -part xc7a35ticsg324-1L
-read_xdc ../top.xdc
+read_xdc ../../generated/top.xdc
 read_edif ../top.edif
 link_design -top top -part xc7a35ticsg324-1L
 report_timing_summary -file top_timing_synth.rpt

minitests/litex/uart_ddr/arty/src.yosys/top.xdc

@@ -1,298 +0,0 @@
-################################################################################
-# IO constraints
-################################################################################
-# serial:0.tx
-set_property LOC D10 [get_ports serial_tx]
-set_property IOSTANDARD LVCMOS33 [get_ports serial_tx]
-
-# serial:0.rx
-set_property LOC A9 [get_ports serial_rx]
-set_property IOSTANDARD LVCMOS33 [get_ports serial_rx]
-
-# cpu_reset:0
-set_property LOC C2 [get_ports cpu_reset]
-set_property IOSTANDARD LVCMOS33 [get_ports cpu_reset]
-
-# clk100:0
-set_property LOC E3 [get_ports clk100]
-set_property IOSTANDARD LVCMOS33 [get_ports clk100]
-
-# ddram:0.a
-set_property LOC R2 [get_ports ddram_a[0]]
-set_property SLEW FAST [get_ports ddram_a[0]]
-set_property IOSTANDARD SSTL135 [get_ports ddram_a[0]]
-
-# ddram:0.a
-set_property LOC M6 [get_ports ddram_a[1]]
-set_property SLEW FAST [get_ports ddram_a[1]]
-set_property IOSTANDARD SSTL135 [get_ports ddram_a[1]]
-
-# ddram:0.a
-set_property LOC N4 [get_ports ddram_a[2]]
-set_property SLEW FAST [get_ports ddram_a[2]]
-set_property IOSTANDARD SSTL135 [get_ports ddram_a[2]]
-
-# ddram:0.a
-set_property LOC T1 [get_ports ddram_a[3]]
-set_property SLEW FAST [get_ports ddram_a[3]]
-set_property IOSTANDARD SSTL135 [get_ports ddram_a[3]]
-
-# ddram:0.a
-set_property LOC N6 [get_ports ddram_a[4]]
-set_property SLEW FAST [get_ports ddram_a[4]]
-set_property IOSTANDARD SSTL135 [get_ports ddram_a[4]]
-
-# ddram:0.a
-set_property LOC R7 [get_ports ddram_a[5]]
-set_property SLEW FAST [get_ports ddram_a[5]]
-set_property IOSTANDARD SSTL135 [get_ports ddram_a[5]]
-
-# ddram:0.a
-set_property LOC V6 [get_ports ddram_a[6]]
-set_property SLEW FAST [get_ports ddram_a[6]]
-set_property IOSTANDARD SSTL135 [get_ports ddram_a[6]]
-
-# ddram:0.a
-set_property LOC U7 [get_ports ddram_a[7]]
-set_property SLEW FAST [get_ports ddram_a[7]]
-set_property IOSTANDARD SSTL135 [get_ports ddram_a[7]]
-
-# ddram:0.a
-set_property LOC R8 [get_ports ddram_a[8]]
-set_property SLEW FAST [get_ports ddram_a[8]]
-set_property IOSTANDARD SSTL135 [get_ports ddram_a[8]]
-
-# ddram:0.a
-set_property LOC V7 [get_ports ddram_a[9]]
-set_property SLEW FAST [get_ports ddram_a[9]]
-set_property IOSTANDARD SSTL135 [get_ports ddram_a[9]]
-
-# ddram:0.a
-set_property LOC R6 [get_ports ddram_a[10]]
-set_property SLEW FAST [get_ports ddram_a[10]]
-set_property IOSTANDARD SSTL135 [get_ports ddram_a[10]]
-
-# ddram:0.a
-set_property LOC U6 [get_ports ddram_a[11]]
-set_property SLEW FAST [get_ports ddram_a[11]]
-set_property IOSTANDARD SSTL135 [get_ports ddram_a[11]]
-
-# ddram:0.a
-set_property LOC T6 [get_ports ddram_a[12]]
-set_property SLEW FAST [get_ports ddram_a[12]]
-set_property IOSTANDARD SSTL135 [get_ports ddram_a[12]]
-
-# ddram:0.a
-set_property LOC T8 [get_ports ddram_a[13]]
-set_property SLEW FAST [get_ports ddram_a[13]]
-set_property IOSTANDARD SSTL135 [get_ports ddram_a[13]]
-
-# ddram:0.ba
-set_property LOC R1 [get_ports ddram_ba[0]]
-set_property SLEW FAST [get_ports ddram_ba[0]]
-set_property IOSTANDARD SSTL135 [get_ports ddram_ba[0]]
-
-# ddram:0.ba
-set_property LOC P4 [get_ports ddram_ba[1]]
-set_property SLEW FAST [get_ports ddram_ba[1]]
-set_property IOSTANDARD SSTL135 [get_ports ddram_ba[1]]
-
-# ddram:0.ba
-set_property LOC P2 [get_ports ddram_ba[2]]
-set_property SLEW FAST [get_ports ddram_ba[2]]
-set_property IOSTANDARD SSTL135 [get_ports ddram_ba[2]]
-
-# ddram:0.ras_n
-set_property LOC P3 [get_ports ddram_ras_n]
-set_property SLEW FAST [get_ports ddram_ras_n]
-set_property IOSTANDARD SSTL135 [get_ports ddram_ras_n]
-
-# ddram:0.cas_n
-set_property LOC M4 [get_ports ddram_cas_n]
-set_property SLEW FAST [get_ports ddram_cas_n]
-set_property IOSTANDARD SSTL135 [get_ports ddram_cas_n]
-
-# ddram:0.we_n
-set_property LOC P5 [get_ports ddram_we_n]
-set_property SLEW FAST [get_ports ddram_we_n]
-set_property IOSTANDARD SSTL135 [get_ports ddram_we_n]
-
-# ddram:0.cs_n
-set_property LOC U8 [get_ports ddram_cs_n]
-set_property SLEW FAST [get_ports ddram_cs_n]
-set_property IOSTANDARD SSTL135 [get_ports ddram_cs_n]
-
-# ddram:0.dm
-set_property LOC L1 [get_ports ddram_dm[0]]
-set_property SLEW FAST [get_ports ddram_dm[0]]
-set_property IOSTANDARD SSTL135 [get_ports ddram_dm[0]]
-
-# ddram:0.dm
-set_property LOC U1 [get_ports ddram_dm[1]]
-set_property SLEW FAST [get_ports ddram_dm[1]]
-set_property IOSTANDARD SSTL135 [get_ports ddram_dm[1]]
-
-# ddram:0.dq
-set_property LOC K5 [get_ports ddram_dq[0]]
-set_property SLEW FAST [get_ports ddram_dq[0]]
-set_property IOSTANDARD SSTL135 [get_ports ddram_dq[0]]
-set_property IN_TERM UNTUNED_SPLIT_40 [get_ports ddram_dq[0]]
-
-# ddram:0.dq
-set_property LOC L3 [get_ports ddram_dq[1]]
-set_property SLEW FAST [get_ports ddram_dq[1]]
-set_property IOSTANDARD SSTL135 [get_ports ddram_dq[1]]
-set_property IN_TERM UNTUNED_SPLIT_40 [get_ports ddram_dq[1]]
-
-# ddram:0.dq
-set_property LOC K3 [get_ports ddram_dq[2]]
-set_property SLEW FAST [get_ports ddram_dq[2]]
-set_property IOSTANDARD SSTL135 [get_ports ddram_dq[2]]
-set_property IN_TERM UNTUNED_SPLIT_40 [get_ports ddram_dq[2]]
-
-# ddram:0.dq
-set_property LOC L6 [get_ports ddram_dq[3]]
-set_property SLEW FAST [get_ports ddram_dq[3]]
-set_property IOSTANDARD SSTL135 [get_ports ddram_dq[3]]
-set_property IN_TERM UNTUNED_SPLIT_40 [get_ports ddram_dq[3]]
-
-# ddram:0.dq
-set_property LOC M3 [get_ports ddram_dq[4]]
-set_property SLEW FAST [get_ports ddram_dq[4]]
-set_property IOSTANDARD SSTL135 [get_ports ddram_dq[4]]
-set_property IN_TERM UNTUNED_SPLIT_40 [get_ports ddram_dq[4]]
-
-# ddram:0.dq
-set_property LOC M1 [get_ports ddram_dq[5]]
-set_property SLEW FAST [get_ports ddram_dq[5]]
-set_property IOSTANDARD SSTL135 [get_ports ddram_dq[5]]
-set_property IN_TERM UNTUNED_SPLIT_40 [get_ports ddram_dq[5]]
-
-# ddram:0.dq
-set_property LOC L4 [get_ports ddram_dq[6]]
-set_property SLEW FAST [get_ports ddram_dq[6]]
-set_property IOSTANDARD SSTL135 [get_ports ddram_dq[6]]
-set_property IN_TERM UNTUNED_SPLIT_40 [get_ports ddram_dq[6]]
-
-# ddram:0.dq
-set_property LOC M2 [get_ports ddram_dq[7]]
-set_property SLEW FAST [get_ports ddram_dq[7]]
-set_property IOSTANDARD SSTL135 [get_ports ddram_dq[7]]
-set_property IN_TERM UNTUNED_SPLIT_40 [get_ports ddram_dq[7]]
-
-# ddram:0.dq
-set_property LOC V4 [get_ports ddram_dq[8]]
-set_property SLEW FAST [get_ports ddram_dq[8]]
-set_property IOSTANDARD SSTL135 [get_ports ddram_dq[8]]
-set_property IN_TERM UNTUNED_SPLIT_40 [get_ports ddram_dq[8]]
-
-# ddram:0.dq
-set_property LOC T5 [get_ports ddram_dq[9]]
-set_property SLEW FAST [get_ports ddram_dq[9]]
-set_property IOSTANDARD SSTL135 [get_ports ddram_dq[9]]
-set_property IN_TERM UNTUNED_SPLIT_40 [get_ports ddram_dq[9]]
-
-# ddram:0.dq
-set_property LOC U4 [get_ports ddram_dq[10]]
-set_property SLEW FAST [get_ports ddram_dq[10]]
-set_property IOSTANDARD SSTL135 [get_ports ddram_dq[10]]
-set_property IN_TERM UNTUNED_SPLIT_40 [get_ports ddram_dq[10]]
-
-# ddram:0.dq
-set_property LOC V5 [get_ports ddram_dq[11]]
-set_property SLEW FAST [get_ports ddram_dq[11]]
-set_property IOSTANDARD SSTL135 [get_ports ddram_dq[11]]
-set_property IN_TERM UNTUNED_SPLIT_40 [get_ports ddram_dq[11]]
-
-# ddram:0.dq
-set_property LOC V1 [get_ports ddram_dq[12]]
-set_property SLEW FAST [get_ports ddram_dq[12]]
-set_property IOSTANDARD SSTL135 [get_ports ddram_dq[12]]
-set_property IN_TERM UNTUNED_SPLIT_40 [get_ports ddram_dq[12]]
-
-# ddram:0.dq
-set_property LOC T3 [get_ports ddram_dq[13]]
-set_property SLEW FAST [get_ports ddram_dq[13]]
-set_property IOSTANDARD SSTL135 [get_ports ddram_dq[13]]
-set_property IN_TERM UNTUNED_SPLIT_40 [get_ports ddram_dq[13]]
-
-# ddram:0.dq
-set_property LOC U3 [get_ports ddram_dq[14]]
-set_property SLEW FAST [get_ports ddram_dq[14]]
-set_property IOSTANDARD SSTL135 [get_ports ddram_dq[14]]
-set_property IN_TERM UNTUNED_SPLIT_40 [get_ports ddram_dq[14]]
-
-# ddram:0.dq
-set_property LOC R3 [get_ports ddram_dq[15]]
-set_property SLEW FAST [get_ports ddram_dq[15]]
-set_property IOSTANDARD SSTL135 [get_ports ddram_dq[15]]
-set_property IN_TERM UNTUNED_SPLIT_40 [get_ports ddram_dq[15]]
-
-# ddram:0.dqs_p
-set_property LOC N2 [get_ports ddram_dqs_p[0]]
-set_property SLEW FAST [get_ports ddram_dqs_p[0]]
-set_property IOSTANDARD DIFF_SSTL135 [get_ports ddram_dqs_p[0]]
-
-# ddram:0.dqs_p
-set_property LOC U2 [get_ports ddram_dqs_p[1]]
-set_property SLEW FAST [get_ports ddram_dqs_p[1]]
-set_property IOSTANDARD DIFF_SSTL135 [get_ports ddram_dqs_p[1]]
-
-# ddram:0.dqs_n
-set_property LOC N1 [get_ports ddram_dqs_n[0]]
-set_property SLEW FAST [get_ports ddram_dqs_n[0]]
-set_property IOSTANDARD DIFF_SSTL135 [get_ports ddram_dqs_n[0]]
-
-# ddram:0.dqs_n
-set_property LOC V2 [get_ports ddram_dqs_n[1]]
-set_property SLEW FAST [get_ports ddram_dqs_n[1]]
-set_property IOSTANDARD DIFF_SSTL135 [get_ports ddram_dqs_n[1]]
-
-# ddram:0.clk_p
-set_property LOC U9 [get_ports ddram_clk_p]
-set_property SLEW FAST [get_ports ddram_clk_p]
-set_property IOSTANDARD DIFF_SSTL135 [get_ports ddram_clk_p]
-
-# ddram:0.clk_n
-set_property LOC V9 [get_ports ddram_clk_n]
-set_property SLEW FAST [get_ports ddram_clk_n]
-set_property IOSTANDARD DIFF_SSTL135 [get_ports ddram_clk_n]
-
-# ddram:0.cke
-set_property LOC N5 [get_ports ddram_cke]
-set_property SLEW FAST [get_ports ddram_cke]
-set_property IOSTANDARD SSTL135 [get_ports ddram_cke]
-
-# ddram:0.odt
-set_property LOC R5 [get_ports ddram_odt]
-set_property SLEW FAST [get_ports ddram_odt]
-set_property IOSTANDARD SSTL135 [get_ports ddram_odt]
-
-# ddram:0.reset_n
-set_property LOC K6 [get_ports ddram_reset_n]
-set_property SLEW FAST [get_ports ddram_reset_n]
-set_property IOSTANDARD SSTL135 [get_ports ddram_reset_n]
-
-################################################################################
-# Design constraints
-################################################################################
-
-set_property INTERNAL_VREF 0.675 [get_iobanks 34]
-
-################################################################################
-# Clock constraints
-################################################################################
-
-
-create_clock -name clk100 -period 10.0 [get_nets clk100]
-
-################################################################################
-# False path constraints
-################################################################################
-
-
-set_false_path -quiet -to [get_nets -quiet -filter {mr_ff == TRUE}]
-
-set_false_path -quiet -to [get_pins -quiet -filter {REF_PIN_NAME == PRE} -of [get_cells -quiet -filter {ars_ff1 == TRUE || ars_ff2 == TRUE}]]
-
-set_max_delay 2 -quiet -from [get_pins -quiet -filter {REF_PIN_NAME == Q} -of [get_cells -quiet -filter {ars_ff1 == TRUE}]] -to [get_pins -quiet -filter {REF_PIN_NAME == D} -of [get_cells -quiet -filter {ars_ff2 == TRUE}]]