From 4d6f75e8ad35a5ec8a46ed078db9955d0a085eca Mon Sep 17 00:00:00 2001 From: Maciej Kurc Date: Fri, 28 Jun 2019 10:53:27 +0200 Subject: [PATCH] Added packing tests for SRL32+LUT6 Signed-off-by: Maciej Kurc --- minitests/srl/srl32_x1_and_lut6_x3.v | 62 +++++++++++++++++++++++++++ minitests/srl/srl32_x2_and_lut6_x2.v | 63 ++++++++++++++++++++++++++++ minitests/srl/srl32_x3_and_lut6_x1.v | 63 ++++++++++++++++++++++++++++ 3 files changed, 188 insertions(+) create mode 100644 minitests/srl/srl32_x1_and_lut6_x3.v create mode 100644 minitests/srl/srl32_x2_and_lut6_x2.v create mode 100644 minitests/srl/srl32_x3_and_lut6_x1.v diff --git a/minitests/srl/srl32_x1_and_lut6_x3.v b/minitests/srl/srl32_x1_and_lut6_x3.v new file mode 100644 index 00000000..ab1a894b --- /dev/null +++ b/minitests/srl/srl32_x1_and_lut6_x3.v @@ -0,0 +1,62 @@ +module top +( +(* clock_buffer_type = "NONE" *) +input wire CLK, +input wire CE, +input wire D, +input wire [5:0] I, +input wire [4:0] A, +output wire [3:0] Q +); + + (* DONT_TOUCH="yes" *) + (* LOC="SLICE_X2Y0", BEL="A6LUT" *) + SRLC32E srl_a + ( + .CLK (CLK), + .CE (CE), + .D (D), + .A (A), + .Q (Q[0]) + ); + + (* DONT_TOUCH="yes" *) + (* LOC="SLICE_X2Y0", BEL="B6LUT" *) + LUT6 lut_b + ( + .I0 (I[0]), + .I1 (I[1]), + .I2 (I[2]), + .I3 (I[3]), + .I4 (I[4]), + .I5 (I[5]), + .O (Q[1]) + ); + + (* DONT_TOUCH="yes" *) + (* LOC="SLICE_X2Y0", BEL="C6LUT" *) + LUT6 lut_c + ( + .I0 (I[0]), + .I1 (I[1]), + .I2 (I[2]), + .I3 (I[3]), + .I4 (I[4]), + .I5 (I[5]), + .O (Q[2]) + ); + + (* DONT_TOUCH="yes" *) + (* LOC="SLICE_X2Y0", BEL="D6LUT" *) + LUT6 lut_d + ( + .I0 (I[0]), + .I1 (I[1]), + .I2 (I[2]), + .I3 (I[3]), + .I4 (I[4]), + .I5 (I[5]), + .O (Q[3]) + ); + +endmodule diff --git a/minitests/srl/srl32_x2_and_lut6_x2.v b/minitests/srl/srl32_x2_and_lut6_x2.v new file mode 100644 index 00000000..c68e0c1e --- /dev/null +++ b/minitests/srl/srl32_x2_and_lut6_x2.v @@ -0,0 +1,63 @@ +module top +( +(* clock_buffer_type = "NONE" *) +input wire CLK, +input wire CE, +input wire D, +input wire [5:0] I, +input wire [4:0] A, +output wire [3:0] Q +); + + wire srl_b_mc31; + + (* DONT_TOUCH="yes" *) + (* LOC="SLICE_X2Y0", BEL="A6LUT" *) + SRLC32E srl_a + ( + .CLK (CLK), + .CE (CE), + .D (srl_b_mc31), + .A (A), + .Q (Q[0]) + ); + + (* DONT_TOUCH="yes" *) + (* LOC="SLICE_X2Y0", BEL="B6LUT" *) + SRLC32E srl_b + ( + .CLK (CLK), + .CE (CE), + .D (D), + .A (A), + .Q (Q[1]), + .Q31 (srl_b_mc31) + ); + + (* DONT_TOUCH="yes" *) + (* LOC="SLICE_X2Y0", BEL="C6LUT" *) + LUT6 lut_c + ( + .I0 (I[0]), + .I1 (I[1]), + .I2 (I[2]), + .I3 (I[3]), + .I4 (I[4]), + .I5 (I[5]), + .O (Q[2]) + ); + + (* DONT_TOUCH="yes" *) + (* LOC="SLICE_X2Y0", BEL="D6LUT" *) + LUT6 lut_d + ( + .I0 (I[0]), + .I1 (I[1]), + .I2 (I[2]), + .I3 (I[3]), + .I4 (I[4]), + .I5 (I[5]), + .O (Q[3]) + ); + +endmodule diff --git a/minitests/srl/srl32_x3_and_lut6_x1.v b/minitests/srl/srl32_x3_and_lut6_x1.v new file mode 100644 index 00000000..c931bbc9 --- /dev/null +++ b/minitests/srl/srl32_x3_and_lut6_x1.v @@ -0,0 +1,63 @@ +module top +( +(* clock_buffer_type = "NONE" *) +input wire CLK, +input wire CE, +input wire D, +input wire [5:0] I, +input wire [4:0] A, +output wire [3:0] Q +); + + wire srl_b_mc31; + wire srl_c_mc31; + + (* DONT_TOUCH="yes" *) + (* LOC="SLICE_X2Y0", BEL="A6LUT" *) + SRLC32E srl_a + ( + .CLK (CLK), + .CE (CE), + .D (srl_b_mc31), + .A (A), + .Q (Q[0]) + ); + + (* DONT_TOUCH="yes" *) + (* LOC="SLICE_X2Y0", BEL="B6LUT" *) + SRLC32E srl_b + ( + .CLK (CLK), + .CE (CE), + .D (srl_c_mc31), + .A (A), + .Q (Q[1]), + .Q31 (srl_b_mc31) + ); + + (* DONT_TOUCH="yes" *) + (* LOC="SLICE_X2Y0", BEL="C6LUT" *) + SRLC32E srl_c + ( + .CLK (CLK), + .CE (CE), + .D (D), + .A (A), + .Q (Q[2]), + .Q31 (srl_c_mc31) + ); + + (* DONT_TOUCH="yes" *) + (* LOC="SLICE_X2Y0", BEL="D6LUT" *) + LUT6 lut_d + ( + .I0 (I[0]), + .I1 (I[1]), + .I2 (I[2]), + .I3 (I[3]), + .I4 (I[4]), + .I5 (I[5]), + .O (Q[3]) + ); + +endmodule