Add 071-ppips

Signed-off-by: Clifford Wolf <clifford@clifford.at>
Signed-off-by: Tim 'mithro' Ansell <mithro@mithis.com>

fuzzers/071-ppips/.gitignore

@@ -0,0 +1,3 @@
+/specimen_*/
+/ppips_clbl[ml]_[lr].txt
+/ppips_int_[lr].txt

fuzzers/071-ppips/Makefile

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+
+N := 1
+SPECIMENS := $(addprefix specimen_,$(shell seq -f '%03.0f' $(N)))
+SPECIMENS_OK := $(addsuffix /OK,$(SPECIMENS))
+
+database: $(SPECIMENS_OK)
+	cp specimen_001/ppips_clblm_l.txt .
+	cp specimen_001/ppips_clblm_r.txt .
+	cp specimen_001/ppips_clbll_l.txt .
+	cp specimen_001/ppips_clbll_r.txt .
+	cp specimen_001/ppips_int_l.txt .
+	cp specimen_001/ppips_int_r.txt .
+
+pushdb:
+	cp ppips_clblm_l.txt ${XRAY_DATABASE_DIR}/$(XRAY_DATABASE)/ppips_clblm_l.db
+	cp ppips_clblm_r.txt ${XRAY_DATABASE_DIR}/$(XRAY_DATABASE)/ppips_clblm_r.db
+	cp ppips_clbll_l.txt ${XRAY_DATABASE_DIR}/$(XRAY_DATABASE)/ppips_clbll_l.db
+	cp ppips_clbll_r.txt ${XRAY_DATABASE_DIR}/$(XRAY_DATABASE)/ppips_clbll_r.db
+	cp ppips_int_l.txt   ${XRAY_DATABASE_DIR}/$(XRAY_DATABASE)/ppips_int_l.db
+	cp ppips_int_r.txt   ${XRAY_DATABASE_DIR}/$(XRAY_DATABASE)/ppips_int_r.db
+
+$(SPECIMENS_OK):
+	bash generate.sh $(subst /OK,,$@)
+	touch $@
+
+clean:
+	rm -rf specimen_[0-9][0-9][0-9]/ ppips_clbl[ml]_[lr].txt ppips_int_[lr].txt
+
+.PHONY: database pushdb clean
+

fuzzers/071-ppips/generate.sh

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+#!/bin/bash -x
+
+source ${XRAY_GENHEADER}
+
+vivado -mode batch -source ../generate.tcl
+

fuzzers/071-ppips/generate.tcl

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+create_project -force -part $::env(XRAY_PART) design design
+
+read_verilog ../top.v
+synth_design -top top
+
+set_property -dict "PACKAGE_PIN $::env(XRAY_PIN_00) IOSTANDARD LVCMOS33" [get_ports a]
+set_property -dict "PACKAGE_PIN $::env(XRAY_PIN_01) IOSTANDARD LVCMOS33" [get_ports y]
+
+create_pblock roi
+resize_pblock [get_pblocks roi] -add "$::env(XRAY_ROI)"
+
+set_property CFGBVS VCCO [current_design]
+set_property CONFIG_VOLTAGE 3.3 [current_design]
+set_property BITSTREAM.GENERAL.PERFRAMECRC YES [current_design]
+
+place_design
+route_design
+
+write_checkpoint -force design.dcp
+# write_bitstream -force design.bit
+
+proc write_clb_ppips_db {filename tile} {
+	set fp [open $filename "w"]
+	set tile [get_tiles $tile]
+	set tile_type [get_property TILE_TYPE $tile]
+
+	foreach pip [get_pips -of_objects $tile] {
+		set dst_wire [get_wires -downhill -of_objects $pip]
+		if {[get_pips -uphill -of_objects [get_nodes -of_objects $dst_wire]] == $pip} {
+			set src_wire [get_wires -uphill -of_objects $pip]
+			puts $fp "${tile_type}.[regsub {.*/} $dst_wire ""].[regsub {.*/} $src_wire ""] always"
+		}
+	}
+
+	close $fp
+}
+
+proc write_int_ppips_db {filename tile} {
+	set fp [open $filename "w"]
+	set tile [get_tiles $tile]
+	set tile_type [get_property TILE_TYPE $tile]
+
+	foreach pip [get_pips -of_objects [get_wires $tile/VCC_WIRE]] {
+		set wire [regsub {.*/} [get_wires -downhill -of_objects $pip] ""]
+		puts $fp "${tile_type}.${wire}.VCC_WIRE default"
+	}
+
+	foreach pip [get_pips -of_objects $tile] {
+		set dst_wire [get_wires -downhill -of_objects $pip]
+		if {[get_pips -uphill -of_objects [get_nodes -of_objects $dst_wire]] == $pip} {
+			set src_wire [get_wires -uphill -of_objects $pip]
+			if {! [regexp "^GCLK_" $src_wire]} {
+				puts $fp "${tile_type}.[regsub {.*/} $dst_wire ""].[regsub {.*/} $src_wire ""] always"
+			}
+		}
+	}
+
+	close $fp
+}
+
+write_clb_ppips_db "ppips_clblm_l.txt" CLBLM_L_X10Y115
+write_clb_ppips_db "ppips_clblm_r.txt" CLBLM_R_X11Y115
+write_clb_ppips_db "ppips_clbll_l.txt" CLBLL_L_X12Y115
+write_clb_ppips_db "ppips_clbll_r.txt" CLBLL_R_X13Y115
+write_int_ppips_db "ppips_int_l.txt" INT_L_X12Y115
+write_int_ppips_db "ppips_int_r.txt" INT_R_X13Y115
+

fuzzers/071-ppips/top.v

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+module top(input a, output y);
+	assign y = a;
+endmodule