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Ran make format-py 

Signed-off-by: Maciej Kurc <mkurc@antmicro.com>
This commit is contained in:
Maciej Kurc 2019-07-22 10:52:45 +02:00
parent a2552bf478
commit 369aa38c6a
2 changed files with 79 additions and 46 deletions
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46
fuzzers/035b-iob-iserdes/generate.py
View File

@ -12,8 +12,10 @@ segmk = Segmaker("design.bits")
with open("params.json", "r") as fp: with open("params.json", "r") as fp:
data = json.load(fp) data = json.load(fp)
iface_types = ["NETWORKING", "OVERSAMPLE", "MEMORY", "MEMORY_DDR3", "MEMORY_QDR"] iface_types = [
data_rates = ["SDR", "DDR"] "NETWORKING", "OVERSAMPLE", "MEMORY", "MEMORY_DDR3", "MEMORY_QDR"
]
data_rates = ["SDR", "DDR"]
data_widths = [2, 3, 4, 5, 6, 7, 8, 10, 14] data_widths = [2, 3, 4, 5, 6, 7, 8, 10, 14]
# Output tags # Output tags
@ -33,7 +35,7 @@ for params in data:
segmk.add_site_tag(loc, "ISERDES.IN_USE", 0) segmk.add_site_tag(loc, "ISERDES.IN_USE", 0)
segmk.add_site_tag(loc, "ISERDES.MODE.MASTER", 0) segmk.add_site_tag(loc, "ISERDES.MODE.MASTER", 0)
segmk.add_site_tag(loc, "ISERDES.MODE.SLAVE", 0) segmk.add_site_tag(loc, "ISERDES.MODE.SLAVE", 0)
for i in iface_types: for i in iface_types:
if i == "NETWORKING": if i == "NETWORKING":
@ -48,10 +50,10 @@ for params in data:
segmk.add_site_tag(loc, "ISERDES.NUM_CE.1", 0) segmk.add_site_tag(loc, "ISERDES.NUM_CE.1", 0)
segmk.add_site_tag(loc, "ISERDES.NUM_CE.2", 0) segmk.add_site_tag(loc, "ISERDES.NUM_CE.2", 0)
for i in range(1, 4+1): for i in range(1, 4 + 1):
segmk.add_site_tag(loc, "IFF.ZINIT_Q%d" % i, 0) segmk.add_site_tag(loc, "IFF.ZINIT_Q%d" % i, 0)
for i in range(1, 4+1): for i in range(1, 4 + 1):
segmk.add_site_tag(loc, "IFF.ZSRVAL_Q%d" % i, 0) segmk.add_site_tag(loc, "IFF.ZSRVAL_Q%d" % i, 0)
segmk.add_site_tag(loc, "ZINV_D", 0) segmk.add_site_tag(loc, "ZINV_D", 0)
@ -75,15 +77,15 @@ for params in data:
value = verilog.unquote(params["SERDES_MODE"]) value = verilog.unquote(params["SERDES_MODE"])
if value == "MASTER": if value == "MASTER":
segmk.add_site_tag(loc, "ISERDES.MODE.MASTER", 1) segmk.add_site_tag(loc, "ISERDES.MODE.MASTER", 1)
segmk.add_site_tag(loc, "ISERDES.MODE.SLAVE", 0) segmk.add_site_tag(loc, "ISERDES.MODE.SLAVE", 0)
if value == "SLAVE": if value == "SLAVE":
segmk.add_site_tag(loc, "ISERDES.MODE.MASTER", 0) segmk.add_site_tag(loc, "ISERDES.MODE.MASTER", 0)
segmk.add_site_tag(loc, "ISERDES.MODE.SLAVE", 1) segmk.add_site_tag(loc, "ISERDES.MODE.SLAVE", 1)
iface_type = verilog.unquote(params["INTERFACE_TYPE"]) iface_type = verilog.unquote(params["INTERFACE_TYPE"])
data_rate = verilog.unquote(params["DATA_RATE"]) data_rate = verilog.unquote(params["DATA_RATE"])
data_width = int(params["DATA_WIDTH"]) data_width = int(params["DATA_WIDTH"])
for i in iface_types: for i in iface_types:
for j in data_rates: for j in data_rates:
for k in data_widths: for k in data_widths:
@ -103,23 +105,28 @@ for params in data:
segmk.add_site_tag(loc, "ISERDES.NUM_CE.1", 0) segmk.add_site_tag(loc, "ISERDES.NUM_CE.1", 0)
segmk.add_site_tag(loc, "ISERDES.NUM_CE.2", 1) segmk.add_site_tag(loc, "ISERDES.NUM_CE.2", 1)
for i in range(1, 4+1): for i in range(1, 4 + 1):
if ("INIT_Q%d" % i) in params: if ("INIT_Q%d" % i) in params:
segmk.add_site_tag(loc, "IFF.ZINIT_Q%d" % i, not params["INIT_Q%d" % i]) segmk.add_site_tag(
loc, "IFF.ZINIT_Q%d" % i, not params["INIT_Q%d" % i])
for i in range(1, 4+1): for i in range(1, 4 + 1):
if ("SRVAL_Q%d" % i) in params: if ("SRVAL_Q%d" % i) in params:
segmk.add_site_tag(loc, "IFF.ZSRVAL_Q%d" % i, not params["SRVAL_Q%d" % i]) segmk.add_site_tag(
loc, "IFF.ZSRVAL_Q%d" % i, not params["SRVAL_Q%d" % i])
if "IS_D_INVERTED" in params: if "IS_D_INVERTED" in params:
segmk.add_site_tag(loc, "ZINV_D", int(params["IS_D_INVERTED"] == 0)) segmk.add_site_tag(
loc, "ZINV_D", int(params["IS_D_INVERTED"] == 0))
if "DYN_CLKDIV_INV_EN" in params: if "DYN_CLKDIV_INV_EN" in params:
value = verilog.unquote(params["DYN_CLKDIV_INV_EN"]) value = verilog.unquote(params["DYN_CLKDIV_INV_EN"])
segmk.add_site_tag(loc, "ISERDES.DYN_CLKDIV_INV_EN", int(value == "TRUE")) segmk.add_site_tag(
loc, "ISERDES.DYN_CLKDIV_INV_EN", int(value == "TRUE"))
if "DYN_CLK_INV_EN" in params: if "DYN_CLK_INV_EN" in params:
value = verilog.unquote(params["DYN_CLK_INV_EN"]) value = verilog.unquote(params["DYN_CLK_INV_EN"])
segmk.add_site_tag(loc, "ISERDES.DYN_CLK_INV_EN", int(value == "TRUE")) segmk.add_site_tag(
loc, "ISERDES.DYN_CLK_INV_EN", int(value == "TRUE"))
# This parameter actually controls muxes used both in ILOGIC and # This parameter actually controls muxes used both in ILOGIC and
# ISERDES mode. # ISERDES mode.
@ -157,7 +164,11 @@ for params in data:
# Write segments and tags for later check # Write segments and tags for later check
with open("tags.json", "w") as fp: with open("tags.json", "w") as fp:
tags = {loc_to_tile_site_map[l]: {k: int(v) for k, v in d.items()} for l, d in segmk.site_tags.items()} tags = {
loc_to_tile_site_map[l]: {k: int(v)
for k, v in d.items()}
for l, d in segmk.site_tags.items()
}
json.dump(tags, fp, sort_keys=True, indent=1) json.dump(tags, fp, sort_keys=True, indent=1)
@ -166,5 +177,6 @@ def bitfilter(frame_idx, bit_idx):
return False return False
return True return True
segmk.compile(bitfilter=bitfilter) segmk.compile(bitfilter=bitfilter)
segmk.write() segmk.write()

79
fuzzers/035b-iob-iserdes/top.py
View File

@ -13,7 +13,7 @@ from prjxray.db import Database
# ============================================================================= # =============================================================================
def gen_sites(): def gen_sites():
db = Database(util.get_db_root()) db = Database(util.get_db_root())
grid = db.grid() grid = db.grid()
@ -78,44 +78,65 @@ wire [{N}:0] do_buf;
# Bottom site # Bottom site
if random.randint(0, 1): if random.randint(0, 1):
iob_i = sites[1] iob_i = sites[1]
iob_o = sites[3] iob_o = sites[3]
ilogic = sites[2] ilogic = sites[2]
# Top site # Top site
else: else:
iob_i = sites[3] iob_i = sites[3]
iob_o = sites[1] iob_o = sites[1]
ilogic = sites[4] ilogic = sites[4]
# Site params # Site params
params = { params = {
"_LOC": verilog.quote(ilogic), "_LOC":
"IS_USED": int(random.randint(0, 10) > 0), # Make it used more often verilog.quote(ilogic),
"INIT_Q1": random.randint(0, 1), "IS_USED":
"INIT_Q2": random.randint(0, 1), int(random.randint(0, 10) > 0), # Make it used more often
"INIT_Q3": random.randint(0, 1), "INIT_Q1":
"INIT_Q4": random.randint(0, 1), random.randint(0, 1),
"SRVAL_Q1": random.randint(0, 1), "INIT_Q2":
"SRVAL_Q2": random.randint(0, 1), random.randint(0, 1),
"SRVAL_Q3": random.randint(0, 1), "INIT_Q3":
"SRVAL_Q4": random.randint(0, 1), random.randint(0, 1),
"NUM_CE": random.randint(1, 2), "INIT_Q4":
random.randint(0, 1),
"SRVAL_Q1":
random.randint(0, 1),
"SRVAL_Q2":
random.randint(0, 1),
"SRVAL_Q3":
random.randint(0, 1),
"SRVAL_Q4":
random.randint(0, 1),
"NUM_CE":
random.randint(1, 2),
# The following one shows negative correlation (0 - not inverted) # The following one shows negative correlation (0 - not inverted)
"IS_D_INVERTED": random.randint(0, 1), "IS_D_INVERTED":
random.randint(0, 1),
# No bits were found for parameters below # No bits were found for parameters below
#"IS_OCLKB_INVERTED": random.randint(0, 1), #"IS_OCLKB_INVERTED": random.randint(0, 1),
#"IS_OCLK_INVERTED": random.randint(0, 1), #"IS_OCLK_INVERTED": random.randint(0, 1),
#"IS_CLKDIVP_INVERTED": random.randint(0, 1), #"IS_CLKDIVP_INVERTED": random.randint(0, 1),
#"IS_CLKDIV_INVERTED": random.randint(0, 1), #"IS_CLKDIV_INVERTED": random.randint(0, 1),
#"IS_CLKB_INVERTED": random.randint(0, 1), #"IS_CLKB_INVERTED": random.randint(0, 1),
#"IS_CLK_INVERTED": random.randint(0, 1), #"IS_CLK_INVERTED": random.randint(0, 1),
"DYN_CLKDIV_INV_EN": verilog.quote(random.choice(["TRUE", "FALSE"])), "DYN_CLKDIV_INV_EN":
"DYN_CLK_INV_EN": verilog.quote(random.choice(["TRUE", "FALSE"])), verilog.quote(random.choice(["TRUE", "FALSE"])),
"IOBDELAY": verilog.quote(random.choice(["NONE", "IBUF", "IFD", "BOTH"])), "DYN_CLK_INV_EN":
"OFB_USED": verilog.quote(random.choice(["TRUE"] + ["FALSE"]*9)), # Force more FALSEs verilog.quote(random.choice(["TRUE", "FALSE"])),
"IOBDELAY":
verilog.quote(random.choice(["NONE", "IBUF", "IFD", "BOTH"])),
"OFB_USED":
verilog.quote(
random.choice(["TRUE"] + ["FALSE"] * 9)), # Force more FALSEs
} }
iface_type = random.choice(["NETWORKING", "OVERSAMPLE", "MEMORY", "MEMORY_DDR3", "MEMORY_QDR"]) iface_type = random.choice(
[
"NETWORKING", "OVERSAMPLE", "MEMORY", "MEMORY_DDR3",
"MEMORY_QDR"
])
data_rate = random.choice(["SDR", "DDR"]) data_rate = random.choice(["SDR", "DDR"])
serdes_mode = random.choice(["MASTER", "SLAVE"]) serdes_mode = random.choice(["MASTER", "SLAVE"])
@ -138,7 +159,7 @@ wire [{N}:0] do_buf;
if verilog.unquote(params["OFB_USED"]) == "TRUE": if verilog.unquote(params["OFB_USED"]) == "TRUE":
params["IOBDELAY"] = verilog.quote("NONE") params["IOBDELAY"] = verilog.quote("NONE")
# Instantiate cell # Instantiate cell
param_str = ",".join(".%s(%s)" % (k, v) for k, v in params.items()) param_str = ",".join(".%s(%s)" % (k, v) for k, v in params.items())
print('') print('')