mirror of https://github.com/openXC7/prjxray.git
Initial fuzzer for ISERDES only.
Signed-off-by: Maciej Kurc <mkurc@antmicro.com>
This commit is contained in:
Maciej Kurc
parent
073577dd96
commit
a2552bf478
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@ -0,0 +1,22 @@
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N := 50
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include ../fuzzer.mk
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database: build/segbits_xiob33.db
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build/segbits_xiob33_msk.rdb: $(SPECIMENS_OK)
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#${XRAY_SEGMATCH} -c -1 -m 1 -M 1 -o build/segbits_xiob33.rdb $$(find -name segdata_*.txt)
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#python3 ~/Work/segmask.py -i build/segbits_xiob33.rdb -o build/segbits_xiob33_msk.rdb -m IN_USE
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python3 ~/Work/lms_solver.py -o build/segbits_xiob33_msk.rdb -m IN_USE $$(find -name segdata_*.txt)
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build/segbits_xiob33.db: build/segbits_xiob33_msk.rdb
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${XRAY_DBFIXUP} --db-root build --zero-db bits.dbf --seg-fn-in $^ --seg-fn-out $@
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${XRAY_MASKMERGE} build/mask_xiob33.db $$(find -name segdata_*.txt)
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pushdb:
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${XRAY_MERGEDB} liob33 build/segbits_xiob33.db
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${XRAY_MERGEDB} riob33 build/segbits_xiob33.db
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${XRAY_MERGEDB} mask_liob33 build/mask_xiob33.db
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${XRAY_MERGEDB} mask_riob33 build/mask_xiob33.db
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.PHONY: database pushdb
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@ -0,0 +1,170 @@
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#!/usr/bin/env python3
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import json
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import re
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from prjxray.segmaker import Segmaker
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from prjxray import util
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from prjxray import verilog
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segmk = Segmaker("design.bits")
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# Load tags
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with open("params.json", "r") as fp:
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data = json.load(fp)
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iface_types = ["NETWORKING", "OVERSAMPLE", "MEMORY", "MEMORY_DDR3", "MEMORY_QDR"]
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data_rates = ["SDR", "DDR"]
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data_widths = [2, 3, 4, 5, 6, 7, 8, 10, 14]
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# Output tags
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loc_to_tile_site_map = {}
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for params in data:
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loc = verilog.unquote(params["_LOC"])
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loc = loc.replace("ILOGIC", "IOB")
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get_xy = util.create_xy_fun('IOB_')
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x, y = get_xy(loc)
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loc_to_tile_site_map[loc] = params["TILE"] + ".IOB_X0Y%d" % (y % 2)
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# Serdes not used at all
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if not params["IS_USED"]:
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segmk.add_site_tag(loc, "ISERDES.IN_USE", 0)
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segmk.add_site_tag(loc, "ISERDES.MODE.MASTER", 0)
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segmk.add_site_tag(loc, "ISERDES.MODE.SLAVE", 0)
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for i in iface_types:
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if i == "NETWORKING":
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for j in data_rates:
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for k in data_widths:
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tag = "ISERDES.%s.%s.%s" % (i, j, k)
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segmk.add_site_tag(loc, tag, 0)
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else:
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for j in data_rates:
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segmk.add_site_tag(loc, "ISERDES.%s.%s.4" % (i, j), 0)
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segmk.add_site_tag(loc, "ISERDES.NUM_CE.1", 0)
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segmk.add_site_tag(loc, "ISERDES.NUM_CE.2", 0)
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for i in range(1, 4+1):
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segmk.add_site_tag(loc, "IFF.ZINIT_Q%d" % i, 0)
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for i in range(1, 4+1):
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segmk.add_site_tag(loc, "IFF.ZSRVAL_Q%d" % i, 0)
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segmk.add_site_tag(loc, "ZINV_D", 0)
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segmk.add_site_tag(loc, "ISERDES.DYN_CLKDIV_INV_EN", 0)
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segmk.add_site_tag(loc, "ISERDES.DYN_CLK_INV_EN", 0)
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segmk.add_site_tag(loc, "IFFDELMUXE3.0", 1)
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segmk.add_site_tag(loc, "IFFDELMUXE3.1", 0)
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segmk.add_site_tag(loc, "IDELMUXE3.0", 1)
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segmk.add_site_tag(loc, "IDELMUXE3.1", 0)
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segmk.add_site_tag(loc, "ISERDES.OFB_USED", 0)
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# Serdes used
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else:
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segmk.add_site_tag(loc, "ISERDES.IN_USE", 1)
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if "SERDES_MODE" in params:
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value = verilog.unquote(params["SERDES_MODE"])
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if value == "MASTER":
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segmk.add_site_tag(loc, "ISERDES.MODE.MASTER", 1)
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segmk.add_site_tag(loc, "ISERDES.MODE.SLAVE", 0)
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if value == "SLAVE":
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segmk.add_site_tag(loc, "ISERDES.MODE.MASTER", 0)
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segmk.add_site_tag(loc, "ISERDES.MODE.SLAVE", 1)
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iface_type = verilog.unquote(params["INTERFACE_TYPE"])
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data_rate = verilog.unquote(params["DATA_RATE"])
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data_width = int(params["DATA_WIDTH"])
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for i in iface_types:
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for j in data_rates:
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for k in data_widths:
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tag = "ISERDES.%s.%s.%s" % (i, j, k)
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if i == iface_type:
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if j == data_rate:
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if k == data_width:
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segmk.add_site_tag(loc, tag, 1)
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if "NUM_CE" in params:
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value = params["NUM_CE"]
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if value == 1:
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segmk.add_site_tag(loc, "ISERDES.NUM_CE.1", 1)
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segmk.add_site_tag(loc, "ISERDES.NUM_CE.2", 0)
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if value == 2:
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segmk.add_site_tag(loc, "ISERDES.NUM_CE.1", 0)
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segmk.add_site_tag(loc, "ISERDES.NUM_CE.2", 1)
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for i in range(1, 4+1):
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if ("INIT_Q%d" % i) in params:
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segmk.add_site_tag(loc, "IFF.ZINIT_Q%d" % i, not params["INIT_Q%d" % i])
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for i in range(1, 4+1):
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if ("SRVAL_Q%d" % i) in params:
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segmk.add_site_tag(loc, "IFF.ZSRVAL_Q%d" % i, not params["SRVAL_Q%d" % i])
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if "IS_D_INVERTED" in params:
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segmk.add_site_tag(loc, "ZINV_D", int(params["IS_D_INVERTED"] == 0))
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if "DYN_CLKDIV_INV_EN" in params:
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value = verilog.unquote(params["DYN_CLKDIV_INV_EN"])
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segmk.add_site_tag(loc, "ISERDES.DYN_CLKDIV_INV_EN", int(value == "TRUE"))
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if "DYN_CLK_INV_EN" in params:
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value = verilog.unquote(params["DYN_CLK_INV_EN"])
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segmk.add_site_tag(loc, "ISERDES.DYN_CLK_INV_EN", int(value == "TRUE"))
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# This parameter actually controls muxes used both in ILOGIC and
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# ISERDES mode.
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if "IOBDELAY" in params:
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value = verilog.unquote(params["IOBDELAY"])
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if value == "NONE":
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#segmk.add_site_tag(loc, "IOBDELAY_NONE", 1)
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segmk.add_site_tag(loc, "IFFDELMUXE3.0", 0)
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segmk.add_site_tag(loc, "IFFDELMUXE3.1", 1)
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segmk.add_site_tag(loc, "IDELMUXE3.0", 0)
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segmk.add_site_tag(loc, "IDELMUXE3.1", 1)
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if value == "IBUF":
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#segmk.add_site_tag(loc, "IOBDELAY_IBUF", 1)
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segmk.add_site_tag(loc, "IFFDELMUXE3.0", 0)
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segmk.add_site_tag(loc, "IFFDELMUXE3.1", 1)
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segmk.add_site_tag(loc, "IDELMUXE3.0", 1)
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segmk.add_site_tag(loc, "IDELMUXE3.1", 0)
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if value == "IFD":
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#segmk.add_site_tag(loc, "IOBDELAY_IFD" , 1)
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segmk.add_site_tag(loc, "IFFDELMUXE3.0", 1)
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segmk.add_site_tag(loc, "IFFDELMUXE3.1", 0)
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segmk.add_site_tag(loc, "IDELMUXE3.0", 0)
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segmk.add_site_tag(loc, "IDELMUXE3.1", 1)
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if value == "BOTH":
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#segmk.add_site_tag(loc, "IOBDELAY_BOTH", 1)
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segmk.add_site_tag(loc, "IFFDELMUXE3.0", 1)
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segmk.add_site_tag(loc, "IFFDELMUXE3.1", 0)
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segmk.add_site_tag(loc, "IDELMUXE3.0", 1)
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segmk.add_site_tag(loc, "IDELMUXE3.1", 0)
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if "OFB_USED" in params:
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value = verilog.unquote(params["OFB_USED"])
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if value == "TRUE":
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segmk.add_site_tag(loc, "ISERDES.OFB_USED", 1)
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# Write segments and tags for later check
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with open("tags.json", "w") as fp:
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tags = {loc_to_tile_site_map[l]: {k: int(v) for k, v in d.items()} for l, d in segmk.site_tags.items()}
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json.dump(tags, fp, sort_keys=True, indent=1)
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def bitfilter(frame_idx, bit_idx):
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if frame_idx < 25 or frame_idx > 31:
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return False
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return True
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segmk.compile(bitfilter=bitfilter)
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segmk.write()
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@ -0,0 +1,24 @@
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set_param general.maxThreads 1
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create_project -force -part $::env(XRAY_PART) design design
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read_verilog top.v
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synth_design -top top
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set_property CFGBVS VCCO [current_design]
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set_property CONFIG_VOLTAGE 3.3 [current_design]
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set_property BITSTREAM.GENERAL.PERFRAMECRC YES [current_design]
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set_param tcl.collectionResultDisplayLimit 0
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set_property IS_ENABLED 0 [get_drc_checks {NSTD-1}]
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set_property IS_ENABLED 0 [get_drc_checks {UCIO-1}]
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set_property IS_ENABLED 0 [get_drc_checks {REQP-98}]
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set_property IS_ENABLED 0 [get_drc_checks {REQP-109}]
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set_property IS_ENABLED 0 [get_drc_checks {REQP-111}]
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set_property IS_ENABLED 0 [get_drc_checks {REQP-103}]
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set_property IS_ENABLED 0 [get_drc_checks {PDRC-26}]
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place_design
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route_design
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write_checkpoint -force design.dcp
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write_bitstream -force design.bit
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@ -0,0 +1,283 @@
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#!/usr/bin/env python3
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import os, random
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random.seed(int(os.getenv("SEED"), 16))
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import re
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import json
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from prjxray import util
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from prjxray import verilog
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from prjxray.db import Database
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# =============================================================================
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def gen_sites():
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db = Database(util.get_db_root())
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grid = db.grid()
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tile_list = []
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for tile_name in sorted(grid.tiles()):
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if "IOB33" not in tile_name or "SING" in tile_name:
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continue
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tile_list.append(tile_name)
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get_xy = util.create_xy_fun('[LR]IOB33_')
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tile_list.sort(key=get_xy)
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for iob_tile_name in tile_list:
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iob_gridinfo = grid.gridinfo_at_loc(
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grid.loc_of_tilename(iob_tile_name))
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# Find IOI tile adjacent to IOB
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for suffix in ["IOI3", "IOI3_TBYTESRC", "IOI3_TBYTETERM"]:
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try:
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ioi_tile_name = iob_tile_name.replace("IOB33", suffix)
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ioi_gridinfo = grid.gridinfo_at_loc(
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grid.loc_of_tilename(ioi_tile_name))
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break
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except KeyError:
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pass
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iob33s = [k for k, v in iob_gridinfo.sites.items() if v == "IOB33S"][0]
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iob33m = [k for k, v in iob_gridinfo.sites.items() if v == "IOB33M"][0]
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ilogic_s = iob33s.replace("IOB", "ILOGIC")
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ilogic_m = iob33m.replace("IOB", "ILOGIC")
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yield iob_tile_name, iob33m, ilogic_m, iob33s, ilogic_s
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def run():
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# Get all [LR]IOI3 tiles
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tiles = list(gen_sites())
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# Header
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print("// Tile count: %d" % len(tiles))
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print("// Seed: '%s'" % os.getenv("SEED"))
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print(
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'''
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module top (
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(* CLOCK_BUFFER_TYPE = "NONE" *)
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input wire clk1,
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(* CLOCK_BUFFER_TYPE = "NONE" *)
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input wire clk2,
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input wire [{N}:0] di,
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output wire [{N}:0] do
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);
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wire [{N}:0] di_buf;
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wire [{N}:0] do_buf;
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'''.format(**{"N": len(tiles) - 1}))
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# LOCes IOBs
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data = []
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for i, sites in enumerate(tiles):
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tile_name = sites[0]
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# Bottom site
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if random.randint(0, 1):
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iob_i = sites[1]
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iob_o = sites[3]
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ilogic = sites[2]
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# Top site
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else:
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iob_i = sites[3]
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iob_o = sites[1]
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ilogic = sites[4]
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# Site params
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params = {
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"_LOC": verilog.quote(ilogic),
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"IS_USED": int(random.randint(0, 10) > 0), # Make it used more often
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"INIT_Q1": random.randint(0, 1),
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"INIT_Q2": random.randint(0, 1),
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"INIT_Q3": random.randint(0, 1),
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"INIT_Q4": random.randint(0, 1),
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"SRVAL_Q1": random.randint(0, 1),
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"SRVAL_Q2": random.randint(0, 1),
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"SRVAL_Q3": random.randint(0, 1),
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"SRVAL_Q4": random.randint(0, 1),
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"NUM_CE": random.randint(1, 2),
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# The following one shows negative correlation (0 - not inverted)
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"IS_D_INVERTED": random.randint(0, 1),
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# No bits were found for parameters below
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#"IS_OCLKB_INVERTED": random.randint(0, 1),
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#"IS_OCLK_INVERTED": random.randint(0, 1),
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#"IS_CLKDIVP_INVERTED": random.randint(0, 1),
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#"IS_CLKDIV_INVERTED": random.randint(0, 1),
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#"IS_CLKB_INVERTED": random.randint(0, 1),
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#"IS_CLK_INVERTED": random.randint(0, 1),
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"DYN_CLKDIV_INV_EN": verilog.quote(random.choice(["TRUE", "FALSE"])),
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"DYN_CLK_INV_EN": verilog.quote(random.choice(["TRUE", "FALSE"])),
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"IOBDELAY": verilog.quote(random.choice(["NONE", "IBUF", "IFD", "BOTH"])),
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"OFB_USED": verilog.quote(random.choice(["TRUE"] + ["FALSE"]*9)), # Force more FALSEs
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}
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iface_type = random.choice(["NETWORKING", "OVERSAMPLE", "MEMORY", "MEMORY_DDR3", "MEMORY_QDR"])
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data_rate = random.choice(["SDR", "DDR"])
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serdes_mode = random.choice(["MASTER", "SLAVE"])
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params["INTERFACE_TYPE"] = verilog.quote(iface_type)
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params["DATA_RATE"] = verilog.quote(data_rate)
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params["SERDES_MODE"] = verilog.quote(serdes_mode)
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# Networking mode
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if iface_type == "NETWORKING":
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data_widths = {
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"SDR": [2, 3, 4, 5, 6, 7, 8],
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"DDR": [4, 6, 8, 10, 14],
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}
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params["DATA_WIDTH"] = random.choice(data_widths[data_rate])
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# Others
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else:
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params["DATA_WIDTH"] = 4
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if verilog.unquote(params["OFB_USED"]) == "TRUE":
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params["IOBDELAY"] = verilog.quote("NONE")
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# Instantiate cell
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param_str = ",".join(".%s(%s)" % (k, v) for k, v in params.items())
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print('')
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print('(* LOC="%s", KEEP, DONT_TOUCH *)' % iob_i)
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print('IBUF ibuf_%03d (.I(di[%3d]), .O(di_buf[%3d]));' % (i, i, i))
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print('(* LOC="%s", KEEP, DONT_TOUCH *)' % iob_o)
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print('OBUF obuf_%03d (.I(do_buf[%3d]), .O(do[%3d]));' % (i, i, i))
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print(
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'iserdes_single #(%s) iserdes_%03d (.clk1(clk1), .clk2(clk2), .I(di_buf[%3d]), .O(do_buf[%3d]));'
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% (param_str, i, i, i))
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params["TILE"] = tile_name
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data.append(params)
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# Store params
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with open("params.json", "w") as fp:
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json.dump(data, fp, sort_keys=True, indent=1)
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print(
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'''
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endmodule
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(* KEEP, DONT_TOUCH *)
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module iserdes_single(
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input wire clk1,
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input wire clk2,
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input wire I,
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output wire O
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);
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parameter _LOC = "";
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parameter IS_USED = 1;
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parameter INTERFACE_TYPE = "NETWORKING";
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parameter DATA_RATE = "DDR";
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parameter DATA_WIDTH = 4;
|
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parameter SERDES_MODE = "MASTER";
|
||||
parameter NUM_CE = 2;
|
||||
parameter INIT_Q1 = 0;
|
||||
parameter INIT_Q2 = 0;
|
||||
parameter INIT_Q3 = 0;
|
||||
parameter INIT_Q4 = 0;
|
||||
parameter SRVAL_Q1 = 0;
|
||||
parameter SRVAL_Q2 = 0;
|
||||
parameter SRVAL_Q3 = 0;
|
||||
parameter SRVAL_Q4 = 0;
|
||||
parameter IS_D_INVERTED = 0;
|
||||
parameter IS_OCLK_INVERTED = 0;
|
||||
parameter IS_OCLKB_INVERTED = 0;
|
||||
parameter IS_CLK_INVERTED = 0;
|
||||
parameter IS_CLKB_INVERTED = 0;
|
||||
parameter IS_CLKDIV_INVERTED = 0;
|
||||
parameter IS_CLKDIVP_INVERTED = 0;
|
||||
parameter DYN_CLKDIV_INV_EN = "FALSE";
|
||||
parameter DYN_CLK_INV_EN = "FALSE";
|
||||
parameter IOBDELAY = "NONE";
|
||||
parameter OFB_USED = "FALSE";
|
||||
|
||||
(* KEEP, DONT_TOUCH *)
|
||||
wire [7:0] x;
|
||||
|
||||
generate if (IS_USED) begin
|
||||
|
||||
// Single ISERDES
|
||||
(* LOC=_LOC, KEEP, DONT_TOUCH *)
|
||||
ISERDESE2 #
|
||||
(
|
||||
.INTERFACE_TYPE(INTERFACE_TYPE),
|
||||
.DATA_RATE(DATA_RATE),
|
||||
.DATA_WIDTH(DATA_WIDTH),
|
||||
.SERDES_MODE(SERDES_MODE),
|
||||
.NUM_CE(NUM_CE),
|
||||
.IS_D_INVERTED(IS_D_INVERTED),
|
||||
.IS_OCLK_INVERTED(IS_OCLK_INVERTED),
|
||||
.IS_OCLKB_INVERTED(IS_OCLKB_INVERTED),
|
||||
.IS_CLK_INVERTED(IS_CLK_INVERTED),
|
||||
.IS_CLKB_INVERTED(IS_CLKB_INVERTED),
|
||||
.IS_CLKDIV_INVERTED(IS_CLKDIV_INVERTED),
|
||||
.IS_CLKDIVP_INVERTED(IS_CLKDIVP_INVERTED),
|
||||
.INIT_Q1(INIT_Q1),
|
||||
.INIT_Q2(INIT_Q2),
|
||||
.INIT_Q3(INIT_Q3),
|
||||
.INIT_Q4(INIT_Q4),
|
||||
.SRVAL_Q1(SRVAL_Q1),
|
||||
.SRVAL_Q2(SRVAL_Q2),
|
||||
.SRVAL_Q3(SRVAL_Q3),
|
||||
.SRVAL_Q4(SRVAL_Q4),
|
||||
.DYN_CLKDIV_INV_EN(DYN_CLKDIV_INV_EN),
|
||||
.DYN_CLK_INV_EN(DYN_CLK_INV_EN),
|
||||
.IOBDELAY(IOBDELAY),
|
||||
.OFB_USED(OFB_USED)
|
||||
)
|
||||
isedres
|
||||
(
|
||||
.D(I),
|
||||
.DDLY(),
|
||||
.OFB(),
|
||||
//.TFB(),
|
||||
.CE1(),
|
||||
.CE2(),
|
||||
.DYNCLKSEL(),
|
||||
.CLK(clk1),
|
||||
.CLKB(clk2),
|
||||
.OCLK(),
|
||||
.DYNCLKDIVSEL(),
|
||||
.CLKDIV(),
|
||||
.CLKDIVP(),
|
||||
.RST(),
|
||||
.BITSLIP(),
|
||||
.O(),
|
||||
.Q1(x[0]),
|
||||
.Q2(x[1]),
|
||||
.Q3(x[2]),
|
||||
.Q4(x[3]),
|
||||
.Q5(x[4]),
|
||||
.Q6(x[5]),
|
||||
.Q7(x[6]),
|
||||
.Q8(x[7]),
|
||||
.SHIFTOUT1(),
|
||||
.SHIFTOUT2()
|
||||
);
|
||||
|
||||
end else begin
|
||||
|
||||
assign x[0] = I;
|
||||
assign x[1] = I;
|
||||
assign x[2] = I;
|
||||
assign x[3] = I;
|
||||
assign x[4] = I;
|
||||
assign x[5] = I;
|
||||
assign x[6] = I;
|
||||
assign x[7] = I;
|
||||
|
||||
end endgenerate
|
||||
|
||||
// Output
|
||||
assign O = |x;
|
||||
|
||||
endmodule
|
||||
''')
|
||||
|
||||
|
||||
run()
|
||||
Loading…
Reference in New Issue