From 369aa38c6ae2f714c5bbe39546cfc92ddb42cd56 Mon Sep 17 00:00:00 2001 From: Maciej Kurc Date: Mon, 22 Jul 2019 10:52:45 +0200 Subject: [PATCH] Ran make format-py Signed-off-by: Maciej Kurc --- fuzzers/035b-iob-iserdes/generate.py | 46 ++++++++++------ fuzzers/035b-iob-iserdes/top.py | 79 ++++++++++++++++++---------- 2 files changed, 79 insertions(+), 46 deletions(-) diff --git a/fuzzers/035b-iob-iserdes/generate.py b/fuzzers/035b-iob-iserdes/generate.py index 55f31edf..25da34a9 100644 --- a/fuzzers/035b-iob-iserdes/generate.py +++ b/fuzzers/035b-iob-iserdes/generate.py @@ -12,8 +12,10 @@ segmk = Segmaker("design.bits") with open("params.json", "r") as fp: data = json.load(fp) -iface_types = ["NETWORKING", "OVERSAMPLE", "MEMORY", "MEMORY_DDR3", "MEMORY_QDR"] -data_rates = ["SDR", "DDR"] +iface_types = [ + "NETWORKING", "OVERSAMPLE", "MEMORY", "MEMORY_DDR3", "MEMORY_QDR" +] +data_rates = ["SDR", "DDR"] data_widths = [2, 3, 4, 5, 6, 7, 8, 10, 14] # Output tags @@ -33,7 +35,7 @@ for params in data: segmk.add_site_tag(loc, "ISERDES.IN_USE", 0) segmk.add_site_tag(loc, "ISERDES.MODE.MASTER", 0) - segmk.add_site_tag(loc, "ISERDES.MODE.SLAVE", 0) + segmk.add_site_tag(loc, "ISERDES.MODE.SLAVE", 0) for i in iface_types: if i == "NETWORKING": @@ -48,10 +50,10 @@ for params in data: segmk.add_site_tag(loc, "ISERDES.NUM_CE.1", 0) segmk.add_site_tag(loc, "ISERDES.NUM_CE.2", 0) - for i in range(1, 4+1): + for i in range(1, 4 + 1): segmk.add_site_tag(loc, "IFF.ZINIT_Q%d" % i, 0) - for i in range(1, 4+1): + for i in range(1, 4 + 1): segmk.add_site_tag(loc, "IFF.ZSRVAL_Q%d" % i, 0) segmk.add_site_tag(loc, "ZINV_D", 0) @@ -75,15 +77,15 @@ for params in data: value = verilog.unquote(params["SERDES_MODE"]) if value == "MASTER": segmk.add_site_tag(loc, "ISERDES.MODE.MASTER", 1) - segmk.add_site_tag(loc, "ISERDES.MODE.SLAVE", 0) + segmk.add_site_tag(loc, "ISERDES.MODE.SLAVE", 0) if value == "SLAVE": segmk.add_site_tag(loc, "ISERDES.MODE.MASTER", 0) - segmk.add_site_tag(loc, "ISERDES.MODE.SLAVE", 1) + segmk.add_site_tag(loc, "ISERDES.MODE.SLAVE", 1) iface_type = verilog.unquote(params["INTERFACE_TYPE"]) - data_rate = verilog.unquote(params["DATA_RATE"]) + data_rate = verilog.unquote(params["DATA_RATE"]) data_width = int(params["DATA_WIDTH"]) - + for i in iface_types: for j in data_rates: for k in data_widths: @@ -103,23 +105,28 @@ for params in data: segmk.add_site_tag(loc, "ISERDES.NUM_CE.1", 0) segmk.add_site_tag(loc, "ISERDES.NUM_CE.2", 1) - for i in range(1, 4+1): + for i in range(1, 4 + 1): if ("INIT_Q%d" % i) in params: - segmk.add_site_tag(loc, "IFF.ZINIT_Q%d" % i, not params["INIT_Q%d" % i]) + segmk.add_site_tag( + loc, "IFF.ZINIT_Q%d" % i, not params["INIT_Q%d" % i]) - for i in range(1, 4+1): + for i in range(1, 4 + 1): if ("SRVAL_Q%d" % i) in params: - segmk.add_site_tag(loc, "IFF.ZSRVAL_Q%d" % i, not params["SRVAL_Q%d" % i]) + segmk.add_site_tag( + loc, "IFF.ZSRVAL_Q%d" % i, not params["SRVAL_Q%d" % i]) if "IS_D_INVERTED" in params: - segmk.add_site_tag(loc, "ZINV_D", int(params["IS_D_INVERTED"] == 0)) + segmk.add_site_tag( + loc, "ZINV_D", int(params["IS_D_INVERTED"] == 0)) if "DYN_CLKDIV_INV_EN" in params: value = verilog.unquote(params["DYN_CLKDIV_INV_EN"]) - segmk.add_site_tag(loc, "ISERDES.DYN_CLKDIV_INV_EN", int(value == "TRUE")) + segmk.add_site_tag( + loc, "ISERDES.DYN_CLKDIV_INV_EN", int(value == "TRUE")) if "DYN_CLK_INV_EN" in params: value = verilog.unquote(params["DYN_CLK_INV_EN"]) - segmk.add_site_tag(loc, "ISERDES.DYN_CLK_INV_EN", int(value == "TRUE")) + segmk.add_site_tag( + loc, "ISERDES.DYN_CLK_INV_EN", int(value == "TRUE")) # This parameter actually controls muxes used both in ILOGIC and # ISERDES mode. @@ -157,7 +164,11 @@ for params in data: # Write segments and tags for later check with open("tags.json", "w") as fp: - tags = {loc_to_tile_site_map[l]: {k: int(v) for k, v in d.items()} for l, d in segmk.site_tags.items()} + tags = { + loc_to_tile_site_map[l]: {k: int(v) + for k, v in d.items()} + for l, d in segmk.site_tags.items() + } json.dump(tags, fp, sort_keys=True, indent=1) @@ -166,5 +177,6 @@ def bitfilter(frame_idx, bit_idx): return False return True + segmk.compile(bitfilter=bitfilter) segmk.write() diff --git a/fuzzers/035b-iob-iserdes/top.py b/fuzzers/035b-iob-iserdes/top.py index 58ffd3fd..8edee1d6 100644 --- a/fuzzers/035b-iob-iserdes/top.py +++ b/fuzzers/035b-iob-iserdes/top.py @@ -13,7 +13,7 @@ from prjxray.db import Database # ============================================================================= -def gen_sites(): +def gen_sites(): db = Database(util.get_db_root()) grid = db.grid() @@ -78,44 +78,65 @@ wire [{N}:0] do_buf; # Bottom site if random.randint(0, 1): - iob_i = sites[1] - iob_o = sites[3] + iob_i = sites[1] + iob_o = sites[3] ilogic = sites[2] # Top site else: - iob_i = sites[3] - iob_o = sites[1] + iob_i = sites[3] + iob_o = sites[1] ilogic = sites[4] # Site params params = { - "_LOC": verilog.quote(ilogic), - "IS_USED": int(random.randint(0, 10) > 0), # Make it used more often - "INIT_Q1": random.randint(0, 1), - "INIT_Q2": random.randint(0, 1), - "INIT_Q3": random.randint(0, 1), - "INIT_Q4": random.randint(0, 1), - "SRVAL_Q1": random.randint(0, 1), - "SRVAL_Q2": random.randint(0, 1), - "SRVAL_Q3": random.randint(0, 1), - "SRVAL_Q4": random.randint(0, 1), - "NUM_CE": random.randint(1, 2), + "_LOC": + verilog.quote(ilogic), + "IS_USED": + int(random.randint(0, 10) > 0), # Make it used more often + "INIT_Q1": + random.randint(0, 1), + "INIT_Q2": + random.randint(0, 1), + "INIT_Q3": + random.randint(0, 1), + "INIT_Q4": + random.randint(0, 1), + "SRVAL_Q1": + random.randint(0, 1), + "SRVAL_Q2": + random.randint(0, 1), + "SRVAL_Q3": + random.randint(0, 1), + "SRVAL_Q4": + random.randint(0, 1), + "NUM_CE": + random.randint(1, 2), # The following one shows negative correlation (0 - not inverted) - "IS_D_INVERTED": random.randint(0, 1), + "IS_D_INVERTED": + random.randint(0, 1), # No bits were found for parameters below - #"IS_OCLKB_INVERTED": random.randint(0, 1), - #"IS_OCLK_INVERTED": random.randint(0, 1), - #"IS_CLKDIVP_INVERTED": random.randint(0, 1), - #"IS_CLKDIV_INVERTED": random.randint(0, 1), - #"IS_CLKB_INVERTED": random.randint(0, 1), - #"IS_CLK_INVERTED": random.randint(0, 1), - "DYN_CLKDIV_INV_EN": verilog.quote(random.choice(["TRUE", "FALSE"])), - "DYN_CLK_INV_EN": verilog.quote(random.choice(["TRUE", "FALSE"])), - "IOBDELAY": verilog.quote(random.choice(["NONE", "IBUF", "IFD", "BOTH"])), - "OFB_USED": verilog.quote(random.choice(["TRUE"] + ["FALSE"]*9)), # Force more FALSEs + #"IS_OCLKB_INVERTED": random.randint(0, 1), + #"IS_OCLK_INVERTED": random.randint(0, 1), + #"IS_CLKDIVP_INVERTED": random.randint(0, 1), + #"IS_CLKDIV_INVERTED": random.randint(0, 1), + #"IS_CLKB_INVERTED": random.randint(0, 1), + #"IS_CLK_INVERTED": random.randint(0, 1), + "DYN_CLKDIV_INV_EN": + verilog.quote(random.choice(["TRUE", "FALSE"])), + "DYN_CLK_INV_EN": + verilog.quote(random.choice(["TRUE", "FALSE"])), + "IOBDELAY": + verilog.quote(random.choice(["NONE", "IBUF", "IFD", "BOTH"])), + "OFB_USED": + verilog.quote( + random.choice(["TRUE"] + ["FALSE"] * 9)), # Force more FALSEs } - iface_type = random.choice(["NETWORKING", "OVERSAMPLE", "MEMORY", "MEMORY_DDR3", "MEMORY_QDR"]) + iface_type = random.choice( + [ + "NETWORKING", "OVERSAMPLE", "MEMORY", "MEMORY_DDR3", + "MEMORY_QDR" + ]) data_rate = random.choice(["SDR", "DDR"]) serdes_mode = random.choice(["MASTER", "SLAVE"]) @@ -138,7 +159,7 @@ wire [{N}:0] do_buf; if verilog.unquote(params["OFB_USED"]) == "TRUE": params["IOBDELAY"] = verilog.quote("NONE") - # Instantiate cell + # Instantiate cell param_str = ",".join(".%s(%s)" % (k, v) for k, v in params.items()) print('')