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Add EN_ECC_READ/WRITE bits. 

Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com>
This commit is contained in:
Keith Rothman 2019-01-29 18:34:12 -08:00
parent 1fc6cc7007
commit 15f411a42b
3 changed files with 15 additions and 2 deletions
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4
fuzzers/027-bram36-config/generate.py
View File

@ -3,7 +3,6 @@
import json
from prjxray.segmaker import Segmaker
from prjxray import verilog
def write_ram_ext_tags(segmk, tile_param):
@ -26,6 +25,9 @@ def main():
for tile_param in params:
write_ram_ext_tags(segmk, tile_param)
segmk.add_site_tag(tile_param['site'], 'EN_ECC_READ', tile_param['EN_ECC_READ'])
segmk.add_site_tag(tile_param['site'], 'EN_ECC_WRITE', tile_param['EN_ECC_WRITE'])
segmk.compile()
segmk.write()

3
fuzzers/027-bram36-config/generate.tcl
View File

@ -11,6 +11,9 @@ proc run {} {
set_property IS_ENABLED 0 [get_drc_checks {REQP-192}]
set_property IS_ENABLED 0 [get_drc_checks {REQP-193}]
set_property IS_ENABLED 0 [get_drc_checks {REQP-194}]
set_property IS_ENABLED 0 [get_drc_checks {AVAL-94}]
set_property IS_ENABLED 0 [get_drc_checks {AVAL-95}]
set_property IS_ENABLED 0 [get_drc_checks {PDCN-1576}]
place_design
route_design

10
fuzzers/027-bram36-config/top.py
View File

@ -28,6 +28,8 @@ module top();
for tile_name, site_name in gen_bram36():
ram_extension_a = random.choice(RAM_EXTENSION_OPTS)
ram_extension_b = random.choice(RAM_EXTENSION_OPTS)
en_ecc_read = random.randint(0, 1)
en_ecc_write = random.randint(0, 1)
print(
'''
@ -38,7 +40,9 @@ module top();
.READ_WIDTH_B(1),
.WRITE_WIDTH_B(1),
.RAM_EXTENSION_A({ram_extension_a}),
.RAM_EXTENSION_B({ram_extension_b})
.RAM_EXTENSION_B({ram_extension_b}),
.EN_ECC_READ({en_ecc_read}),
.EN_ECC_WRITE({en_ecc_write})
) bram_{site} (
.CLKARDCLK(),
.CLKBWRCLK(),
@ -66,6 +70,8 @@ module top();
site=site_name,
ram_extension_a=verilog.quote(ram_extension_a),
ram_extension_b=verilog.quote(ram_extension_b),
en_ecc_read=en_ecc_read,
en_ecc_write=en_ecc_write,
))
params.append(
@ -74,6 +80,8 @@ module top();
'site': site_name,
'RAM_EXTENSION_A': ram_extension_a,
'RAM_EXTENSION_B': ram_extension_b,
'EN_ECC_READ': en_ecc_read,
'EN_ECC_WRITE': en_ecc_write,
})
print("endmodule")