From 15f411a42bd79c39442f0115099cdae1fe822c58 Mon Sep 17 00:00:00 2001
From: Keith Rothman <537074+litghost@users.noreply.github.com>
Date: Tue, 29 Jan 2019 18:34:12 -0800
Subject: [PATCH] Add EN_ECC_READ/WRITE bits.

Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com>
---
 fuzzers/027-bram36-config/generate.py  |  4 +++-
 fuzzers/027-bram36-config/generate.tcl |  3 +++
 fuzzers/027-bram36-config/top.py       | 10 +++++++++-
 3 files changed, 15 insertions(+), 2 deletions(-)

diff --git a/fuzzers/027-bram36-config/generate.py b/fuzzers/027-bram36-config/generate.py
index 76e9835c..e76dc571 100644
--- a/fuzzers/027-bram36-config/generate.py
+++ b/fuzzers/027-bram36-config/generate.py
@@ -3,7 +3,6 @@
 import json
 
 from prjxray.segmaker import Segmaker
-from prjxray import verilog
 
 
 def write_ram_ext_tags(segmk, tile_param):
@@ -26,6 +25,9 @@ def main():
     for tile_param in params:
         write_ram_ext_tags(segmk, tile_param)
 
+        segmk.add_site_tag(tile_param['site'], 'EN_ECC_READ', tile_param['EN_ECC_READ'])
+        segmk.add_site_tag(tile_param['site'], 'EN_ECC_WRITE', tile_param['EN_ECC_WRITE'])
+
     segmk.compile()
     segmk.write()
 
diff --git a/fuzzers/027-bram36-config/generate.tcl b/fuzzers/027-bram36-config/generate.tcl
index a675ffbc..ae41001f 100644
--- a/fuzzers/027-bram36-config/generate.tcl
+++ b/fuzzers/027-bram36-config/generate.tcl
@@ -11,6 +11,9 @@ proc run {} {
     set_property IS_ENABLED 0 [get_drc_checks {REQP-192}]
     set_property IS_ENABLED 0 [get_drc_checks {REQP-193}]
     set_property IS_ENABLED 0 [get_drc_checks {REQP-194}]
+    set_property IS_ENABLED 0 [get_drc_checks {AVAL-94}]
+    set_property IS_ENABLED 0 [get_drc_checks {AVAL-95}]
+    set_property IS_ENABLED 0 [get_drc_checks {PDCN-1576}]
 
     place_design
     route_design
diff --git a/fuzzers/027-bram36-config/top.py b/fuzzers/027-bram36-config/top.py
index 7c64b620..32d9cdc7 100644
--- a/fuzzers/027-bram36-config/top.py
+++ b/fuzzers/027-bram36-config/top.py
@@ -28,6 +28,8 @@ module top();
     for tile_name, site_name in gen_bram36():
         ram_extension_a = random.choice(RAM_EXTENSION_OPTS)
         ram_extension_b = random.choice(RAM_EXTENSION_OPTS)
+        en_ecc_read = random.randint(0, 1)
+        en_ecc_write = random.randint(0, 1)
 
         print(
             '''
@@ -38,7 +40,9 @@ module top();
                 .READ_WIDTH_B(1),
                 .WRITE_WIDTH_B(1),
                 .RAM_EXTENSION_A({ram_extension_a}),
-                .RAM_EXTENSION_B({ram_extension_b})
+                .RAM_EXTENSION_B({ram_extension_b}),
+                .EN_ECC_READ({en_ecc_read}),
+                .EN_ECC_WRITE({en_ecc_write})
                 ) bram_{site} (
                     .CLKARDCLK(),
                     .CLKBWRCLK(),
@@ -66,6 +70,8 @@ module top();
                 site=site_name,
                 ram_extension_a=verilog.quote(ram_extension_a),
                 ram_extension_b=verilog.quote(ram_extension_b),
+                en_ecc_read=en_ecc_read,
+                en_ecc_write=en_ecc_write,
             ))
 
         params.append(
@@ -74,6 +80,8 @@ module top();
                 'site': site_name,
                 'RAM_EXTENSION_A': ram_extension_a,
                 'RAM_EXTENSION_B': ram_extension_b,
+                'EN_ECC_READ': en_ecc_read,
+                'EN_ECC_WRITE': en_ecc_write,
             })
 
     print("endmodule")