Add RAM extension bits for 1 bit cascades.

Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com>

fuzzers/027-bram36-config/Makefile

@@ -0,0 +1,22 @@
+# read/write width is relatively slow to resolve
+# Even slower with multi bit masks...
+N ?= 2
+
+include ../fuzzer.mk
+
+database: build/segbits_bramx.db
+
+build/segbits_bramx.rdb: $(SPECIMENS_OK)
+	${XRAY_SEGMATCH} -o build/segbits_bramx.rdb $(addsuffix /segdata_bram_[lr].txt,$(SPECIMENS))
+
+build/segbits_bramx.db: build/segbits_bramx.rdb
+	${XRAY_DBFIXUP} --db-root build --zero-db bits.dbf --seg-fn-in $^ --seg-fn-out $@
+	${XRAY_MASKMERGE} build/mask_bramx.db $(addsuffix /segdata_bram_[lr].txt,$(SPECIMENS))
+
+pushdb:
+	${XRAY_MERGEDB} bram_l build/segbits_bramx.db
+	${XRAY_MERGEDB} bram_r build/segbits_bramx.db
+	${XRAY_MERGEDB} mask_bram_l build/mask_bramx.db
+	${XRAY_MERGEDB} mask_bram_r build/mask_bramx.db
+
+.PHONY: database pushdb

fuzzers/027-bram36-config/bits.dbf

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+# Y0
+27_188,BRAM.RAMB36.RAM_EXTENSION_A_NONE_OR_UPPER
+
+# Y1
+27_187,BRAM.RAMB36.RAM_EXTENSION_B_NONE_OR_UPPER

fuzzers/027-bram36-config/generate.py

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+#!/usr/bin/env python3
+
+import json
+
+from prjxray.segmaker import Segmaker
+from prjxray import verilog
+
+
+def write_ram_ext_tags(segmk, tile_param):
+    for param in ["RAM_EXTENSION_A", "RAM_EXTENSION_B"]:
+        set_val = tile_param[param]
+        for opt in ["LOWER"]:
+            segmk.add_site_tag(
+                tile_param['site'], "{}_{}".format(param, opt), set_val == opt)
+        segmk.add_site_tag(
+            tile_param['site'], "{}_NONE_OR_UPPER".format(param, opt), set_val != "LOWER")
+
+
+def main():
+    segmk = Segmaker("design.bits")
+
+    print("Loading tags")
+    with open('params.json') as f:
+        params = json.load(f)
+
+    for tile_param in params:
+        write_ram_ext_tags(segmk, tile_param)
+
+    segmk.compile()
+    segmk.write()
+
+
+if __name__ == '__main__':
+    main()

fuzzers/027-bram36-config/generate.tcl

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+proc run {} {
+    create_project -force -part $::env(XRAY_PART) design design
+    read_verilog top.v
+    synth_design -top top
+
+    set_property CFGBVS VCCO [current_design]
+    set_property CONFIG_VOLTAGE 3.3 [current_design]
+    set_property BITSTREAM.GENERAL.PERFRAMECRC YES [current_design]
+    set_property IS_ENABLED 0 [get_drc_checks {PDCN-137}]
+    set_property IS_ENABLED 0 [get_drc_checks {REQP-191}]
+    set_property IS_ENABLED 0 [get_drc_checks {REQP-192}]
+    set_property IS_ENABLED 0 [get_drc_checks {REQP-193}]
+    set_property IS_ENABLED 0 [get_drc_checks {REQP-194}]
+
+    place_design
+    route_design
+
+    write_checkpoint -force design.dcp
+    write_bitstream -force design.bit
+}
+
+run

fuzzers/027-bram36-config/top.py

@@ -0,0 +1,86 @@
+import os
+import random
+import json
+random.seed(int(os.getenv("SEED"), 16))
+from prjxray import util
+from prjxray import verilog
+
+
+def gen_bram36():
+    for tile_name, site_name, _site_type in util.get_roi().gen_sites(
+        ['RAMBFIFO36E1']):
+        yield tile_name, site_name
+
+
+RAM_EXTENSION_OPTS = [
+    "NONE",
+    "LOWER",
+    "UPPER",
+]
+
+
+def main():
+    print('''
+module top();
+    ''')
+
+    params = []
+    for tile_name, site_name in gen_bram36():
+        ram_extension_a = random.choice(RAM_EXTENSION_OPTS)
+        ram_extension_b = random.choice(RAM_EXTENSION_OPTS)
+
+        print(
+            '''
+            (* KEEP, DONT_TOUCH, LOC = "{site}" *)
+            RAMB36E1 #(
+                .READ_WIDTH_A(1),
+                .WRITE_WIDTH_A(1),
+                .READ_WIDTH_B(1),
+                .WRITE_WIDTH_B(1),
+                .RAM_EXTENSION_A({ram_extension_a}),
+                .RAM_EXTENSION_B({ram_extension_b})
+                ) bram_{site} (
+                    .CLKARDCLK(),
+                    .CLKBWRCLK(),
+                    .ENARDEN(),
+                    .ENBWREN(),
+                    .REGCEAREGCE(),
+                    .REGCEB(),
+                    .RSTRAMARSTRAM(),
+                    .RSTRAMB(),
+                    .RSTREGARSTREG(),
+                    .RSTREGB(),
+                    .ADDRARDADDR(),
+                    .ADDRBWRADDR(),
+                    .DIADI(),
+                    .DIBDI(),
+                    .DIPADIP(),
+                    .DIPBDIP(),
+                    .WEA(),
+                    .WEBWE(),
+                    .DOADO(),
+                    .DOBDO(),
+                    .DOPADOP(),
+                    .DOPBDOP());
+            '''.format(
+                site=site_name,
+                ram_extension_a=verilog.quote(ram_extension_a),
+                ram_extension_b=verilog.quote(ram_extension_b),
+            ))
+
+        params.append(
+            {
+                'tile': tile_name,
+                'site': site_name,
+                'RAM_EXTENSION_A': ram_extension_a,
+                'RAM_EXTENSION_B': ram_extension_b,
+            })
+
+    print("endmodule")
+
+    with open('params.json', 'w') as f:
+        json.dump(params, f, indent=2)
+
+
+if __name__ == '__main__':
+    main()