2018-01-17 23:39:37 +01:00
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# Loosely based on
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# segprint -zd test_data/clb_ff/design.bits
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# FF as LDCE
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2018-01-23 03:36:20 +01:00
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CLBLM_L_X10Y102.SLICEM_X0.AFF.DMUX AX
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2018-01-23 02:49:08 +01:00
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CLBLM_L_X10Y102.SLICEM_X0.AFF.ZINI 1
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CLBLM_L_X10Y102.SLICEM_X0.AFF.ZRST 1
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CLBLM_L_X10Y102.SLICEM_X0.CEUSEDMUX 1
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2018-01-23 03:36:20 +01:00
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# CLBLM_L_X10Y102.SLICEM_X0.SRUSEDMUX 1
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2018-01-23 02:49:08 +01:00
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CLBLM_L_X10Y102.SLICEM_X0.SRUSEDMUX 1
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2018-01-17 23:39:37 +01:00
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# Note: a number of pseudo pips here
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# Omitted
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2018-01-23 03:36:20 +01:00
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INT_L_X10Y102.BYP_ALT0 EE2END0
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INT_L_X10Y102.BYP_ALT1 EL1END1
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INT_L_X10Y102.CLK_L1 GCLK_L_B11_WEST
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INT_L_X10Y102.CTRL_L1 ER1END2
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INT_L_X10Y102.FAN_ALT7 BYP_BOUNCE0
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INT_L_X10Y102.WW2BEG0 LOGIC_OUTS_L4
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2018-01-17 23:39:37 +01:00
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2018-01-23 03:36:20 +01:00
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HCLK_L_X31Y130.ENABLE_BUFFER.HCLK_CK_BUFHCLK8 1
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HCLK_L_X31Y130.HCLK_LEAF_CLK_B_BOTL5 HCLK_CK_BUFHCLK8
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2018-01-17 23:39:37 +01:00
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