mirror of https://github.com/openXC7/prjxray.git
fasm2frame FPGA assembler tool. Remove minitest rel path
Signed-off-by: John McMaster <johndmcmaster@gmail.com>
This commit is contained in:
John McMaster
parent
b5960c9b55
commit
e995034158
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@ -1,5 +1,5 @@
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all:
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bash ../util/runme.sh
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bash $$XRAY_DIR/minitests/util/runme.sh
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clean:
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rm -rf specimen_[0-9][0-9][0-9]/ seg_clblx.segbits vivado*.log vivado_*.str vivado*.jou design *.bits *.dcp *.bit design.txt .Xil
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@ -1,7 +1,7 @@
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#!/bin/bash
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set -ex
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vivado -mode batch -source ../util/runme.tcl
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vivado -mode batch -source $XRAY_DIR/minitests/util/runme.tcl
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${XRAY_BITREAD} -F $XRAY_ROI_FRAMES -o design.bits -z -y design.bit
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test -z "$(fgrep CRITICAL vivado.log)"
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${XRAY_SEGPRINT} -z -D design.bits >design.txt
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@ -0,0 +1,242 @@
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#!/usr/bin/env python3
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import os
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import re
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import sys
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import json
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# Based on segprint function
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# Modified to return dict instead of list
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segbitsdb = dict()
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def get_database(segtype):
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if segtype in segbitsdb:
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return segbitsdb[segtype]
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segbitsdb[segtype] = {}
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with open("%s/%s/segbits_%s.db" % (os.getenv("XRAY_DATABASE_DIR"),
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os.getenv("XRAY_DATABASE"), segtype),
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"r") as f:
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for line in f:
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# CLBLM_L.SLICEL_X1.ALUT.INIT[10] 29_14
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parts = line.split()
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name = parts[0]
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vals = parts[1:]
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segbitsdb[segtype][name] = vals
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with open("%s/%s/segbits_int_%s.db" %
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(os.getenv("XRAY_DATABASE_DIR"), os.getenv("XRAY_DATABASE"),
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segtype[-1]), "r") as f:
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for line in f:
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# CLBLM_L.SLICEL_X1.ALUT.INIT[10] 29_14
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parts = line.split()
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name = parts[0]
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vals = parts[1:]
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segbitsdb[segtype][name] = vals
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return segbitsdb[segtype]
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def dump_frames_verbose(frames):
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print()
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print("Frames: %d" % len(frames))
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for addr in sorted(frames.keys()):
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words = frames[addr]
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print(
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'0x%08X ' % addr + ', '.join(['0x%08X' % w
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for w in words]) + '...')
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def dump_frames_sparse(frames):
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print()
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print("Frames: %d" % len(frames))
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for addr in sorted(frames.keys()):
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words = frames[addr]
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# Skip frames without filled words
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for w in words:
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if w:
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break
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else:
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continue
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print('Frame @ 0x%08X' % addr)
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for i, w in enumerate(words):
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if w:
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print(' % 3d: 0x%08X' % (i, w))
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def dump_frm(f, frames):
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'''Write a .frm file given a list of frames, each containing a list of 101 32 bit words'''
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for addr in sorted(frames.keys()):
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words = frames[addr]
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f.write(
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'0x%08X ' % addr + ','.join(['0x%08X' % w for w in words]) + '\n')
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def run(f_in, f_out, sparse=False, debug=False):
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# address to array of 101 32 bit words
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frames = {}
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def frames_init():
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'''Set all frames to 0'''
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for segj in grid['segments'].values():
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seg_baseaddr, seg_word_base = segj['baseaddr']
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seg_baseaddr = int(seg_baseaddr, 0)
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for coli in range(segj['frames']):
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frame_init(seg_baseaddr + coli)
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def frame_init(addr):
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'''Set given frame to 0'''
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if not addr in frames:
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frames[addr] = [0 for _i in range(101)]
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def frame_set(frame_addr, word_addr, bit_index):
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'''Set given bit in given frame address and word'''
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frames[frame_addr][word_addr] |= 1 << bit_index
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with open("%s/%s/tilegrid.json" % (os.getenv("XRAY_DATABASE_DIR"),
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os.getenv("XRAY_DATABASE")), "r") as f:
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grid = json.load(f)
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if not sparse:
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# Initiaize bitstream to 0
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frames_init()
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for l in f_in:
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# Comment
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# Remove all text including and after #
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i = l.rfind('#')
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if i >= 0:
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l = l[0:i]
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l = l.strip()
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# Ignore blank lines
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if not l:
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continue
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# tile.site.stuff value
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# INT_L_X10Y102.CENTER_INTER_L.IMUX_L1 EE2END0
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m = re.match(
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r'([a-zA-Z0-9_]+)[.]([a-zA-Z0-9_]+)[.]([a-zA-Z0-9_.\[\]]+)[ ](.+)',
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l)
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if not m:
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raise Exception("Bad line: %s" % l)
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tile = m.group(1)
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site = m.group(2)
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suffix = m.group(3)
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value = m.group(4)
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tilej = grid['tiles'][tile]
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seg = tilej['segment']
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segj = grid['segments'][seg]
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seg_baseaddr, seg_word_base = segj['baseaddr']
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seg_baseaddr = int(seg_baseaddr, 0)
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# Ensure that all frames exist for this segment
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# FIXME: type dependent
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for coli in range(segj['frames']):
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frame_init(seg_baseaddr + coli)
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# Now lets look up the bits we need frames for
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segdb = get_database(segj['type'])
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def clb2dbkey(tile, tilej, site, suffix, value):
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def slice_global2x01(tile_name, tile_type, site):
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# SLICE_X12Y102 => SLICEL_X0
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m = re.match(r'SLICE_X([0-9]+)Y[0-9]+', site)
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xg = int(m.group(1))
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prefix = {
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'CLBLL_L': {
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0: 'SLICEL',
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1: 'SLICEL'
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},
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'CLBLM_L': {
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0: 'SLICEM',
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1: 'SLICEL'
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},
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'CLBLL_R': {
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0: 'SLICEL',
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1: 'SLICEL'
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},
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'CLBLM_R': {
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0: 'SLICEM',
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1: 'SLICEL'
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},
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}
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x01 = xg % 2
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return '%s_X%d' % (prefix[tile_type][x01], x01)
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db_site = slice_global2x01(tile, tilej['type'], site)
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db_k = '%s.%s.%s' % (tilej['type'], db_site, suffix)
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return db_k
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def int2dbkey(tile, tilej, site, suffix, value):
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return '%s.%s.%s' % (tilej['type'], suffix, value)
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tile2dbkey = {
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'CLBLM_L': clb2dbkey,
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'CLBLM_R': clb2dbkey,
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'INT_L': int2dbkey,
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'INT_R': int2dbkey,
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'HCLK_L': int2dbkey,
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}
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f = tile2dbkey.get(tilej['type'], None)
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if f is None:
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raise Exception("Unhandled segment type %s" % tilej['type'])
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db_k = f(tile, tilej, site, suffix, value)
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try:
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db_vals = segdb[db_k]
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except KeyError:
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raise Exception(
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"Key %s (from line '%s') not found in segment DB %s" %
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(db_k, l, segj['type']))
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for val in db_vals:
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# Default is 0. Skip explicit call outs
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if val[0] == '!':
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continue
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# 28_05 => 28, 05
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seg_word_column, word_bit_n = val.split('_')
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seg_word_column, word_bit_n = int(seg_word_column), int(word_bit_n)
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# Now we have the word column and word bit index
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# Combine with the segments relative frame position to fully get the position
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frame_addr = seg_baseaddr + seg_word_column
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# 2 words per segment
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word_addr = seg_word_base + word_bit_n // 32
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bit_index = word_bit_n % 32
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frame_set(frame_addr, word_addr, bit_index)
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if debug:
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#dump_frames_verbose(frames)
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dump_frames_sparse(frames)
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dump_frm(f_out, frames)
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if __name__ == '__main__':
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import argparse
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parser = argparse.ArgumentParser(
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description=
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'Convert FPGA configuration description ("FPGA assembly") into binary frame equivalent'
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)
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parser.add_argument(
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'--sparse', action='store_true', help="Don't zero fill all frames")
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parser.add_argument(
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'--debug', action='store_true', help="Print debug dump")
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parser.add_argument('fn_in', help='Input FPGA assembly (.fasm) file')
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parser.add_argument('fn_out', help='Output FPGA frame (.frm) file')
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args = parser.parse_args()
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run(
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open(args.fn_in, 'r'),
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open(args.fn_out, 'w'),
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sparse=args.sparse,
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debug=args.debug)
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@ -0,0 +1,8 @@
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/.Xil
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/design/
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/design.bit
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/design.dcp
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/usage_statistics_webtalk.*
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/vivado*
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!design.bits
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@ -0,0 +1,24 @@
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bit_00020500_004_27
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bit_00020500_005_01
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bit_00020500_005_10
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bit_00020500_050_14
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bit_00020501_004_25
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bit_00020501_004_26
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bit_00020501_004_29
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bit_00020501_005_03
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bit_00020501_005_07
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bit_00020502_050_20
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bit_00020504_050_22
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bit_00020509_004_14
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bit_0002050f_004_14
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bit_00020511_004_15
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bit_00020512_004_06
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bit_00020514_005_00
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bit_00020516_004_15
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bit_00020518_004_07
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bit_00020518_004_15
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bit_00020519_004_15
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bit_00020519_005_00
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bit_0002051e_004_01
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bit_0002051e_004_12
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bit_0002051f_004_03
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@ -0,0 +1,39 @@
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module top(input clk, stb, di, output do);
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localparam integer DIN_N = 3;
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localparam integer DOUT_N = 1;
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reg [DIN_N-1:0] din;
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wire [DOUT_N-1:0] dout;
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reg [DIN_N-1:0] din_shr;
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reg [DOUT_N-1:0] dout_shr;
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always @(posedge clk) begin
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din_shr <= {din_shr, di};
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dout_shr <= {dout_shr, din_shr[DIN_N-1]};
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if (stb) begin
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din <= din_shr;
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dout_shr <= dout;
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end
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end
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assign do = dout_shr[DOUT_N-1];
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roi roi (
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.clk(clk),
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.din(din),
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.dout(dout)
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);
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endmodule
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module roi(input clk, input [2:0] din, output [0:0] dout);
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(* LOC="SLICE_X12Y102", BEL="AFF" *)
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FDCE ff (
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.C(clk),
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.Q(dout[0]),
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.CE(din[0]),
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.CLR(din[1]),
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.D(din[2])
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);
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endmodule
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@ -0,0 +1,8 @@
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/.Xil
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/design/
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/design.bit
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/design.dcp
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/usage_statistics_webtalk.*
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/vivado*
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!design.bits
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@ -0,0 +1,31 @@
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bit_0002050b_004_14
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bit_0002050c_004_14
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bit_00020511_004_17
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bit_00020511_004_26
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bit_00020511_005_01
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bit_00020512_004_03
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bit_00020512_004_08
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bit_00020512_005_24
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bit_00020517_004_02
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bit_00020517_004_26
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bit_00020518_004_02
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bit_00020518_004_09
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bit_00020518_004_17
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bit_00020518_004_26
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bit_00020518_005_01
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bit_00020518_005_25
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bit_00020519_004_02
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bit_00020519_004_26
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bit_00020520_004_04
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bit_00020520_004_05
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bit_00020520_004_12
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bit_00020520_004_14
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bit_00020520_004_15
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bit_00020521_004_00
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bit_00020521_004_04
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bit_00020521_004_06
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bit_00020521_004_07
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bit_00020521_004_12
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bit_00020521_004_13
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bit_00020521_004_14
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bit_00020522_004_15
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@ -0,0 +1,42 @@
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module top(input clk, stb, di, output do);
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localparam integer DIN_N = 6;
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localparam integer DOUT_N = 1;
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reg [DIN_N-1:0] din;
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wire [DOUT_N-1:0] dout;
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reg [DIN_N-1:0] din_shr;
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reg [DOUT_N-1:0] dout_shr;
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always @(posedge clk) begin
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din_shr <= {din_shr, di};
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dout_shr <= {dout_shr, din_shr[DIN_N-1]};
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if (stb) begin
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din <= din_shr;
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dout_shr <= dout;
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end
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end
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assign do = dout_shr[DOUT_N-1];
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roi roi (
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.clk(clk),
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.din(din),
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.dout(dout)
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);
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endmodule
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module roi(input clk, input [5:0] din, output [0:0] dout);
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(* LOC="SLICE_X12Y102", BEL="A6LUT", KEEP, DONT_TOUCH *)
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LUT6 #(
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.INIT(64'h8000_DEAD_0000_0001)
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) lutd (
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.I0(din[0]),
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.I1(din[1]),
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.I2(din[2]),
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.I3(din[3]),
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.I4(din[4]),
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.I5(din[5]),
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.O(dout[0]));
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endmodule
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@ -0,0 +1,24 @@
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# Loosely based on
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# segprint -zd test_data/clb_ff/design.bits
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# FF as LDCE
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CLBLM_L_X10Y102.SLICE_X12Y102.AFF.DMUX.AX 1
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CLBLM_L_X10Y102.SLICE_X12Y102.AFF.ZINI 1
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CLBLM_L_X10Y102.SLICE_X12Y102.AFF.ZRST 1
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CLBLM_L_X10Y102.SLICE_X12Y102.CEUSEDMUX 1
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CLBLM_L_X10Y102.SLICE_X12Y102.SRUSEDMUX 1
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# CLBLM_L_X10Y102.SLICE_X12Y102.FFSYNC 0
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# CLBLM_L_X10Y102.SLICE_X12Y102.LATCH 0
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# Note: a number of pseudo pips here
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# Omitted
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INT_L_X10Y102.CENTER_INTER_L.BYP_ALT0 EE2END0
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INT_L_X10Y102.CENTER_INTER_L.BYP_ALT1 EL1END1
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INT_L_X10Y102.CENTER_INTER_L.CLK_L1 GCLK_L_B11_WEST
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INT_L_X10Y102.CENTER_INTER_L.CTRL_L1 ER1END2
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INT_L_X10Y102.CENTER_INTER_L.FAN_ALT7 BYP_BOUNCE0
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INT_L_X10Y102.CENTER_INTER_L.WW2BEG0 LOGIC_OUTS_L4
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HCLK_L_X31Y130.HCLK_L.ENABLE_BUFFER HCLK_CK_BUFHCLK8
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HCLK_L_X31Y130.HCLK_L.HCLK_LEAF_CLK_B_BOTL5 HCLK_CK_BUFHCLK8
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@ -0,0 +1,15 @@
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# LUT
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CLBLM_L_X10Y102.SLICE_X12Y102.ALUT.INIT[00] 1
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CLBLM_L_X10Y102.SLICE_X12Y102.ALUT.INIT[08] 1
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CLBLM_L_X10Y102.SLICE_X12Y102.ALUT.INIT[10] 1
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CLBLM_L_X10Y102.SLICE_X12Y102.ALUT.INIT[11] 1
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CLBLM_L_X10Y102.SLICE_X12Y102.ALUT.INIT[13] 1
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CLBLM_L_X10Y102.SLICE_X12Y102.ALUT.INIT[14] 1
|
||||
CLBLM_L_X10Y102.SLICE_X12Y102.ALUT.INIT[15] 1
|
||||
CLBLM_L_X10Y102.SLICE_X12Y102.ALUT.INIT[41] 1
|
||||
CLBLM_L_X10Y102.SLICE_X12Y102.ALUT.INIT[43] 1
|
||||
CLBLM_L_X10Y102.SLICE_X12Y102.ALUT.INIT[44] 1
|
||||
CLBLM_L_X10Y102.SLICE_X12Y102.ALUT.INIT[46] 1
|
||||
CLBLM_L_X10Y102.SLICE_X12Y102.ALUT.INIT[47] 1
|
||||
CLBLM_L_X10Y102.SLICE_X12Y102.ALUT.INIT[63] 1
|
||||
|
||||
|
|
@ -0,0 +1,35 @@
|
|||
# Loosely based on
|
||||
# segprint -zd test_data/clb_lut/design.bits
|
||||
|
||||
# LUT
|
||||
CLBLM_L_X10Y102.SLICE_X12Y102.ALUT.INIT[00] 1
|
||||
CLBLM_L_X10Y102.SLICE_X12Y102.ALUT.INIT[08] 1
|
||||
CLBLM_L_X10Y102.SLICE_X12Y102.ALUT.INIT[10] 1
|
||||
CLBLM_L_X10Y102.SLICE_X12Y102.ALUT.INIT[11] 1
|
||||
CLBLM_L_X10Y102.SLICE_X12Y102.ALUT.INIT[13] 1
|
||||
CLBLM_L_X10Y102.SLICE_X12Y102.ALUT.INIT[14] 1
|
||||
CLBLM_L_X10Y102.SLICE_X12Y102.ALUT.INIT[15] 1
|
||||
CLBLM_L_X10Y102.SLICE_X12Y102.ALUT.INIT[41] 1
|
||||
CLBLM_L_X10Y102.SLICE_X12Y102.ALUT.INIT[43] 1
|
||||
CLBLM_L_X10Y102.SLICE_X12Y102.ALUT.INIT[44] 1
|
||||
CLBLM_L_X10Y102.SLICE_X12Y102.ALUT.INIT[46] 1
|
||||
CLBLM_L_X10Y102.SLICE_X12Y102.ALUT.INIT[47] 1
|
||||
CLBLM_L_X10Y102.SLICE_X12Y102.ALUT.INIT[63] 1
|
||||
|
||||
# din bus
|
||||
# din[0]
|
||||
INT_L_X10Y102.CENTER_INTER_L.IMUX_L1 EE2END0
|
||||
# din[1]
|
||||
INT_L_X10Y102.CENTER_INTER_L.IMUX_L2 EE2END1
|
||||
# din[2]
|
||||
INT_L_X10Y102.CENTER_INTER_L.IMUX_L4 EE2END2
|
||||
# din[3]
|
||||
INT_L_X10Y102.CENTER_INTER_L.IMUX_L7 EE2END3
|
||||
# din[4]
|
||||
INT_L_X10Y102.CENTER_INTER_L.IMUX_L8 EL1END0
|
||||
# din[5]
|
||||
INT_L_X10Y102.CENTER_INTER_L.IMUX_L11 EL1END1
|
||||
|
||||
# dout[0]
|
||||
INT_L_X10Y102.CENTER_INTER_L.WW2BEG0 LOGIC_OUTS_L12
|
||||
|
||||
|
|
@ -0,0 +1,101 @@
|
|||
import fasm2frame
|
||||
|
||||
import unittest
|
||||
import StringIO
|
||||
import re
|
||||
|
||||
|
||||
def frm2bits(txt):
|
||||
'''
|
||||
Convert output .frm file text to set of (frame addr, word #, bit index) tuples
|
||||
'''
|
||||
bits_out = set()
|
||||
for l in txt.split('\n'):
|
||||
l = l.strip()
|
||||
if not l:
|
||||
continue
|
||||
# 0x00020500 0x00000000,0x00000000,0x00000000,...
|
||||
addr, words = l.split(' ')
|
||||
addr = int(addr, 0)
|
||||
words = words.split(',')
|
||||
assert (101 == len(words))
|
||||
for wordi, word in enumerate(words):
|
||||
word = int(word, 0)
|
||||
for biti in xrange(32):
|
||||
val = word & (1 << biti)
|
||||
if val:
|
||||
bits_out.add((addr, wordi, biti))
|
||||
return bits_out
|
||||
|
||||
|
||||
def bitread2bits(txt):
|
||||
'''
|
||||
Convert .bits text file (ie bitread output) to set of (frame addr, word #, bit index) tuples
|
||||
'''
|
||||
bits_ref = set()
|
||||
for l in txt.split('\n'):
|
||||
l = l.strip()
|
||||
if not l:
|
||||
continue
|
||||
# bit_0002050b_004_14
|
||||
m = re.match(r'bit_(.{8})_(.{3})_(.{2})', l)
|
||||
addr = int(m.group(1), 16)
|
||||
word = int(m.group(2), 10)
|
||||
bit = int(m.group(3), 10)
|
||||
bits_ref.add((addr, word, bit))
|
||||
return bits_ref
|
||||
|
||||
|
||||
class TestStringMethods(unittest.TestCase):
|
||||
def test_lut(self):
|
||||
'''Simple smoke test on just the LUTs'''
|
||||
fout = StringIO.StringIO()
|
||||
fasm2frame.run(open('test_data/lut.fasm', 'r'), fout)
|
||||
|
||||
def bitread_frm_equals(self, frm_fn, bitread_fn):
|
||||
fout = StringIO.StringIO()
|
||||
fasm2frame.run(open(frm_fn, 'r'), fout)
|
||||
|
||||
# Build a list of output used bits
|
||||
bits_out = frm2bits(fout.getvalue())
|
||||
|
||||
# Build a list of reference used bits
|
||||
bits_ref = bitread2bits(open(bitread_fn, 'r').read())
|
||||
|
||||
# Now check for equivilence vs reference design
|
||||
self.assertEquals(len(bits_ref), len(bits_out))
|
||||
self.assertEquals(bits_ref, bits_out)
|
||||
|
||||
def test_lut_int(self):
|
||||
self.bitread_frm_equals(
|
||||
'test_data/lut_int.fasm', 'test_data/clb_lut/design.bits')
|
||||
|
||||
def test_ff_int(self):
|
||||
self.bitread_frm_equals(
|
||||
'test_data/ff_int.fasm', 'test_data/clb_ff/design.bits')
|
||||
|
||||
def test_sparse(self):
|
||||
'''Verify sparse equivilent to normal encoding'''
|
||||
frm_fn = 'test_data/lut_int.fasm'
|
||||
|
||||
fout_sparse = StringIO.StringIO()
|
||||
fasm2frame.run(open(frm_fn, 'r'), fout_sparse, sparse=True)
|
||||
fout_sparse_txt = fout_sparse.getvalue()
|
||||
bits_sparse = frm2bits(fout_sparse_txt)
|
||||
|
||||
fout_full = StringIO.StringIO()
|
||||
fasm2frame.run(open(frm_fn, 'r'), fout_full, sparse=False)
|
||||
fout_full_txt = fout_full.getvalue()
|
||||
bits_full = frm2bits(fout_full_txt)
|
||||
|
||||
# Now check for equivilence vs reference design
|
||||
self.assertEquals(len(bits_sparse), len(bits_full))
|
||||
self.assertEquals(bits_sparse, bits_full)
|
||||
|
||||
# Verify the full ROI is way bigger description
|
||||
# It will still be decent size though since even sparse occupies all columns in that area
|
||||
self.assertGreaterEqual(len(fout_full_txt), len(fout_sparse_txt) * 4)
|
||||
|
||||
|
||||
if __name__ == '__main__':
|
||||
unittest.main()
|
||||
Loading…
Reference in New Issue