luke
/
prjxray
mirror of https://github.com/openXC7/prjxray.git
1
0
Fork 0
Code Issues Packages Projects Releases Wiki Activity
prjxray/minitests/litex/uart_ddr/arty/src.yosys/mem_1.init

1 line
21 B
Plaintext
Raw Normal View History

Added UART DDR minitest Signed-off-by: Alessandro Comodi <acomodi@antmicro.com>
2020-02-03 12:30:42 +01:00
../verilog/mem_1.init