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prjxray/minitests/litex/uart_ddr/arty/src.yosys
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Alessandro Comodi f85e244ac6 Added UART DDR minitest 
Signed-off-by: Alessandro Comodi <acomodi@antmicro.com>
 		2020-02-03 12:41:40 +01:00
..
Makefile Added UART DDR minitest 2020-02-03 12:41:40 +01:00
mem.init Added UART DDR minitest 2020-02-03 12:41:40 +01:00
mem_1.init Added UART DDR minitest 2020-02-03 12:41:40 +01:00
missing_bit_report.py Added UART DDR minitest 2020-02-03 12:41:40 +01:00
synth.ys Added UART DDR minitest 2020-02-03 12:41:40 +01:00
top.tcl Added UART DDR minitest 2020-02-03 12:41:40 +01:00
top.xdc Added UART DDR minitest 2020-02-03 12:41:40 +01:00