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prjxray/minitests/litex/src.yosys/synth.ys

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Added LiteX SoC project (VexRiscV + DRAM + Ethernet for Arty board) Signed-off-by: Maciej Kurc <mkurc@antmicro.com>
2019-06-13 15:58:06 +02:00
read_verilog top.v
Fixed the LiteX generated SoC to be Linux capable Signed-off-by: Maciej Kurc <mkurc@antmicro.com>
2019-06-17 13:45:11 +02:00
read_verilog VexRiscv_Linux.v
Added LiteX SoC project (VexRiscV + DRAM + Ethernet for Arty board) Signed-off-by: Maciej Kurc <mkurc@antmicro.com>
2019-06-13 15:58:06 +02:00
synth_xilinx -edif top.edif