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prjxray-db
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Updating DB based on "Merge pull request #229 from mcmasterg/k7_bits". 

See [Info File](Info.md) for details.

Signed-off-by: Tim 'mithro' Ansell <me@mith.ro>
This commit is contained in:
Tim 'mithro' Ansell 2018-11-12 02:59:36 +00:00
parent 6f02e2fa4b
commit 51bd5eac70
201 changed files with 1123390 additions and 23741 deletions
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251
Info.md
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@ -37,37 +37,39 @@ These files are released under the very permissive [CC0 1.0 Universal](COPYING).
# Details
Last updated on Thu Oct 25 23:18:25 UTC 2018 (2018-10-25T23:18:25+00:00).
Last updated on Mon Nov 12 02:59:35 UTC 2018 (2018-11-12T02:59:35+00:00).
Created using [Project X-Ray](https://github.com/SymbiFlow/prjxray) version [v0.0-903-ga0cfca8](https://github.com/SymbiFlow/prjxray/commit/a0cfca860872a99ac81b223ee1e5e9ae567b9590).
Created using [Project X-Ray](https://github.com/SymbiFlow/prjxray) version [v0.0-984-gb43bf35](https://github.com/SymbiFlow/prjxray/commit/b43bf3539f51ed8a755ae245682cd660ca23d813).
Latest commit was;
```
commit a0cfca860872a99ac81b223ee1e5e9ae567b9590
Merge: d33fdb7 3247963
commit b43bf3539f51ed8a755ae245682cd660ca23d813
Merge: b5d691c e2e236e
Author: Tim Ansell <me@mith.ro>
Date: Wed Oct 24 17:00:19 2018 -0700
Date: Tue Nov 6 15:11:29 2018 -0800
Merge pull request #191 from mithro/master
Merge pull request #229 from mcmasterg/k7_bits
minitests/roi_harness: Add XRAY_PIN values valid for Arty.
k7: use all bitstream bits, format settings.sh alike
```
## Database for [artix7](artix7/)
### Settings
Created using following [settings.sh (sha256: cb777c1e854d877556482ff2067eff348386ce627caa0ef5617a6e5dea01dc6a)](https://github.com/SymbiFlow/prjxray/blob/a0cfca860872a99ac81b223ee1e5e9ae567b9590/database/artix7/settings.sh)
Created using following [settings.sh (sha256: d77b40f729b66962f0197a5e31b43860326401b6116ac36e727411319adac0f2)](https://github.com/SymbiFlow/prjxray/blob/b43bf3539f51ed8a755ae245682cd660ca23d813/database/artix7/settings.sh)
```shell
export XRAY_DATABASE="artix7"
export XRAY_PART="xc7a50tfgg484-1"
export XRAY_ROI="SLICE_X12Y100:SLICE_X27Y149"
export XRAY_ROI_FRAMES="0x00000000:0xffffffff"
# Leave some CLBs to the left to allow easy ROI entering
export XRAY_ROI="SLICE_X8Y100:SLICE_X27Y149 RAMB18_X0Y40:RAMB18_X0Y59 RAMB36_X0Y20:RAMB36_X0Y29 DSP48_X0Y40:DSP48_X0Y59"
export XRAY_ROI_GRID_X1="18"
export XRAY_ROI_GRID_X2="47"
# All CLB's in part, all BRAM's in part, all DSP's in part.
export XRAY_ROI="SLICE_X0Y0:SLICE_X65Y99 SLICE_X0Y100:SLICE_X57Y149 RAMB18_X0Y0:RAMB18_X1Y59 RAMB36_X0Y0:RAMB36_X1Y29 RAMB18_X2Y0:RAMB18_X2Y39 RAMB36_X2Y0:RAMB36_X2Y19 DSP48_X0Y0:DSP48_X1Y59"
# Most of CMT X0Y2.
export XRAY_ROI_GRID_X1="9"
export XRAY_ROI_GRID_X2="58"
# Include VBRK / VTERM
export XRAY_ROI_GRID_Y1="0"
export XRAY_ROI_GRID_Y2="52"
@ -127,7 +129,7 @@ Results have checksums;
* [`5e22f758a04eab3185b2453c9994aa2fa48f50ca8a6b49bf82e8fc4351f23a5c ./artix7/segbits_hclk_r.db`](./artix7/segbits_hclk_r.db)
* [`08dee581e565abbd09db559f9226139ba5a253f8aec4f3492152d8df8a87bbab ./artix7/segbits_int_l.db`](./artix7/segbits_int_l.db)
* [`13bc58bf4a42029adf4f9b06ffd7c9436e2294bf4fdc16cdaa70505c28a2a7b7 ./artix7/segbits_int_r.db`](./artix7/segbits_int_r.db)
* [`cb777c1e854d877556482ff2067eff348386ce627caa0ef5617a6e5dea01dc6a ./artix7/settings.sh`](./artix7/settings.sh)
* [`d77b40f729b66962f0197a5e31b43860326401b6116ac36e727411319adac0f2 ./artix7/settings.sh`](./artix7/settings.sh)
* [`3f6ab41214df9776a9cd8ea63cca60adab925abf08a3204549fa956ef87270de ./artix7/site_type_BSCAN.json`](./artix7/site_type_BSCAN.json)
* [`b1e326e9c93fa1d239423b681aa22a1f999994280a6ef94626eafeb855d93571 ./artix7/site_type_BUFGCTRL.json`](./artix7/site_type_BUFGCTRL.json)
* [`04a2cffb41ec815914fc361cb527df69cb36e4db74f25de6792c59f6ce97f6d3 ./artix7/site_type_BUFHCE.json`](./artix7/site_type_BUFHCE.json)
@ -294,16 +296,21 @@ Results have checksums;
### Settings
Created using following [settings.sh (sha256: 2daf6a69dd6d20df7b1273ff43c5c340abe36f8229d297646865edcfd91eff18)](https://github.com/SymbiFlow/prjxray/blob/a0cfca860872a99ac81b223ee1e5e9ae567b9590/database/kintex7/settings.sh)
Created using following [settings.sh (sha256: 555d484e8c10c35897ac446eb7a1bbebf0606c56dcd19caa9c8d916bb77cad64)](https://github.com/SymbiFlow/prjxray/blob/b43bf3539f51ed8a755ae245682cd660ca23d813/database/kintex7/settings.sh)
```shell
export XRAY_DATABASE="kintex7"
export XRAY_PART="xc7k70tfbg676-2"
export XRAY_ROI_FRAMES="0x00000000:0xffffffff"
export XRAY_ROI="SLICE_X0Y50:SLICE_X19Y99 DSP48_X0Y20:DSP48_X0Y39 RAMB18_X0Y20:RAMB18_X0Y39 RAMB36_X0Y10:RAMB36_X0Y19"
export XRAY_ROI_FRAMES="0x00400100:0x004006ff"
# Part of CMT X0Y1
export XRAY_ROI_GRID_X1="9"
export XRAY_ROI_GRID_X2="38"
# Include VBRK / VTERM
export XRAY_ROI_GRID_Y1="104"
export XRAY_ROI_GRID_Y2="156"
# Choose the first N High Range I/Os
export XRAY_PIN_00="K25"
export XRAY_PIN_01="K26"
@ -320,6 +327,7 @@ source $(dirname ${BASH_SOURCE[0]})/../../utils/environment.sh
Results have checksums;
* [`d154b5fc62e0ae17091b880050a7302f4f75fed1008967eb88e2c1e3f13f4792 ./kintex7/element_counts.csv`](./kintex7/element_counts.csv)
* [`6f6dd0ba33fdd78d87f8591adbff5aad2d3653a1b1fa03d77079ce64a7c1f175 ./kintex7/mask_bram0_l.db`](./kintex7/mask_bram0_l.db)
* [`9d12bc3be758587479874bff531ad702f429a963518d7bc5b2b3c0400ded4c6a ./kintex7/mask_bram0_r.db`](./kintex7/mask_bram0_r.db)
* [`6f6dd0ba33fdd78d87f8591adbff5aad2d3653a1b1fa03d77079ce64a7c1f175 ./kintex7/mask_bram1_l.db`](./kintex7/mask_bram1_l.db)
@ -330,10 +338,12 @@ Results have checksums;
* [`9d12bc3be758587479874bff531ad702f429a963518d7bc5b2b3c0400ded4c6a ./kintex7/mask_bram3_r.db`](./kintex7/mask_bram3_r.db)
* [`6f6dd0ba33fdd78d87f8591adbff5aad2d3653a1b1fa03d77079ce64a7c1f175 ./kintex7/mask_bram4_l.db`](./kintex7/mask_bram4_l.db)
* [`9d12bc3be758587479874bff531ad702f429a963518d7bc5b2b3c0400ded4c6a ./kintex7/mask_bram4_r.db`](./kintex7/mask_bram4_r.db)
* [`03fe7af3125c25f3d84bd8e874525c83275a6c3b6736d0b01134b5f982721f5b ./kintex7/mask_clbll_l.db`](./kintex7/mask_clbll_l.db)
* [`be34841c9aa64527e5f84d1819abbac1d324047367003b6fdc1402cd695481de ./kintex7/mask_clbll_r.db`](./kintex7/mask_clbll_r.db)
* [`fec2e4a94efd8b4e9d29d52689d406482f842e6f718ab671131b5e9ac2e0805b ./kintex7/mask_clblm_l.db`](./kintex7/mask_clblm_l.db)
* [`7b68fbcb19382d54bdc57971dd7eb9b0cbb4318f9b6053b301f3384f7ee4bb75 ./kintex7/mask_clblm_r.db`](./kintex7/mask_clblm_r.db)
* [`5d8e00a868cba3369bf2d5696d6871695967cb2a42f6464cb366dcef5d7d48e7 ./kintex7/mask_bram_l.db`](./kintex7/mask_bram_l.db)
* [`5d8e00a868cba3369bf2d5696d6871695967cb2a42f6464cb366dcef5d7d48e7 ./kintex7/mask_bram_r.db`](./kintex7/mask_bram_r.db)
* [`5c274320294201935a3edccb43eca8e347ca1f0acded71ec388c794877d4b55b ./kintex7/mask_clbll_l.db`](./kintex7/mask_clbll_l.db)
* [`5c274320294201935a3edccb43eca8e347ca1f0acded71ec388c794877d4b55b ./kintex7/mask_clbll_r.db`](./kintex7/mask_clbll_r.db)
* [`5c274320294201935a3edccb43eca8e347ca1f0acded71ec388c794877d4b55b ./kintex7/mask_clblm_l.db`](./kintex7/mask_clblm_l.db)
* [`5c274320294201935a3edccb43eca8e347ca1f0acded71ec388c794877d4b55b ./kintex7/mask_clblm_r.db`](./kintex7/mask_clblm_r.db)
* [`6f6dd0ba33fdd78d87f8591adbff5aad2d3653a1b1fa03d77079ce64a7c1f175 ./kintex7/mask_dsp0_l.db`](./kintex7/mask_dsp0_l.db)
* [`9d12bc3be758587479874bff531ad702f429a963518d7bc5b2b3c0400ded4c6a ./kintex7/mask_dsp0_r.db`](./kintex7/mask_dsp0_r.db)
* [`6f6dd0ba33fdd78d87f8591adbff5aad2d3653a1b1fa03d77079ce64a7c1f175 ./kintex7/mask_dsp1_l.db`](./kintex7/mask_dsp1_l.db)
@ -344,13 +354,196 @@ Results have checksums;
* [`9d12bc3be758587479874bff531ad702f429a963518d7bc5b2b3c0400ded4c6a ./kintex7/mask_dsp3_r.db`](./kintex7/mask_dsp3_r.db)
* [`6f6dd0ba33fdd78d87f8591adbff5aad2d3653a1b1fa03d77079ce64a7c1f175 ./kintex7/mask_dsp4_l.db`](./kintex7/mask_dsp4_l.db)
* [`9d12bc3be758587479874bff531ad702f429a963518d7bc5b2b3c0400ded4c6a ./kintex7/mask_dsp4_r.db`](./kintex7/mask_dsp4_r.db)
* [`3e3b19a2d49a1d0f25937bc5d0b33f0269c22c5e8ae3cfe52e4ff5c65843b134 ./kintex7/segbits_clbll_l.db`](./kintex7/segbits_clbll_l.db)
* [`fdb5499b9e2aa9d1796332279f0b5dc881a5ad0796698e8ef3af40ddc98df26b ./kintex7/segbits_clbll_r.db`](./kintex7/segbits_clbll_r.db)
* [`0b79670cc5a03b7580f73dc162a8bad048ade2f50971622138e0d0a5759899b6 ./kintex7/segbits_clblm_l.db`](./kintex7/segbits_clblm_l.db)
* [`e7f5d16940fde9397f69d5f52c2a6339641191dc9dba4466e8b7f9e5f6a735bf ./kintex7/segbits_clblm_r.db`](./kintex7/segbits_clblm_r.db)
* [`9ed8769618df03902c73e78312467108c7b74b903ac61d1bbbba1fd9710e6d3b ./kintex7/segbits_int_l.db`](./kintex7/segbits_int_l.db)
* [`dbf6cba5bbba95d7d78d9b51d236d8819dc776c2ebc540521e5b48d3a2c1390f ./kintex7/segbits_int_r.db`](./kintex7/segbits_int_r.db)
* [`2daf6a69dd6d20df7b1273ff43c5c340abe36f8229d297646865edcfd91eff18 ./kintex7/settings.sh`](./kintex7/settings.sh)
* [`8f5b7a7924adec5132208cf8e851e81bcb01a5c61f8839eb5a5de0b20b924510 ./kintex7/tilegrid.json`](./kintex7/tilegrid.json)
* [`68426295ab4a35e367c9dff93e4f9b807afd43fe83418cb2da7465cd4d7177a2 ./kintex7/xc7k70tfbg676-2.yaml`](./kintex7/xc7k70tfbg676-2.yaml)
* [`76a9286b89fa91babd4ab8b59156b12a7024130d66f9f08da290797d00a115e6 ./kintex7/mask_dsp_l.db`](./kintex7/mask_dsp_l.db)
* [`76a9286b89fa91babd4ab8b59156b12a7024130d66f9f08da290797d00a115e6 ./kintex7/mask_dsp_r.db`](./kintex7/mask_dsp_r.db)
* [`76d1e0bd4b7ad492cf3fe8698b2b5f46f7dcc5fe446984e5dccae373c63edafd ./kintex7/mask_hclk_l.db`](./kintex7/mask_hclk_l.db)
* [`76d1e0bd4b7ad492cf3fe8698b2b5f46f7dcc5fe446984e5dccae373c63edafd ./kintex7/mask_hclk_r.db`](./kintex7/mask_hclk_r.db)
* [`6baea72435613b87334f95cfe2b1ab36da4d57ada20b71a7dd870715b3e430c4 ./kintex7/ppips_clbll_l.db`](./kintex7/ppips_clbll_l.db)
* [`3955d590e8ee64c843bb80f911a08781c1bac63e71b577436ae1f44195a88e22 ./kintex7/ppips_clbll_r.db`](./kintex7/ppips_clbll_r.db)
* [`29f175153821dc13989eb580676ff0007e108d911275a74e7ebe45e819c14eaf ./kintex7/ppips_clblm_l.db`](./kintex7/ppips_clblm_l.db)
* [`52b53ae735d40632403283ab720db2172794a22c5245b3da7693b264d69a122d ./kintex7/ppips_clblm_r.db`](./kintex7/ppips_clblm_r.db)
* [`6d35b568a51f9b6761da2470a71738b2477ef72c16068a529ae8eb52b65bf17a ./kintex7/ppips_hclk_l.db`](./kintex7/ppips_hclk_l.db)
* [`81e0696179a33bdf8d2279a53b406911a403d50224355e9ad29eccee01a70305 ./kintex7/ppips_hclk_r.db`](./kintex7/ppips_hclk_r.db)
* [`be617c15d1ec311b6249791414bbd69380fe90b476353cbb2fc2a7cb06f5029d ./kintex7/ppips_int_l.db`](./kintex7/ppips_int_l.db)
* [`a1423859c97a82dcfb114644f50b991db4ca7e0996e6d1ae4d2c97bfdfcb723d ./kintex7/ppips_int_r.db`](./kintex7/ppips_int_r.db)
* [`e3b0c44298fc1c149afbf4c8996fb92427ae41e4649b934ca495991b7852b855 ./kintex7/segbits_bram_l.block_ram.db`](./kintex7/segbits_bram_l.block_ram.db)
* [`b3011b6a49b05f1f0a40b499537d0f3eb208a51b87d6d97811911df50d4ad2d2 ./kintex7/segbits_bram_l.db`](./kintex7/segbits_bram_l.db)
* [`e3b0c44298fc1c149afbf4c8996fb92427ae41e4649b934ca495991b7852b855 ./kintex7/segbits_bram_r.block_ram.db`](./kintex7/segbits_bram_r.block_ram.db)
* [`ac4e1c029ed8e623985ca2665e7aa1fae57aa2b33defb5f8cfa17d34d160e4b1 ./kintex7/segbits_bram_r.db`](./kintex7/segbits_bram_r.db)
* [`7591abf4d35e031e0d35cb8fdfe77c2b7d0f2840625c105977108e08451857f4 ./kintex7/segbits_clbll_l.db`](./kintex7/segbits_clbll_l.db)
* [`9a23ca5a568841b282c0207ed4cfe70925b0d5c4bbf232e5ee5697123082078c ./kintex7/segbits_clbll_r.db`](./kintex7/segbits_clbll_r.db)
* [`10f499474dc8b6c4b051291d70aedadfb9902219079553eefbbc64dabfd78a06 ./kintex7/segbits_clblm_l.db`](./kintex7/segbits_clblm_l.db)
* [`4c3a3a92b4bb860098596ce8d4a6fd869aff59705dc5d5049ce97ee70f6d39ac ./kintex7/segbits_clblm_r.db`](./kintex7/segbits_clblm_r.db)
* [`df496c4d335fac0c379497ff0a75ba4f5c5c25bcce79f9c7a72d5f08066310db ./kintex7/segbits_hclk_l.db`](./kintex7/segbits_hclk_l.db)
* [`5e22f758a04eab3185b2453c9994aa2fa48f50ca8a6b49bf82e8fc4351f23a5c ./kintex7/segbits_hclk_r.db`](./kintex7/segbits_hclk_r.db)
* [`51b25643ef3b8a7a90181ad61199cd70ac8c5baa18ee1aacd2e81ff50ccdbfcf ./kintex7/segbits_int_l.db`](./kintex7/segbits_int_l.db)
* [`05d1165f911881b3600b01f86cad9a6618c8b0dadb7014def3145f9254fd0c45 ./kintex7/segbits_int_r.db`](./kintex7/segbits_int_r.db)
* [`555d484e8c10c35897ac446eb7a1bbebf0606c56dcd19caa9c8d916bb77cad64 ./kintex7/settings.sh`](./kintex7/settings.sh)
* [`3d3390a265afd578bb096a995b3cd820b910712e6392d8abf6c4d90ba77cf3bd ./kintex7/site_type_BSCAN.json`](./kintex7/site_type_BSCAN.json)
* [`b4fd720cdfda56436ae275c9b96eac3b02d1eb46cc7ed67bcdbe02a22288f96a ./kintex7/site_type_BUFGCTRL.json`](./kintex7/site_type_BUFGCTRL.json)
* [`de586b421d77a904b9814921ad04b9dd37bf55dccbcb457d2cd5b7bd2059e408 ./kintex7/site_type_BUFHCE.json`](./kintex7/site_type_BUFHCE.json)
* [`b8fba943d1daba4bf68b60662ecd54d15d2e420844b3c365fccbbf540397e04f ./kintex7/site_type_BUFIO.json`](./kintex7/site_type_BUFIO.json)
* [`12f445c57c357a516bee5821b4432afa3428cc2435485fe4760d9f9d71df01da ./kintex7/site_type_BUFMRCE.json`](./kintex7/site_type_BUFMRCE.json)
* [`7f74df4f448f0688ff77300ca3a78f43d850876f50974dd99fa3e4b2b9eb93c4 ./kintex7/site_type_BUFR.json`](./kintex7/site_type_BUFR.json)
* [`918f7d1fa92e0781305ce37ec4a4803efbb19472b165b7a56fa78f254f5df8dc ./kintex7/site_type_CAPTURE.json`](./kintex7/site_type_CAPTURE.json)
* [`74c501f8de850d82eb3f3c9b1e50dfb0c29ead2449b03d85378bef0483219e0f ./kintex7/site_type_DCIRESET.json`](./kintex7/site_type_DCIRESET.json)
* [`e7e73464183458595a02afa7da58537dffd3dcd098c0e96dcce7ec197ac8afa7 ./kintex7/site_type_DNA_PORT.json`](./kintex7/site_type_DNA_PORT.json)
* [`0f696a78a57fab8995671dba639ac73d61013f4ec7aa65239662362be50a06ae ./kintex7/site_type_DSP48E1.json`](./kintex7/site_type_DSP48E1.json)
* [`ad1f2dc2bc5629fdc3a4308b045d103d76f38612d04c9dc8bde50339575d8d40 ./kintex7/site_type_EFUSE_USR.json`](./kintex7/site_type_EFUSE_USR.json)
* [`ae4b06dee05c810b85a6385d605d4bbf65ac169161b6fc3fe0199eb7737169a2 ./kintex7/site_type_FIFO18E1.json`](./kintex7/site_type_FIFO18E1.json)
* [`653cd09ce90f58d1e2be7ecc5522f058b30a7ec2b95ed549cf5f053d982a4ef7 ./kintex7/site_type_FRAME_ECC.json`](./kintex7/site_type_FRAME_ECC.json)
* [`16b0e88823f0490f8faa0f20cd175e06de645daf15397754c747570626f7737d ./kintex7/site_type_GTXE2_CHANNEL.json`](./kintex7/site_type_GTXE2_CHANNEL.json)
* [`e95bb4dcf5840cb482468f1a7d7160e1905a93c7f56a4d07891a671d250986b1 ./kintex7/site_type_GTXE2_COMMON.json`](./kintex7/site_type_GTXE2_COMMON.json)
* [`334f26f9d610cf1527cd3debabb454ce0db96130bf263a3efbe7ffddbcc5872c ./kintex7/site_type_IBUFDS_GTE2.json`](./kintex7/site_type_IBUFDS_GTE2.json)
* [`de547e93791ca92f8679a8a7d606505ceaa04436f82bdac851035d1836c60f59 ./kintex7/site_type_ICAP.json`](./kintex7/site_type_ICAP.json)
* [`a50c2bc260b5359aa96658a7191fa85212b12363b68cfcb6a75230392b35eefb ./kintex7/site_type_IDELAYCTRL.json`](./kintex7/site_type_IDELAYCTRL.json)
* [`ac42f477f213fc05f118b8f24c51ed01cbcf1c4dfd7ef3fe71ea3415cc4eb98d ./kintex7/site_type_IDELAYE2_FINEDELAY.json`](./kintex7/site_type_IDELAYE2_FINEDELAY.json)
* [`4eafb55d1b61747fd9ef8196454bb0a5df9d0784aeaef7a8e6da67dc1e51668e ./kintex7/site_type_IDELAYE2.json`](./kintex7/site_type_IDELAYE2.json)
* [`b572d4069bb6289d79baa673237a86a5e7d28b0efc6122e9505e31476144ca5d ./kintex7/site_type_ILOGICE2.json`](./kintex7/site_type_ILOGICE2.json)
* [`97cce70ba181e41b8a0ca9076b470ce49dfefae95f588837d73686f82d4305c8 ./kintex7/site_type_ILOGICE3.json`](./kintex7/site_type_ILOGICE3.json)
* [`dbd9354873d1673301b9779a04c23db947c325280fdefc05fec5fec974d25e69 ./kintex7/site_type_IN_FIFO.json`](./kintex7/site_type_IN_FIFO.json)
* [`9cd9d19d9805453ff7319c84f7e092e7af999c054cf11eb4f4839015b599dbee ./kintex7/site_type_IOB18.json`](./kintex7/site_type_IOB18.json)
* [`126b44af8a35bf0fc2a981bd240169a4ce12371f4db48d71bfafd2fb714a54f5 ./kintex7/site_type_IOB18M.json`](./kintex7/site_type_IOB18M.json)
* [`6f850e2eb9ff74e61dc8ee43296ffbba1e195951bba7ab9b195c72bc0c765f20 ./kintex7/site_type_IOB18S.json`](./kintex7/site_type_IOB18S.json)
* [`8d88647b1059737d103ec85b97fc2ea4c1acf871c20feacc7df9e3074ed0e54b ./kintex7/site_type_IOB33.json`](./kintex7/site_type_IOB33.json)
* [`d4ad99dabcca0c2040f348634e8758f9335f4e4b3f97ff7c53d67a929a5252be ./kintex7/site_type_IOB33M.json`](./kintex7/site_type_IOB33M.json)
* [`f875e1ba42bb51dd6ae044223e196c763bd19bfcec40384343a4b6bee5b7cd4f ./kintex7/site_type_IOB33S.json`](./kintex7/site_type_IOB33S.json)
* [`6922af5e94c020bf330e088a74c09ad7be09b4264756154dea5769d5631e22bf ./kintex7/site_type_IPAD.json`](./kintex7/site_type_IPAD.json)
* [`c6536a1020e7164cd3e596c01526c5e3365a73cdfd9c1a6f2cf3616544eced1d ./kintex7/site_type_MMCME2_ADV.json`](./kintex7/site_type_MMCME2_ADV.json)
* [`437ef6ec381eb246a9df43bf6e2e7232a4246bbf87deab3980910b627221e17d ./kintex7/site_type_ODELAYE2.json`](./kintex7/site_type_ODELAYE2.json)
* [`b51e1d6cf2e8874843e19afbddda3c8ba4dac5801890c389cb21b474c4c3b19d ./kintex7/site_type_OLOGICE2.json`](./kintex7/site_type_OLOGICE2.json)
* [`1567aa8832b40e8706ce45da566f681a101ea3ca581a308f0fc0cea40f8e9c20 ./kintex7/site_type_OLOGICE3.json`](./kintex7/site_type_OLOGICE3.json)
* [`26a864898c5fccc0713e6c50cc1d979b85c7f80ef283ad7f4bebc390b272a0a0 ./kintex7/site_type_OPAD.json`](./kintex7/site_type_OPAD.json)
* [`83dd093773549002cf7a1c7b0f4a1aa9309006f4954d5d44986aa9a4c0dd070a ./kintex7/site_type_OUT_FIFO.json`](./kintex7/site_type_OUT_FIFO.json)
* [`a1e6a8c61bd25f4022d8fcd7516d3d81cdde6985b32fd82104f007460cff04f9 ./kintex7/site_type_PCIE_2_1.json`](./kintex7/site_type_PCIE_2_1.json)
* [`aff4c1cecba401965587250c873f7c2a144b6472416ac4623b34dbce6b393aa0 ./kintex7/site_type_PHASER_IN_PHY.json`](./kintex7/site_type_PHASER_IN_PHY.json)
* [`1b18d9c78eb215d6e93c994128c1522fd4227c339f000fa3207e02f2a9a78137 ./kintex7/site_type_PHASER_OUT_PHY.json`](./kintex7/site_type_PHASER_OUT_PHY.json)
* [`3c74a6c5775b46fedb0f870bd9cfacdba57fe7699d4784e9e485425030675dbf ./kintex7/site_type_PHASER_REF.json`](./kintex7/site_type_PHASER_REF.json)
* [`397270675c85b40f5b749c6939fe6209005b6201a26434c743f294ef25d5ca98 ./kintex7/site_type_PHY_CONTROL.json`](./kintex7/site_type_PHY_CONTROL.json)
* [`be572d2892f943ab8a69d03924da674b0f64bf61ad69ff7968242743609e21f3 ./kintex7/site_type_PLLE2_ADV.json`](./kintex7/site_type_PLLE2_ADV.json)
* [`cabec9a6d1e017ff751a80c2ec10d0b0b76ef014d1ba73f6ea6793e3ec2ff2dc ./kintex7/site_type_PMV2.json`](./kintex7/site_type_PMV2.json)
* [`1a869b379e657531322f061b568950595a8fb6030c32f5fea82bfdc19df50120 ./kintex7/site_type_RAMB18E1.json`](./kintex7/site_type_RAMB18E1.json)
* [`a9c86c49d3287782468a28f710fa1334fe2c5a69bb8b20cc804caf112e703148 ./kintex7/site_type_RAMBFIFO36E1.json`](./kintex7/site_type_RAMBFIFO36E1.json)
* [`51804af3230d43c989f909b2a305c67e1c7cc8bafefda5d912864e1fb74a4d14 ./kintex7/site_type_SLICEL.json`](./kintex7/site_type_SLICEL.json)
* [`1ad52d9cf41a20610535e24cd352b7c9cd85e33dd3d0f57580ab56063eb184a5 ./kintex7/site_type_SLICEM.json`](./kintex7/site_type_SLICEM.json)
* [`ba727d2d69816bcace78fd39fd3431ff2a4d89ef94c5401380b475bd49f11ca5 ./kintex7/site_type_STARTUP.json`](./kintex7/site_type_STARTUP.json)
* [`7329766c3d005888d7c26e2971eede01b5868561ebf3a2fd79418ede9b8eea7e ./kintex7/site_type_TIEOFF.json`](./kintex7/site_type_TIEOFF.json)
* [`8630a9324f0e03108cde9c677bd86d0bde54576467691b225e0428948b44d526 ./kintex7/site_type_USR_ACCESS.json`](./kintex7/site_type_USR_ACCESS.json)
* [`dfcdd7535d3da5d3e3fd5ab6487490eacbb697d28058d9a59d6d053b56a348f4 ./kintex7/site_type_XADC.json`](./kintex7/site_type_XADC.json)
* [`fcc005f080da4cebe34427d6ffdab475fa1e994e06ae865cada7556a33a5caa5 ./kintex7/tileconn.json`](./kintex7/tileconn.json)
* [`2ccb101556ecee8ad729fbdd2dcbca296beb0cddc1755f649de3255cbaa51b2f ./kintex7/tilegrid.json`](./kintex7/tilegrid.json)
* [`e41553a434c96945d188d8f4c9479b2c8cdcc266aecedcaec808ce3313a90838 ./kintex7/tile_type_BRAM_INT_INTERFACE_L.json`](./kintex7/tile_type_BRAM_INT_INTERFACE_L.json)
* [`bcdc2360681535c7bd1059bc7589563ee13658a0054e6e7bdc9e2c666f32c161 ./kintex7/tile_type_BRAM_INT_INTERFACE_R.json`](./kintex7/tile_type_BRAM_INT_INTERFACE_R.json)
* [`c02f17fd75d3f9c51cdee987c564623ec7a260a4189b5762fb8ce52ac37403a8 ./kintex7/tile_type_BRAM_L.json`](./kintex7/tile_type_BRAM_L.json)
* [`4860e2e56b17e157efdd9a05e8dd8929bb4b302ba610754d6749eb57cd9707d7 ./kintex7/tile_type_BRAM_R.json`](./kintex7/tile_type_BRAM_R.json)
* [`a2c7168fac50a80ba1ffd64533b079b2f6c7cf3ebfa506f7dd28c42ad102e605 ./kintex7/tile_type_BRKH_BRAM.json`](./kintex7/tile_type_BRKH_BRAM.json)
* [`3147439b966fd3ca65030a80e8cd78de68bfb8493db6adcaddda0dd195edc1d8 ./kintex7/tile_type_BRKH_B_TERM_INT.json`](./kintex7/tile_type_BRKH_B_TERM_INT.json)
* [`21f2bf31f07964e8f4d8878ff6ad90f7c956f91c1ffdfa3775f46935e907676e ./kintex7/tile_type_BRKH_CLB.json`](./kintex7/tile_type_BRKH_CLB.json)
* [`d1c4672ad9c1bcff94d597847751abb6fbac92584c22598abc08ac7c7af8021b ./kintex7/tile_type_BRKH_CLK.json`](./kintex7/tile_type_BRKH_CLK.json)
* [`5578b9e473da648aea8413aee1003f0472dd2826327eb65ec42848ed96735ecc ./kintex7/tile_type_BRKH_CMT.json`](./kintex7/tile_type_BRKH_CMT.json)
* [`ea3e20731602dc5096ca43000f46ec5ecfa01aa91d166b2c6503b37530b06ac5 ./kintex7/tile_type_BRKH_DSP_L.json`](./kintex7/tile_type_BRKH_DSP_L.json)
* [`8e4dd08bb2ca3fce962e6b34a2133f122a96e5e1ae16c2d969c2078c049687b5 ./kintex7/tile_type_BRKH_DSP_R.json`](./kintex7/tile_type_BRKH_DSP_R.json)
* [`4914b83cd7fb2ff11eeaa679fbafcfcc59b5e089e02890b9d99cf703c719a820 ./kintex7/tile_type_BRKH_GTX.json`](./kintex7/tile_type_BRKH_GTX.json)
* [`5fe2c1814b8fac0bc28f32205ea620dff25be4dd9754122a0185d1395b354c5f ./kintex7/tile_type_BRKH_INT.json`](./kintex7/tile_type_BRKH_INT.json)
* [`3d438a6e8f9a7abaf7ec414d67f786fb9b1fa58cdc91649bef84688c00df85c1 ./kintex7/tile_type_BRKH_TERM_INT.json`](./kintex7/tile_type_BRKH_TERM_INT.json)
* [`9ea642a0684cc8102c865e7d6c486a888c88e102dc873f13e7f6d46d47e00047 ./kintex7/tile_type_B_TERM_INT.json`](./kintex7/tile_type_B_TERM_INT.json)
* [`0000c209ed73d7f807258ae042ff63c39c259b1239675d19454b3b000ea71ac2 ./kintex7/tile_type_CFG_CENTER_BOT.json`](./kintex7/tile_type_CFG_CENTER_BOT.json)
* [`32b33effc6925a1af80e119159f536dd768bdea60336fcad5a8d6d081a2372dc ./kintex7/tile_type_CFG_CENTER_MID.json`](./kintex7/tile_type_CFG_CENTER_MID.json)
* [`020ae47321f03311f5897f2c79c569368315a816a42549289d009570a2d76c4a ./kintex7/tile_type_CFG_CENTER_TOP.json`](./kintex7/tile_type_CFG_CENTER_TOP.json)
* [`a49fcafa32e32533ded2d3425d1b0b072e841f932747e6169118837bcf2b59d1 ./kintex7/tile_type_CLBLL_L.json`](./kintex7/tile_type_CLBLL_L.json)
* [`fadf83bf66fb1597816743f59567e632c494495545e00b0d02aa6207691a85b2 ./kintex7/tile_type_CLBLL_R.json`](./kintex7/tile_type_CLBLL_R.json)
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* [`bfc9e3df22c7a99e9af69c7110b1c404fe607c84c3dc77b8004273b630e35fb8 ./kintex7/tile_type_CLK_BUFG_BOT_R.json`](./kintex7/tile_type_CLK_BUFG_BOT_R.json)
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* [`9c2af1c0da6184efb136bd14308401459a411c95bdb2ffc1a51c42fed96b6146 ./kintex7/tile_type_CLK_FEED.json`](./kintex7/tile_type_CLK_FEED.json)
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* [`acbd313bd0e8fa6bc14d913035d9f48c44bdc694b44b80af81003230b6b43bc3 ./kintex7/tile_type_CLK_TERM.json`](./kintex7/tile_type_CLK_TERM.json)
* [`7ebaf8de3ac6d90a54f7bba8ad9296f711e495d31faff3d69d7fa5a738536345 ./kintex7/tile_type_CMT_FIFO_L.json`](./kintex7/tile_type_CMT_FIFO_L.json)
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* [`c923a360ae2c99bb443282431b03ba8b8fba68d05b82a0ff797b716f34bfc251 ./kintex7/tile_type_HCLK_DSP_R.json`](./kintex7/tile_type_HCLK_DSP_R.json)
* [`dde046196e4a4d4da476226fd9667483f82d39cef00bf9dc38cef5f17ab1c914 ./kintex7/tile_type_HCLK_FEEDTHRU_1.json`](./kintex7/tile_type_HCLK_FEEDTHRU_1.json)
* [`9bbb0a7d24a5d02ad01c0e39039130ccc909e879abc349a92f597cbe469dd49d ./kintex7/tile_type_HCLK_FEEDTHRU_2.json`](./kintex7/tile_type_HCLK_FEEDTHRU_2.json)
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* [`8425afb4d0a2d98e1dfd1d26393aa80a74e51f56d1e9aef8935a7970f04bf14d ./kintex7/tile_type_HCLK_GTX.json`](./kintex7/tile_type_HCLK_GTX.json)
* [`81407bfaf8f2526850bd6d4e715895af022f0408c91484608b8381fc12393df2 ./kintex7/tile_type_HCLK_INT_INTERFACE.json`](./kintex7/tile_type_HCLK_INT_INTERFACE.json)
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* [`76260e86d5ecdd6b1f114ffe05ac2a959afcaca4be25635c2d4ecf3f76ff6986 ./kintex7/tile_type_HCLK_IOI3.json`](./kintex7/tile_type_HCLK_IOI3.json)
* [`d39f1659520b0538d275a30d56a24eb176174e10f43fd8817363cc26ddca1f0c ./kintex7/tile_type_HCLK_IOI.json`](./kintex7/tile_type_HCLK_IOI.json)
* [`34f7588770dde88264dfa413b3a56d724001efcf8a70b696a44ac87810150ec6 ./kintex7/tile_type_HCLK_L_BOT_UTURN.json`](./kintex7/tile_type_HCLK_L_BOT_UTURN.json)
* [`574450912455e0c9088b68833d6e535b8868f34deee4c25387301b1de9296a00 ./kintex7/tile_type_HCLK_L.json`](./kintex7/tile_type_HCLK_L.json)
* [`037972ef07a8be72225783db245097c0037b4fd4a42c3551b60114b65968973a ./kintex7/tile_type_HCLK_R_BOT_UTURN.json`](./kintex7/tile_type_HCLK_R_BOT_UTURN.json)
* [`064f051fd195837ec3dd8560bb555be5ce1b66bd8eec94e8b709e365a1fcc2d5 ./kintex7/tile_type_HCLK_R.json`](./kintex7/tile_type_HCLK_R.json)
* [`52aff0ffab55a41d78b9a276dee0b9decc97022c020c74c5a96ad3d92bed5863 ./kintex7/tile_type_HCLK_TERM_GTX.json`](./kintex7/tile_type_HCLK_TERM_GTX.json)
* [`eb62ef0efc2a718ccf84321087ad832ab0467b3203d680adc701179fadc91bf6 ./kintex7/tile_type_HCLK_TERM.json`](./kintex7/tile_type_HCLK_TERM.json)
* [`220b12b284dddb2c238552b0218797d0ba3457ed18175ab70cef8415f0c0201a ./kintex7/tile_type_HCLK_VBRK.json`](./kintex7/tile_type_HCLK_VBRK.json)
* [`46330a09e75de3b349d69a0083b9304822f7fbf8ae1a5fb763da4784973dd240 ./kintex7/tile_type_HCLK_VFRAME.json`](./kintex7/tile_type_HCLK_VFRAME.json)
* [`7f09e309e6653af7118d7fc931fe31b246b7cc8531923861496eedf3dc77b5be ./kintex7/tile_type_INT_FEEDTHRU_1.json`](./kintex7/tile_type_INT_FEEDTHRU_1.json)
* [`28b7ecc94f160d54bc79368c562fe4df0e843509e5434771ed8f6b55f18b6bf4 ./kintex7/tile_type_INT_FEEDTHRU_2.json`](./kintex7/tile_type_INT_FEEDTHRU_2.json)
* [`6aa23f8918efc454795ab7822e52e3999edb1c198eddd8e6aa0c2f653d40d1e4 ./kintex7/tile_type_INT_INTERFACE_L.json`](./kintex7/tile_type_INT_INTERFACE_L.json)
* [`0b317673faf61ae014f66ceb9db46191c8e4f3c8b0a14cc017982ef283e4395e ./kintex7/tile_type_INT_INTERFACE_R.json`](./kintex7/tile_type_INT_INTERFACE_R.json)
* [`26700b39a04bd369ee5563ca9e84ac01f87895c05da73e0ce6046336cc8852ce ./kintex7/tile_type_INT_L.json`](./kintex7/tile_type_INT_L.json)
* [`2e37a5d868bd73ddc1a7d1ecf90df3e8710e6bbbb9f972c14129116326a6b4e4 ./kintex7/tile_type_INT_R.json`](./kintex7/tile_type_INT_R.json)
* [`aa66ce19f9ad6b965241375bfb47bd89e2a1348a58c968368e86281931b44590 ./kintex7/tile_type_IO_INT_INTERFACE_L.json`](./kintex7/tile_type_IO_INT_INTERFACE_L.json)
* [`0b1638c1d020419c7cd893f6f0777fe7e9b31f59cd3df806a04a1d8a75236ca4 ./kintex7/tile_type_IO_INT_INTERFACE_R.json`](./kintex7/tile_type_IO_INT_INTERFACE_R.json)
* [`834aeafff58ab00c55362bcb5b8f57a0c4eba75bed850857396f451005de25b7 ./kintex7/tile_type_LIOB33.json`](./kintex7/tile_type_LIOB33.json)
* [`1cd4802b53f8b51ebda08cb505216bd2359ebe8a25b9b25f0a47009e7bd50a0e ./kintex7/tile_type_LIOB33_SING.json`](./kintex7/tile_type_LIOB33_SING.json)
* [`197d350086961d53460b275c6d38f58dff6b9ddc4022498c1ba7462e975167b6 ./kintex7/tile_type_LIOI3.json`](./kintex7/tile_type_LIOI3.json)
* [`fcee806a19995fefb66d1abf203cabe4551ca5a1555b74438ddb9ebde743a3b7 ./kintex7/tile_type_LIOI3_SING.json`](./kintex7/tile_type_LIOI3_SING.json)
* [`72d291224c4e6a7c875a3985731909c51c7e912670215ce3102129b879d4237d ./kintex7/tile_type_LIOI3_TBYTESRC.json`](./kintex7/tile_type_LIOI3_TBYTESRC.json)
* [`afb7e0c93c96a5f1390d9ea8a7a1427f13a523949ccc3cfb4e73c8a95ecdecf8 ./kintex7/tile_type_LIOI3_TBYTETERM.json`](./kintex7/tile_type_LIOI3_TBYTETERM.json)
* [`916025d46555f5911087f1f062d9af1fb5f8fc69df39cc5d230d448098ff32e6 ./kintex7/tile_type_L_TERM_INT.json`](./kintex7/tile_type_L_TERM_INT.json)
* [`76c1cd952c48be9fc23f284bccaef7fc45589ec023aee73266984877c034d8f7 ./kintex7/tile_type_MONITOR_BOT_FUJI2.json`](./kintex7/tile_type_MONITOR_BOT_FUJI2.json)
* [`6ba81b6b8cc26d484121a92431e780fb60a4fcf3fc5fb87c057281a671b01536 ./kintex7/tile_type_MONITOR_MID_FUJI2.json`](./kintex7/tile_type_MONITOR_MID_FUJI2.json)
* [`86b81044a371a36deeb7c2ba96f2ae7c109a2a81dede577d887e32b129c5f18a ./kintex7/tile_type_MONITOR_TOP_FUJI2.json`](./kintex7/tile_type_MONITOR_TOP_FUJI2.json)
* [`5d1de70987a005e1b8b2fa0589cd53a201e1f2c9836921e6040a000b9484a228 ./kintex7/tile_type_NULL.json`](./kintex7/tile_type_NULL.json)
* [`1ecb8c465ca2a8586c69e79c3d8ec072b9c2c875df10bd1de4decb8bc92f9d55 ./kintex7/tile_type_PCIE_BOT.json`](./kintex7/tile_type_PCIE_BOT.json)
* [`aa7b93e6c781119b8d5f87a10fc48ebaa73a4eead078e93132b7ddaa33dc88c3 ./kintex7/tile_type_PCIE_INT_INTERFACE_L.json`](./kintex7/tile_type_PCIE_INT_INTERFACE_L.json)
* [`0ec7eb6ac887ffd60a1cce398c2b221bcbfb0fc7b4cdff1127beecc48197e3a7 ./kintex7/tile_type_PCIE_INT_INTERFACE_R.json`](./kintex7/tile_type_PCIE_INT_INTERFACE_R.json)
* [`f8abe2a7f48b0b15d56403fe33643420508dfb0b864fb2dd1318705bae67eeb0 ./kintex7/tile_type_PCIE_NULL.json`](./kintex7/tile_type_PCIE_NULL.json)
* [`0f42ceb80f80cdead3214dd5082582573d861183720c3f68aa9efe6510c81252 ./kintex7/tile_type_PCIE_TOP.json`](./kintex7/tile_type_PCIE_TOP.json)
* [`e7ba0a1160e8ca8a9a99ca17b5c624dc75858ae448adb1ff1e1dadd90d9cd602 ./kintex7/tile_type_RIOB18.json`](./kintex7/tile_type_RIOB18.json)
* [`e3e6fcf61bcdee2fd8b46d6e9669b4c73feb8f19e6796762f9ccbad14e5448fe ./kintex7/tile_type_RIOB18_SING.json`](./kintex7/tile_type_RIOB18_SING.json)
* [`41e9510b0f26afe800182bbd33f9bd595c62da90e5240513ba45acae935e15b2 ./kintex7/tile_type_RIOI.json`](./kintex7/tile_type_RIOI.json)
* [`f49c630e38cdae7604634429d94f3f366fdaa7633d8839db2ce981c88aa42f53 ./kintex7/tile_type_RIOI_SING.json`](./kintex7/tile_type_RIOI_SING.json)
* [`f9f803ced00d2affd7f15055757ff71010f336622c023ba96d55afdb1e93df2e ./kintex7/tile_type_RIOI_TBYTESRC.json`](./kintex7/tile_type_RIOI_TBYTESRC.json)
* [`b451e9504276aa50b8ab30db52de2b0c90e539d93565e0fa2fd1286c9fe9701c ./kintex7/tile_type_RIOI_TBYTETERM.json`](./kintex7/tile_type_RIOI_TBYTETERM.json)
* [`8b67fcc25ba2c2a2fc6e40e02b9c937a2f24a15cf341b76f185505e3de8b1f30 ./kintex7/tile_type_R_TERM_INT_GTX.json`](./kintex7/tile_type_R_TERM_INT_GTX.json)
* [`e4fb30a3dbc933eb7329ae159d273d3c1812db2cc687a96ff9593723978b3aa8 ./kintex7/tile_type_R_TERM_INT.json`](./kintex7/tile_type_R_TERM_INT.json)
* [`f9376a728ef3da4da5cabdc092004a3147ad5ef4f23fb35b123c808ca8cf70c4 ./kintex7/tile_type_TERM_CMT.json`](./kintex7/tile_type_TERM_CMT.json)
* [`05c16b5d98372ae3c77cdd752aaf56fa2eb9f935a976c93cbc1228e5e2c79f22 ./kintex7/tile_type_T_TERM_INT.json`](./kintex7/tile_type_T_TERM_INT.json)
* [`3c16819ae98be7cb228351b295b569dd44f9783f76dd986c230c9627b2051479 ./kintex7/tile_type_VBRK_EXT.json`](./kintex7/tile_type_VBRK_EXT.json)
* [`b1df8c22d9d53b06c1e99cef0671c426c5b6b07af2a829b5a6ba4d135b4190d7 ./kintex7/tile_type_VBRK.json`](./kintex7/tile_type_VBRK.json)
* [`29958122ee0af5d22e10da2fca1ebd680c7aeda1f600ebeeab71d350de8c4a55 ./kintex7/tile_type_VFRAME.json`](./kintex7/tile_type_VFRAME.json)
* [`44c1530cc9a184551c98face08bd4ab0a7ec3883623175a52da5c59fba9bfa38 ./kintex7/xc7k70tfbg676-2.yaml`](./kintex7/xc7k70tfbg676-2.yaml)

12
artix7/settings.sh
View File

@ -1,12 +1,14 @@
export XRAY_DATABASE="artix7"
export XRAY_PART="xc7a50tfgg484-1"
export XRAY_ROI="SLICE_X12Y100:SLICE_X27Y149"
export XRAY_ROI_FRAMES="0x00000000:0xffffffff"
# Leave some CLBs to the left to allow easy ROI entering
export XRAY_ROI="SLICE_X8Y100:SLICE_X27Y149 RAMB18_X0Y40:RAMB18_X0Y59 RAMB36_X0Y20:RAMB36_X0Y29 DSP48_X0Y40:DSP48_X0Y59"
export XRAY_ROI_GRID_X1="18"
export XRAY_ROI_GRID_X2="47"
# All CLB's in part, all BRAM's in part, all DSP's in part.
export XRAY_ROI="SLICE_X0Y0:SLICE_X65Y99 SLICE_X0Y100:SLICE_X57Y149 RAMB18_X0Y0:RAMB18_X1Y59 RAMB36_X0Y0:RAMB36_X1Y29 RAMB18_X2Y0:RAMB18_X2Y39 RAMB36_X2Y0:RAMB36_X2Y19 DSP48_X0Y0:DSP48_X1Y59"
# Most of CMT X0Y2.
export XRAY_ROI_GRID_X1="9"
export XRAY_ROI_GRID_X2="58"
# Include VBRK / VTERM
export XRAY_ROI_GRID_Y1="0"
export XRAY_ROI_GRID_Y2="52"

9
kintex7/element_counts.csv Normal file
View File

@ -0,0 +1,9 @@
type,count
tiles,24453
sites,20251
site_pins,740913
site_pips,1505860
pips,29424910
package_pins,676
nodes,2663055
wires,8339126
1 type count
2 tiles 24453
3 sites 20251
4 site_pins 740913
5 site_pips 1505860
6 pips 29424910
7 package_pins 676
8 nodes 2663055
9 wires 8339126

8222
kintex7/mask_bram_l.db Normal file
View File

File diff suppressed because it is too large Load Diff

8222
kintex7/mask_bram_r.db Normal file
View File

File diff suppressed because it is too large Load Diff

30
kintex7/mask_clbll_l.db
View File

@ -1,6 +1,8 @@
bit 00_00
bit 00_01
bit 00_02
bit 00_03
bit 00_04
bit 00_05
bit 00_06
bit 00_07
@ -16,12 +18,15 @@ bit 00_16
bit 00_17
bit 00_18
bit 00_19
bit 00_20
bit 00_21
bit 00_22
bit 00_23
bit 00_24
bit 00_25
bit 00_26
bit 00_27
bit 00_28
bit 00_29
bit 00_30
bit 00_32
@ -32,6 +37,7 @@ bit 00_36
bit 00_37
bit 00_38
bit 00_39
bit 00_40
bit 00_41
bit 00_42
bit 00_43
@ -42,12 +48,18 @@ bit 00_47
bit 00_48
bit 00_49
bit 00_50
bit 00_51
bit 00_52
bit 00_53
bit 00_54
bit 00_55
bit 00_56
bit 00_57
bit 00_58
bit 00_59
bit 00_61
bit 00_62
bit 00_63
bit 01_00
bit 01_01
bit 01_02
@ -71,9 +83,11 @@ bit 01_19
bit 01_20
bit 01_21
bit 01_22
bit 01_23
bit 01_24
bit 01_25
bit 01_26
bit 01_27
bit 01_28
bit 01_29
bit 01_31
@ -88,6 +102,7 @@ bit 01_39
bit 01_40
bit 01_41
bit 01_42
bit 01_43
bit 01_44
bit 01_45
bit 01_46
@ -98,7 +113,14 @@ bit 01_50
bit 01_51
bit 01_52
bit 01_53
bit 01_54
bit 01_55
bit 01_56
bit 01_57
bit 01_58
bit 01_59
bit 01_60
bit 01_61
bit 01_62
bit 02_01
bit 02_02
@ -1876,6 +1898,8 @@ bit 30_12
bit 30_13
bit 30_14
bit 30_15
bit 30_16
bit 30_17
bit 30_18
bit 30_19
bit 30_20
@ -1903,6 +1927,8 @@ bit 30_42
bit 30_43
bit 30_44
bit 30_45
bit 30_46
bit 30_47
bit 30_48
bit 30_49
bit 30_50
@ -1934,6 +1960,8 @@ bit 31_12
bit 31_13
bit 31_14
bit 31_15
bit 31_16
bit 31_17
bit 31_18
bit 31_19
bit 31_20
@ -1961,6 +1989,8 @@ bit 31_42
bit 31_43
bit 31_44
bit 31_45
bit 31_46
bit 31_47
bit 31_48
bit 31_49
bit 31_50

139
kintex7/mask_clbll_r.db
View File

@ -1,4 +1,13 @@
bit 00_00
bit 00_01
bit 00_02
bit 00_03
bit 00_04
bit 00_05
bit 00_06
bit 00_07
bit 00_08
bit 00_09
bit 00_10
bit 00_11
bit 00_12
@ -9,12 +18,15 @@ bit 00_16
bit 00_17
bit 00_18
bit 00_19
bit 00_20
bit 00_21
bit 00_22
bit 00_23
bit 00_24
bit 00_25
bit 00_26
bit 00_27
bit 00_28
bit 00_29
bit 00_30
bit 00_32
@ -25,14 +37,38 @@ bit 00_36
bit 00_37
bit 00_38
bit 00_39
bit 00_40
bit 00_41
bit 00_42
bit 00_43
bit 00_44
bit 00_45
bit 00_46
bit 00_47
bit 00_48
bit 00_49
bit 00_50
bit 00_51
bit 00_52
bit 00_53
bit 00_54
bit 00_55
bit 00_56
bit 00_57
bit 00_58
bit 00_59
bit 00_61
bit 00_62
bit 00_63
bit 01_00
bit 01_01
bit 01_02
bit 01_03
bit 01_04
bit 01_05
bit 01_06
bit 01_07
bit 01_08
bit 01_09
bit 01_10
bit 01_11
@ -47,9 +83,11 @@ bit 01_19
bit 01_20
bit 01_21
bit 01_22
bit 01_23
bit 01_24
bit 01_25
bit 01_26
bit 01_27
bit 01_28
bit 01_29
bit 01_31
@ -63,9 +101,27 @@ bit 01_38
bit 01_39
bit 01_40
bit 01_41
bit 01_42
bit 01_43
bit 01_44
bit 01_45
bit 01_46
bit 01_47
bit 01_48
bit 01_49
bit 01_50
bit 01_51
bit 01_52
bit 01_53
bit 01_54
bit 01_55
bit 01_56
bit 01_57
bit 01_58
bit 01_59
bit 01_60
bit 01_61
bit 01_62
bit 02_01
bit 02_02
bit 02_03
@ -1826,47 +1882,130 @@ bit 29_60
bit 29_61
bit 29_62
bit 29_63
bit 30_00
bit 30_01
bit 30_02
bit 30_03
bit 30_04
bit 30_05
bit 30_06
bit 30_07
bit 30_08
bit 30_09
bit 30_10
bit 30_11
bit 30_12
bit 30_13
bit 30_14
bit 30_15
bit 30_16
bit 30_17
bit 30_18
bit 30_19
bit 30_20
bit 30_21
bit 30_22
bit 30_23
bit 30_24
bit 30_25
bit 30_26
bit 30_27
bit 30_28
bit 30_29
bit 30_30
bit 30_32
bit 30_33
bit 30_34
bit 30_35
bit 30_36
bit 30_37
bit 30_38
bit 30_39
bit 30_40
bit 30_41
bit 30_42
bit 30_43
bit 30_44
bit 30_45
bit 30_46
bit 30_47
bit 30_48
bit 30_49
bit 30_50
bit 30_51
bit 30_52
bit 30_53
bit 30_54
bit 30_55
bit 30_56
bit 30_57
bit 30_58
bit 30_59
bit 30_60
bit 30_61
bit 30_62
bit 31_00
bit 31_01
bit 31_02
bit 31_03
bit 31_04
bit 31_05
bit 31_06
bit 31_07
bit 31_08
bit 31_09
bit 31_10
bit 31_11
bit 31_12
bit 31_13
bit 31_14
bit 31_15
bit 31_16
bit 31_17
bit 31_18
bit 31_19
bit 31_20
bit 31_21
bit 31_22
bit 31_23
bit 31_24
bit 31_25
bit 31_26
bit 31_27
bit 31_28
bit 31_29
bit 31_30
bit 31_32
bit 31_33
bit 31_34
bit 31_35
bit 31_36
bit 31_37
bit 31_38
bit 31_39
bit 31_40
bit 31_41
bit 31_42
bit 31_43
bit 31_44
bit 31_45
bit 31_46
bit 31_47
bit 31_48
bit 31_49
bit 31_50
bit 31_51
bit 31_52
bit 31_53
bit 31_54
bit 31_55
bit 31_56
bit 31_57
bit 31_58
bit 31_59
bit 31_60
bit 31_61
bit 31_62
bit 32_00
bit 32_01
bit 32_02

20
kintex7/mask_clblm_l.db
View File

@ -37,6 +37,7 @@ bit 00_36
bit 00_37
bit 00_38
bit 00_39
bit 00_40
bit 00_41
bit 00_42
bit 00_43
@ -45,12 +46,20 @@ bit 00_45
bit 00_46
bit 00_47
bit 00_48
bit 00_49
bit 00_50
bit 00_51
bit 00_52
bit 00_53
bit 00_54
bit 00_55
bit 00_56
bit 00_57
bit 00_58
bit 00_59
bit 00_61
bit 00_62
bit 00_63
bit 01_00
bit 01_01
bit 01_02
@ -78,6 +87,7 @@ bit 01_23
bit 01_24
bit 01_25
bit 01_26
bit 01_27
bit 01_28
bit 01_29
bit 01_31
@ -103,8 +113,14 @@ bit 01_50
bit 01_51
bit 01_52
bit 01_53
bit 01_54
bit 01_55
bit 01_56
bit 01_57
bit 01_58
bit 01_59
bit 01_60
bit 01_61
bit 01_62
bit 02_01
bit 02_02
@ -1882,6 +1898,8 @@ bit 30_12
bit 30_13
bit 30_14
bit 30_15
bit 30_16
bit 30_17
bit 30_18
bit 30_19
bit 30_20
@ -1909,6 +1927,8 @@ bit 30_42
bit 30_43
bit 30_44
bit 30_45
bit 30_46
bit 30_47
bit 30_48
bit 30_49
bit 30_50

22
kintex7/mask_clblm_r.db
View File

@ -37,6 +37,7 @@ bit 00_36
bit 00_37
bit 00_38
bit 00_39
bit 00_40
bit 00_41
bit 00_42
bit 00_43
@ -45,11 +46,20 @@ bit 00_45
bit 00_46
bit 00_47
bit 00_48
bit 00_49
bit 00_50
bit 00_51
bit 00_52
bit 00_53
bit 00_54
bit 00_55
bit 00_56
bit 00_57
bit 00_58
bit 00_59
bit 00_61
bit 00_62
bit 00_63
bit 01_00
bit 01_01
bit 01_02
@ -77,6 +87,7 @@ bit 01_23
bit 01_24
bit 01_25
bit 01_26
bit 01_27
bit 01_28
bit 01_29
bit 01_31
@ -102,8 +113,15 @@ bit 01_50
bit 01_51
bit 01_52
bit 01_53
bit 01_54
bit 01_55
bit 01_56
bit 01_57
bit 01_58
bit 01_59
bit 01_60
bit 01_61
bit 01_62
bit 02_01
bit 02_02
bit 02_03
@ -1880,6 +1898,8 @@ bit 30_12
bit 30_13
bit 30_14
bit 30_15
bit 30_16
bit 30_17
bit 30_18
bit 30_19
bit 30_20
@ -1907,6 +1927,8 @@ bit 30_42
bit 30_43
bit 30_44
bit 30_45
bit 30_46
bit 30_47
bit 30_48
bit 30_49
bit 30_50

8030
kintex7/mask_dsp_l.db Normal file
View File

File diff suppressed because it is too large Load Diff

8030
kintex7/mask_dsp_r.db Normal file
View File

File diff suppressed because it is too large Load Diff

104
kintex7/mask_hclk_l.db Normal file
View File

@ -0,0 +1,104 @@
bit 00_14
bit 00_15
bit 00_16
bit 00_17
bit 00_18
bit 00_20
bit 00_21
bit 00_22
bit 00_23
bit 00_24
bit 00_25
bit 00_26
bit 00_28
bit 00_29
bit 00_30
bit 00_31
bit 01_14
bit 01_15
bit 01_16
bit 01_17
bit 01_19
bit 01_20
bit 01_21
bit 01_22
bit 01_23
bit 01_24
bit 01_25
bit 01_26
bit 01_28
bit 01_29
bit 01_30
bit 01_31
bit 02_14
bit 02_15
bit 02_16
bit 02_17
bit 02_18
bit 02_19
bit 02_20
bit 02_21
bit 02_22
bit 02_23
bit 02_24
bit 02_25
bit 02_26
bit 02_27
bit 02_28
bit 02_29
bit 02_30
bit 02_31
bit 03_14
bit 03_15
bit 03_16
bit 03_17
bit 03_18
bit 03_19
bit 03_20
bit 03_21
bit 03_22
bit 03_23
bit 03_24
bit 03_25
bit 03_26
bit 03_27
bit 03_28
bit 03_29
bit 03_30
bit 03_31
bit 04_14
bit 04_15
bit 04_16
bit 04_17
bit 04_18
bit 04_19
bit 04_20
bit 04_21
bit 04_22
bit 04_23
bit 04_24
bit 04_25
bit 04_26
bit 04_27
bit 04_28
bit 04_29
bit 04_30
bit 04_31
bit 05_14
bit 05_15
bit 05_16
bit 05_17
bit 05_18
bit 05_19
bit 05_20
bit 05_21
bit 05_22
bit 05_23
bit 05_24
bit 05_25
bit 05_26
bit 05_27
bit 05_28
bit 05_29
bit 05_30
bit 05_31

104
kintex7/mask_hclk_r.db Normal file
View File

@ -0,0 +1,104 @@
bit 00_14
bit 00_15
bit 00_16
bit 00_17
bit 00_18
bit 00_20
bit 00_21
bit 00_22
bit 00_23
bit 00_24
bit 00_25
bit 00_26
bit 00_28
bit 00_29
bit 00_30
bit 00_31
bit 01_14
bit 01_15
bit 01_16
bit 01_17
bit 01_19
bit 01_20
bit 01_21
bit 01_22
bit 01_23
bit 01_24
bit 01_25
bit 01_26
bit 01_28
bit 01_29
bit 01_30
bit 01_31
bit 02_14
bit 02_15
bit 02_16
bit 02_17
bit 02_18
bit 02_19
bit 02_20
bit 02_21
bit 02_22
bit 02_23
bit 02_24
bit 02_25
bit 02_26
bit 02_27
bit 02_28
bit 02_29
bit 02_30
bit 02_31
bit 03_14
bit 03_15
bit 03_16
bit 03_17
bit 03_18
bit 03_19
bit 03_20
bit 03_21
bit 03_22
bit 03_23
bit 03_24
bit 03_25
bit 03_26
bit 03_27
bit 03_28
bit 03_29
bit 03_30
bit 03_31
bit 04_14
bit 04_15
bit 04_16
bit 04_17
bit 04_18
bit 04_19
bit 04_20
bit 04_21
bit 04_22
bit 04_23
bit 04_24
bit 04_25
bit 04_26
bit 04_27
bit 04_28
bit 04_29
bit 04_30
bit 04_31
bit 05_14
bit 05_15
bit 05_16
bit 05_17
bit 05_18
bit 05_19
bit 05_20
bit 05_21
bit 05_22
bit 05_23
bit 05_24
bit 05_25
bit 05_26
bit 05_27
bit 05_28
bit 05_29
bit 05_30
bit 05_31

146
kintex7/ppips_clbll_l.db Normal file
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@ -0,0 +1,146 @@
CLBLL_L.CLBLL_L_AX.CLBLL_BYP0 always
CLBLL_L.CLBLL_LL_AX.CLBLL_BYP1 always
CLBLL_L.CLBLL_L_CX.CLBLL_BYP2 always
CLBLL_L.CLBLL_LL_CX.CLBLL_BYP3 always
CLBLL_L.CLBLL_LL_BX.CLBLL_BYP4 always
CLBLL_L.CLBLL_L_BX.CLBLL_BYP5 always
CLBLL_L.CLBLL_LL_DX.CLBLL_BYP6 always
CLBLL_L.CLBLL_L_DX.CLBLL_BYP7 always
CLBLL_L.CLBLL_L_CLK.CLBLL_CLK0 always
CLBLL_L.CLBLL_LL_CLK.CLBLL_CLK1 always
CLBLL_L.CLBLL_L_SR.CLBLL_CTRL0 always
CLBLL_L.CLBLL_LL_SR.CLBLL_CTRL1 always
CLBLL_L.CLBLL_L_CE.CLBLL_FAN6 always
CLBLL_L.CLBLL_LL_CE.CLBLL_FAN7 always
CLBLL_L.CLBLL_L_A3.CLBLL_IMUX0 always
CLBLL_L.CLBLL_L_A2.CLBLL_IMUX3 always
CLBLL_L.CLBLL_L_A6.CLBLL_IMUX5 always
CLBLL_L.CLBLL_L_A1.CLBLL_IMUX6 always
CLBLL_L.CLBLL_L_A5.CLBLL_IMUX9 always
CLBLL_L.CLBLL_L_A4.CLBLL_IMUX10 always
CLBLL_L.CLBLL_LL_A3.CLBLL_IMUX1 always
CLBLL_L.CLBLL_LL_A2.CLBLL_IMUX2 always
CLBLL_L.CLBLL_LL_A6.CLBLL_IMUX4 always
CLBLL_L.CLBLL_LL_A1.CLBLL_IMUX7 always
CLBLL_L.CLBLL_LL_A5.CLBLL_IMUX8 always
CLBLL_L.CLBLL_LL_A4.CLBLL_IMUX11 always
CLBLL_L.CLBLL_LL_B6.CLBLL_IMUX12 always
CLBLL_L.CLBLL_LL_B1.CLBLL_IMUX15 always
CLBLL_L.CLBLL_LL_B3.CLBLL_IMUX17 always
CLBLL_L.CLBLL_LL_B2.CLBLL_IMUX18 always
CLBLL_L.CLBLL_LL_B5.CLBLL_IMUX24 always
CLBLL_L.CLBLL_LL_B4.CLBLL_IMUX27 always
CLBLL_L.CLBLL_L_B6.CLBLL_IMUX13 always
CLBLL_L.CLBLL_L_B1.CLBLL_IMUX14 always
CLBLL_L.CLBLL_L_B3.CLBLL_IMUX16 always
CLBLL_L.CLBLL_L_B2.CLBLL_IMUX19 always
CLBLL_L.CLBLL_L_B5.CLBLL_IMUX25 always
CLBLL_L.CLBLL_L_B4.CLBLL_IMUX26 always
CLBLL_L.CLBLL_L_C2.CLBLL_IMUX20 always
CLBLL_L.CLBLL_L_C4.CLBLL_IMUX21 always
CLBLL_L.CLBLL_L_C3.CLBLL_IMUX23 always
CLBLL_L.CLBLL_L_C5.CLBLL_IMUX30 always
CLBLL_L.CLBLL_L_C1.CLBLL_IMUX33 always
CLBLL_L.CLBLL_L_C6.CLBLL_IMUX34 always
CLBLL_L.CLBLL_LL_C3.CLBLL_IMUX22 always
CLBLL_L.CLBLL_LL_C4.CLBLL_IMUX28 always
CLBLL_L.CLBLL_LL_C2.CLBLL_IMUX29 always
CLBLL_L.CLBLL_LL_C5.CLBLL_IMUX31 always
CLBLL_L.CLBLL_LL_C1.CLBLL_IMUX32 always
CLBLL_L.CLBLL_LL_C6.CLBLL_IMUX35 always
CLBLL_L.CLBLL_L_D2.CLBLL_IMUX36 always
CLBLL_L.CLBLL_L_D4.CLBLL_IMUX37 always
CLBLL_L.CLBLL_L_D3.CLBLL_IMUX39 always
CLBLL_L.CLBLL_L_D1.CLBLL_IMUX41 always
CLBLL_L.CLBLL_L_D6.CLBLL_IMUX42 always
CLBLL_L.CLBLL_L_D5.CLBLL_IMUX46 always
CLBLL_L.CLBLL_LL_D3.CLBLL_IMUX38 always
CLBLL_L.CLBLL_LL_D1.CLBLL_IMUX40 always
CLBLL_L.CLBLL_LL_D6.CLBLL_IMUX43 always
CLBLL_L.CLBLL_LL_D4.CLBLL_IMUX44 always
CLBLL_L.CLBLL_LL_D2.CLBLL_IMUX45 always
CLBLL_L.CLBLL_LL_D5.CLBLL_IMUX47 always
CLBLL_L.CLBLL_LOGIC_OUTS12.CLBLL_LL_A always
CLBLL_L.CLBLL_LL_AMUX.CLBLL_LL_A hint
CLBLL_L.CLBLL_LL_A.CLBLL_LL_A1 hint
CLBLL_L.CLBLL_LL_A.CLBLL_LL_A2 hint
CLBLL_L.CLBLL_LL_A.CLBLL_LL_A3 hint
CLBLL_L.CLBLL_LL_A.CLBLL_LL_A4 hint
CLBLL_L.CLBLL_LL_A.CLBLL_LL_A5 hint
CLBLL_L.CLBLL_LL_A.CLBLL_LL_A6 hint
CLBLL_L.CLBLL_LOGIC_OUTS20.CLBLL_LL_AMUX always
CLBLL_L.CLBLL_LOGIC_OUTS4.CLBLL_LL_AQ always
CLBLL_L.CLBLL_LOGIC_OUTS13.CLBLL_LL_B always
CLBLL_L.CLBLL_LL_BMUX.CLBLL_LL_B hint
CLBLL_L.CLBLL_LL_B.CLBLL_LL_B1 hint
CLBLL_L.CLBLL_LL_B.CLBLL_LL_B2 hint
CLBLL_L.CLBLL_LL_B.CLBLL_LL_B3 hint
CLBLL_L.CLBLL_LL_B.CLBLL_LL_B4 hint
CLBLL_L.CLBLL_LL_B.CLBLL_LL_B5 hint
CLBLL_L.CLBLL_LL_B.CLBLL_LL_B6 hint
CLBLL_L.CLBLL_LOGIC_OUTS21.CLBLL_LL_BMUX always
CLBLL_L.CLBLL_LOGIC_OUTS5.CLBLL_LL_BQ always
CLBLL_L.CLBLL_LOGIC_OUTS14.CLBLL_LL_C always
CLBLL_L.CLBLL_LL_CMUX.CLBLL_LL_C hint
CLBLL_L.CLBLL_LL_C.CLBLL_LL_C1 hint
CLBLL_L.CLBLL_LL_C.CLBLL_LL_C2 hint
CLBLL_L.CLBLL_LL_C.CLBLL_LL_C3 hint
CLBLL_L.CLBLL_LL_C.CLBLL_LL_C4 hint
CLBLL_L.CLBLL_LL_C.CLBLL_LL_C5 hint
CLBLL_L.CLBLL_LL_C.CLBLL_LL_C6 hint
CLBLL_L.CLBLL_LOGIC_OUTS22.CLBLL_LL_CMUX always
CLBLL_L.CLBLL_LL_COUT_N.CLBLL_LL_COUT always
CLBLL_L.CLBLL_LL_DMUX.CLBLL_LL_COUT hint
CLBLL_L.CLBLL_LOGIC_OUTS6.CLBLL_LL_CQ always
CLBLL_L.CLBLL_LOGIC_OUTS15.CLBLL_LL_D always
CLBLL_L.CLBLL_LL_DMUX.CLBLL_LL_D hint
CLBLL_L.CLBLL_LL_D.CLBLL_LL_D1 hint
CLBLL_L.CLBLL_LL_D.CLBLL_LL_D2 hint
CLBLL_L.CLBLL_LL_D.CLBLL_LL_D3 hint
CLBLL_L.CLBLL_LL_D.CLBLL_LL_D4 hint
CLBLL_L.CLBLL_LL_D.CLBLL_LL_D5 hint
CLBLL_L.CLBLL_LL_D.CLBLL_LL_D6 hint
CLBLL_L.CLBLL_LOGIC_OUTS23.CLBLL_LL_DMUX always
CLBLL_L.CLBLL_LOGIC_OUTS7.CLBLL_LL_DQ always
CLBLL_L.CLBLL_LOGIC_OUTS8.CLBLL_L_A always
CLBLL_L.CLBLL_L_AMUX.CLBLL_L_A hint
CLBLL_L.CLBLL_L_A.CLBLL_L_A1 hint
CLBLL_L.CLBLL_L_A.CLBLL_L_A2 hint
CLBLL_L.CLBLL_L_A.CLBLL_L_A3 hint
CLBLL_L.CLBLL_L_A.CLBLL_L_A4 hint
CLBLL_L.CLBLL_L_A.CLBLL_L_A5 hint
CLBLL_L.CLBLL_L_A.CLBLL_L_A6 hint
CLBLL_L.CLBLL_LOGIC_OUTS16.CLBLL_L_AMUX always
CLBLL_L.CLBLL_LOGIC_OUTS0.CLBLL_L_AQ always
CLBLL_L.CLBLL_LOGIC_OUTS9.CLBLL_L_B always
CLBLL_L.CLBLL_L_BMUX.CLBLL_L_B hint
CLBLL_L.CLBLL_L_B.CLBLL_L_B1 hint
CLBLL_L.CLBLL_L_B.CLBLL_L_B2 hint
CLBLL_L.CLBLL_L_B.CLBLL_L_B3 hint
CLBLL_L.CLBLL_L_B.CLBLL_L_B4 hint
CLBLL_L.CLBLL_L_B.CLBLL_L_B5 hint
CLBLL_L.CLBLL_L_B.CLBLL_L_B6 hint
CLBLL_L.CLBLL_LOGIC_OUTS17.CLBLL_L_BMUX always
CLBLL_L.CLBLL_LOGIC_OUTS1.CLBLL_L_BQ always
CLBLL_L.CLBLL_LOGIC_OUTS10.CLBLL_L_C always
CLBLL_L.CLBLL_L_CMUX.CLBLL_L_C hint
CLBLL_L.CLBLL_L_C.CLBLL_L_C1 hint
CLBLL_L.CLBLL_L_C.CLBLL_L_C2 hint
CLBLL_L.CLBLL_L_C.CLBLL_L_C3 hint
CLBLL_L.CLBLL_L_C.CLBLL_L_C4 hint
CLBLL_L.CLBLL_L_C.CLBLL_L_C5 hint
CLBLL_L.CLBLL_L_C.CLBLL_L_C6 hint
CLBLL_L.CLBLL_LOGIC_OUTS18.CLBLL_L_CMUX always
CLBLL_L.CLBLL_L_COUT_N.CLBLL_L_COUT always
CLBLL_L.CLBLL_L_DMUX.CLBLL_L_COUT hint
CLBLL_L.CLBLL_LOGIC_OUTS2.CLBLL_L_CQ always
CLBLL_L.CLBLL_LOGIC_OUTS11.CLBLL_L_D always
CLBLL_L.CLBLL_L_DMUX.CLBLL_L_D hint
CLBLL_L.CLBLL_L_D.CLBLL_L_D1 hint
CLBLL_L.CLBLL_L_D.CLBLL_L_D2 hint
CLBLL_L.CLBLL_L_D.CLBLL_L_D3 hint
CLBLL_L.CLBLL_L_D.CLBLL_L_D4 hint
CLBLL_L.CLBLL_L_D.CLBLL_L_D5 hint
CLBLL_L.CLBLL_L_D.CLBLL_L_D6 hint
CLBLL_L.CLBLL_LOGIC_OUTS19.CLBLL_L_DMUX always
CLBLL_L.CLBLL_LOGIC_OUTS3.CLBLL_L_DQ always

146
kintex7/ppips_clbll_r.db Normal file
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@ -0,0 +1,146 @@
CLBLL_R.CLBLL_L_AX.CLBLL_BYP0 always
CLBLL_R.CLBLL_LL_AX.CLBLL_BYP1 always
CLBLL_R.CLBLL_L_CX.CLBLL_BYP2 always
CLBLL_R.CLBLL_LL_CX.CLBLL_BYP3 always
CLBLL_R.CLBLL_LL_BX.CLBLL_BYP4 always
CLBLL_R.CLBLL_L_BX.CLBLL_BYP5 always
CLBLL_R.CLBLL_LL_DX.CLBLL_BYP6 always
CLBLL_R.CLBLL_L_DX.CLBLL_BYP7 always
CLBLL_R.CLBLL_L_CLK.CLBLL_CLK0 always
CLBLL_R.CLBLL_LL_CLK.CLBLL_CLK1 always
CLBLL_R.CLBLL_L_SR.CLBLL_CTRL0 always
CLBLL_R.CLBLL_LL_SR.CLBLL_CTRL1 always
CLBLL_R.CLBLL_L_CE.CLBLL_FAN6 always
CLBLL_R.CLBLL_LL_CE.CLBLL_FAN7 always
CLBLL_R.CLBLL_L_A3.CLBLL_IMUX0 always
CLBLL_R.CLBLL_L_A2.CLBLL_IMUX3 always
CLBLL_R.CLBLL_L_A6.CLBLL_IMUX5 always
CLBLL_R.CLBLL_L_A1.CLBLL_IMUX6 always
CLBLL_R.CLBLL_L_A5.CLBLL_IMUX9 always
CLBLL_R.CLBLL_L_A4.CLBLL_IMUX10 always
CLBLL_R.CLBLL_LL_A3.CLBLL_IMUX1 always
CLBLL_R.CLBLL_LL_A2.CLBLL_IMUX2 always
CLBLL_R.CLBLL_LL_A6.CLBLL_IMUX4 always
CLBLL_R.CLBLL_LL_A1.CLBLL_IMUX7 always
CLBLL_R.CLBLL_LL_A5.CLBLL_IMUX8 always
CLBLL_R.CLBLL_LL_A4.CLBLL_IMUX11 always
CLBLL_R.CLBLL_LL_B6.CLBLL_IMUX12 always
CLBLL_R.CLBLL_LL_B1.CLBLL_IMUX15 always
CLBLL_R.CLBLL_LL_B3.CLBLL_IMUX17 always
CLBLL_R.CLBLL_LL_B2.CLBLL_IMUX18 always
CLBLL_R.CLBLL_LL_B5.CLBLL_IMUX24 always
CLBLL_R.CLBLL_LL_B4.CLBLL_IMUX27 always
CLBLL_R.CLBLL_L_B6.CLBLL_IMUX13 always
CLBLL_R.CLBLL_L_B1.CLBLL_IMUX14 always
CLBLL_R.CLBLL_L_B3.CLBLL_IMUX16 always
CLBLL_R.CLBLL_L_B2.CLBLL_IMUX19 always
CLBLL_R.CLBLL_L_B5.CLBLL_IMUX25 always
CLBLL_R.CLBLL_L_B4.CLBLL_IMUX26 always
CLBLL_R.CLBLL_L_C2.CLBLL_IMUX20 always
CLBLL_R.CLBLL_L_C4.CLBLL_IMUX21 always
CLBLL_R.CLBLL_L_C3.CLBLL_IMUX23 always
CLBLL_R.CLBLL_L_C5.CLBLL_IMUX30 always
CLBLL_R.CLBLL_L_C1.CLBLL_IMUX33 always
CLBLL_R.CLBLL_L_C6.CLBLL_IMUX34 always
CLBLL_R.CLBLL_LL_C3.CLBLL_IMUX22 always
CLBLL_R.CLBLL_LL_C4.CLBLL_IMUX28 always
CLBLL_R.CLBLL_LL_C2.CLBLL_IMUX29 always
CLBLL_R.CLBLL_LL_C5.CLBLL_IMUX31 always
CLBLL_R.CLBLL_LL_C1.CLBLL_IMUX32 always
CLBLL_R.CLBLL_LL_C6.CLBLL_IMUX35 always
CLBLL_R.CLBLL_L_D2.CLBLL_IMUX36 always
CLBLL_R.CLBLL_L_D4.CLBLL_IMUX37 always
CLBLL_R.CLBLL_L_D3.CLBLL_IMUX39 always
CLBLL_R.CLBLL_L_D1.CLBLL_IMUX41 always
CLBLL_R.CLBLL_L_D6.CLBLL_IMUX42 always
CLBLL_R.CLBLL_L_D5.CLBLL_IMUX46 always
CLBLL_R.CLBLL_LL_D3.CLBLL_IMUX38 always
CLBLL_R.CLBLL_LL_D1.CLBLL_IMUX40 always
CLBLL_R.CLBLL_LL_D6.CLBLL_IMUX43 always
CLBLL_R.CLBLL_LL_D4.CLBLL_IMUX44 always
CLBLL_R.CLBLL_LL_D2.CLBLL_IMUX45 always
CLBLL_R.CLBLL_LL_D5.CLBLL_IMUX47 always
CLBLL_R.CLBLL_LOGIC_OUTS12.CLBLL_LL_A always
CLBLL_R.CLBLL_LL_AMUX.CLBLL_LL_A hint
CLBLL_R.CLBLL_LL_A.CLBLL_LL_A1 hint
CLBLL_R.CLBLL_LL_A.CLBLL_LL_A2 hint
CLBLL_R.CLBLL_LL_A.CLBLL_LL_A3 hint
CLBLL_R.CLBLL_LL_A.CLBLL_LL_A4 hint
CLBLL_R.CLBLL_LL_A.CLBLL_LL_A5 hint
CLBLL_R.CLBLL_LL_A.CLBLL_LL_A6 hint
CLBLL_R.CLBLL_LOGIC_OUTS20.CLBLL_LL_AMUX always
CLBLL_R.CLBLL_LOGIC_OUTS4.CLBLL_LL_AQ always
CLBLL_R.CLBLL_LOGIC_OUTS13.CLBLL_LL_B always
CLBLL_R.CLBLL_LL_BMUX.CLBLL_LL_B hint
CLBLL_R.CLBLL_LL_B.CLBLL_LL_B1 hint
CLBLL_R.CLBLL_LL_B.CLBLL_LL_B2 hint
CLBLL_R.CLBLL_LL_B.CLBLL_LL_B3 hint
CLBLL_R.CLBLL_LL_B.CLBLL_LL_B4 hint
CLBLL_R.CLBLL_LL_B.CLBLL_LL_B5 hint
CLBLL_R.CLBLL_LL_B.CLBLL_LL_B6 hint
CLBLL_R.CLBLL_LOGIC_OUTS21.CLBLL_LL_BMUX always
CLBLL_R.CLBLL_LOGIC_OUTS5.CLBLL_LL_BQ always
CLBLL_R.CLBLL_LOGIC_OUTS14.CLBLL_LL_C always
CLBLL_R.CLBLL_LL_CMUX.CLBLL_LL_C hint
CLBLL_R.CLBLL_LL_C.CLBLL_LL_C1 hint
CLBLL_R.CLBLL_LL_C.CLBLL_LL_C2 hint
CLBLL_R.CLBLL_LL_C.CLBLL_LL_C3 hint
CLBLL_R.CLBLL_LL_C.CLBLL_LL_C4 hint
CLBLL_R.CLBLL_LL_C.CLBLL_LL_C5 hint
CLBLL_R.CLBLL_LL_C.CLBLL_LL_C6 hint
CLBLL_R.CLBLL_LOGIC_OUTS22.CLBLL_LL_CMUX always
CLBLL_R.CLBLL_LL_COUT_N.CLBLL_LL_COUT always
CLBLL_R.CLBLL_LL_DMUX.CLBLL_LL_COUT hint
CLBLL_R.CLBLL_LOGIC_OUTS6.CLBLL_LL_CQ always
CLBLL_R.CLBLL_LOGIC_OUTS15.CLBLL_LL_D always
CLBLL_R.CLBLL_LL_DMUX.CLBLL_LL_D hint
CLBLL_R.CLBLL_LL_D.CLBLL_LL_D1 hint
CLBLL_R.CLBLL_LL_D.CLBLL_LL_D2 hint
CLBLL_R.CLBLL_LL_D.CLBLL_LL_D3 hint
CLBLL_R.CLBLL_LL_D.CLBLL_LL_D4 hint
CLBLL_R.CLBLL_LL_D.CLBLL_LL_D5 hint
CLBLL_R.CLBLL_LL_D.CLBLL_LL_D6 hint
CLBLL_R.CLBLL_LOGIC_OUTS23.CLBLL_LL_DMUX always
CLBLL_R.CLBLL_LOGIC_OUTS7.CLBLL_LL_DQ always
CLBLL_R.CLBLL_LOGIC_OUTS8.CLBLL_L_A always
CLBLL_R.CLBLL_L_AMUX.CLBLL_L_A hint
CLBLL_R.CLBLL_L_A.CLBLL_L_A1 hint
CLBLL_R.CLBLL_L_A.CLBLL_L_A2 hint
CLBLL_R.CLBLL_L_A.CLBLL_L_A3 hint
CLBLL_R.CLBLL_L_A.CLBLL_L_A4 hint
CLBLL_R.CLBLL_L_A.CLBLL_L_A5 hint
CLBLL_R.CLBLL_L_A.CLBLL_L_A6 hint
CLBLL_R.CLBLL_LOGIC_OUTS16.CLBLL_L_AMUX always
CLBLL_R.CLBLL_LOGIC_OUTS0.CLBLL_L_AQ always
CLBLL_R.CLBLL_LOGIC_OUTS9.CLBLL_L_B always
CLBLL_R.CLBLL_L_BMUX.CLBLL_L_B hint
CLBLL_R.CLBLL_L_B.CLBLL_L_B1 hint
CLBLL_R.CLBLL_L_B.CLBLL_L_B2 hint
CLBLL_R.CLBLL_L_B.CLBLL_L_B3 hint
CLBLL_R.CLBLL_L_B.CLBLL_L_B4 hint
CLBLL_R.CLBLL_L_B.CLBLL_L_B5 hint
CLBLL_R.CLBLL_L_B.CLBLL_L_B6 hint
CLBLL_R.CLBLL_LOGIC_OUTS17.CLBLL_L_BMUX always
CLBLL_R.CLBLL_LOGIC_OUTS1.CLBLL_L_BQ always
CLBLL_R.CLBLL_LOGIC_OUTS10.CLBLL_L_C always
CLBLL_R.CLBLL_L_CMUX.CLBLL_L_C hint
CLBLL_R.CLBLL_L_C.CLBLL_L_C1 hint
CLBLL_R.CLBLL_L_C.CLBLL_L_C2 hint
CLBLL_R.CLBLL_L_C.CLBLL_L_C3 hint
CLBLL_R.CLBLL_L_C.CLBLL_L_C4 hint
CLBLL_R.CLBLL_L_C.CLBLL_L_C5 hint
CLBLL_R.CLBLL_L_C.CLBLL_L_C6 hint
CLBLL_R.CLBLL_LOGIC_OUTS18.CLBLL_L_CMUX always
CLBLL_R.CLBLL_L_COUT_N.CLBLL_L_COUT always
CLBLL_R.CLBLL_L_DMUX.CLBLL_L_COUT hint
CLBLL_R.CLBLL_LOGIC_OUTS2.CLBLL_L_CQ always
CLBLL_R.CLBLL_LOGIC_OUTS11.CLBLL_L_D always
CLBLL_R.CLBLL_L_DMUX.CLBLL_L_D hint
CLBLL_R.CLBLL_L_D.CLBLL_L_D1 hint
CLBLL_R.CLBLL_L_D.CLBLL_L_D2 hint
CLBLL_R.CLBLL_L_D.CLBLL_L_D3 hint
CLBLL_R.CLBLL_L_D.CLBLL_L_D4 hint
CLBLL_R.CLBLL_L_D.CLBLL_L_D5 hint
CLBLL_R.CLBLL_L_D.CLBLL_L_D6 hint
CLBLL_R.CLBLL_LOGIC_OUTS19.CLBLL_L_DMUX always
CLBLL_R.CLBLL_LOGIC_OUTS3.CLBLL_L_DQ always

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CLBLM_L.CLBLM_L_AX.CLBLM_BYP0 always
CLBLM_L.CLBLM_M_AX.CLBLM_BYP1 always
CLBLM_L.CLBLM_L_CX.CLBLM_BYP2 always
CLBLM_L.CLBLM_M_CX.CLBLM_BYP3 always
CLBLM_L.CLBLM_M_BX.CLBLM_BYP4 always
CLBLM_L.CLBLM_L_BX.CLBLM_BYP5 always
CLBLM_L.CLBLM_M_DX.CLBLM_BYP6 always
CLBLM_L.CLBLM_L_DX.CLBLM_BYP7 always
CLBLM_L.CLBLM_L_CLK.CLBLM_CLK0 always
CLBLM_L.CLBLM_M_CLK.CLBLM_CLK1 always
CLBLM_L.CLBLM_L_SR.CLBLM_CTRL0 always
CLBLM_L.CLBLM_M_SR.CLBLM_CTRL1 always
CLBLM_L.CLBLM_M_AI.CLBLM_FAN0 always
CLBLM_L.CLBLM_M_BI.CLBLM_FAN2 always
CLBLM_L.CLBLM_M_DI.CLBLM_FAN3 always
CLBLM_L.CLBLM_M_WE.CLBLM_FAN4 always
CLBLM_L.CLBLM_M_CI.CLBLM_FAN5 always
CLBLM_L.CLBLM_L_CE.CLBLM_FAN6 always
CLBLM_L.CLBLM_M_CE.CLBLM_FAN7 always
CLBLM_L.CLBLM_L_A3.CLBLM_IMUX0 always
CLBLM_L.CLBLM_L_A2.CLBLM_IMUX3 always
CLBLM_L.CLBLM_L_A6.CLBLM_IMUX5 always
CLBLM_L.CLBLM_L_A1.CLBLM_IMUX6 always
CLBLM_L.CLBLM_L_A5.CLBLM_IMUX9 always
CLBLM_L.CLBLM_L_A4.CLBLM_IMUX10 always
CLBLM_L.CLBLM_M_A3.CLBLM_IMUX1 always
CLBLM_L.CLBLM_M_A2.CLBLM_IMUX2 always
CLBLM_L.CLBLM_M_A6.CLBLM_IMUX4 always
CLBLM_L.CLBLM_M_A1.CLBLM_IMUX7 always
CLBLM_L.CLBLM_M_A5.CLBLM_IMUX8 always
CLBLM_L.CLBLM_M_A4.CLBLM_IMUX11 always
CLBLM_L.CLBLM_M_B6.CLBLM_IMUX12 always
CLBLM_L.CLBLM_M_B1.CLBLM_IMUX15 always
CLBLM_L.CLBLM_M_B3.CLBLM_IMUX17 always
CLBLM_L.CLBLM_M_B2.CLBLM_IMUX18 always
CLBLM_L.CLBLM_M_B5.CLBLM_IMUX24 always
CLBLM_L.CLBLM_M_B4.CLBLM_IMUX27 always
CLBLM_L.CLBLM_L_B6.CLBLM_IMUX13 always
CLBLM_L.CLBLM_L_B1.CLBLM_IMUX14 always
CLBLM_L.CLBLM_L_B3.CLBLM_IMUX16 always
CLBLM_L.CLBLM_L_B2.CLBLM_IMUX19 always
CLBLM_L.CLBLM_L_B5.CLBLM_IMUX25 always
CLBLM_L.CLBLM_L_B4.CLBLM_IMUX26 always
CLBLM_L.CLBLM_L_C2.CLBLM_IMUX20 always
CLBLM_L.CLBLM_L_C4.CLBLM_IMUX21 always
CLBLM_L.CLBLM_L_C3.CLBLM_IMUX23 always
CLBLM_L.CLBLM_L_C5.CLBLM_IMUX30 always
CLBLM_L.CLBLM_L_C1.CLBLM_IMUX33 always
CLBLM_L.CLBLM_L_C6.CLBLM_IMUX34 always
CLBLM_L.CLBLM_M_C3.CLBLM_IMUX22 always
CLBLM_L.CLBLM_M_C4.CLBLM_IMUX28 always
CLBLM_L.CLBLM_M_C2.CLBLM_IMUX29 always
CLBLM_L.CLBLM_M_C5.CLBLM_IMUX31 always
CLBLM_L.CLBLM_M_C1.CLBLM_IMUX32 always
CLBLM_L.CLBLM_M_C6.CLBLM_IMUX35 always
CLBLM_L.CLBLM_L_D2.CLBLM_IMUX36 always
CLBLM_L.CLBLM_L_D4.CLBLM_IMUX37 always
CLBLM_L.CLBLM_L_D3.CLBLM_IMUX39 always
CLBLM_L.CLBLM_L_D1.CLBLM_IMUX41 always
CLBLM_L.CLBLM_L_D6.CLBLM_IMUX42 always
CLBLM_L.CLBLM_L_D5.CLBLM_IMUX46 always
CLBLM_L.CLBLM_M_D3.CLBLM_IMUX38 always
CLBLM_L.CLBLM_M_D1.CLBLM_IMUX40 always
CLBLM_L.CLBLM_M_D6.CLBLM_IMUX43 always
CLBLM_L.CLBLM_M_D4.CLBLM_IMUX44 always
CLBLM_L.CLBLM_M_D2.CLBLM_IMUX45 always
CLBLM_L.CLBLM_M_D5.CLBLM_IMUX47 always
CLBLM_L.CLBLM_LOGIC_OUTS8.CLBLM_L_A always
CLBLM_L.CLBLM_L_AMUX.CLBLM_L_A hint
CLBLM_L.CLBLM_L_A.CLBLM_L_A1 hint
CLBLM_L.CLBLM_L_A.CLBLM_L_A2 hint
CLBLM_L.CLBLM_L_A.CLBLM_L_A3 hint
CLBLM_L.CLBLM_L_A.CLBLM_L_A4 hint
CLBLM_L.CLBLM_L_A.CLBLM_L_A5 hint
CLBLM_L.CLBLM_L_A.CLBLM_L_A6 hint
CLBLM_L.CLBLM_LOGIC_OUTS16.CLBLM_L_AMUX always
CLBLM_L.CLBLM_LOGIC_OUTS0.CLBLM_L_AQ always
CLBLM_L.CLBLM_LOGIC_OUTS9.CLBLM_L_B always
CLBLM_L.CLBLM_L_BMUX.CLBLM_L_B hint
CLBLM_L.CLBLM_L_B.CLBLM_L_B1 hint
CLBLM_L.CLBLM_L_B.CLBLM_L_B2 hint
CLBLM_L.CLBLM_L_B.CLBLM_L_B3 hint
CLBLM_L.CLBLM_L_B.CLBLM_L_B4 hint
CLBLM_L.CLBLM_L_B.CLBLM_L_B5 hint
CLBLM_L.CLBLM_L_B.CLBLM_L_B6 hint
CLBLM_L.CLBLM_LOGIC_OUTS17.CLBLM_L_BMUX always
CLBLM_L.CLBLM_LOGIC_OUTS1.CLBLM_L_BQ always
CLBLM_L.CLBLM_LOGIC_OUTS10.CLBLM_L_C always
CLBLM_L.CLBLM_L_CMUX.CLBLM_L_C hint
CLBLM_L.CLBLM_L_C.CLBLM_L_C1 hint
CLBLM_L.CLBLM_L_C.CLBLM_L_C2 hint
CLBLM_L.CLBLM_L_C.CLBLM_L_C3 hint
CLBLM_L.CLBLM_L_C.CLBLM_L_C4 hint
CLBLM_L.CLBLM_L_C.CLBLM_L_C5 hint
CLBLM_L.CLBLM_L_C.CLBLM_L_C6 hint
CLBLM_L.CLBLM_LOGIC_OUTS18.CLBLM_L_CMUX always
CLBLM_L.CLBLM_L_COUT_N.CLBLM_L_COUT always
CLBLM_L.CLBLM_L_DMUX.CLBLM_L_COUT hint
CLBLM_L.CLBLM_LOGIC_OUTS2.CLBLM_L_CQ always
CLBLM_L.CLBLM_LOGIC_OUTS11.CLBLM_L_D always
CLBLM_L.CLBLM_L_DMUX.CLBLM_L_D hint
CLBLM_L.CLBLM_L_D.CLBLM_L_D1 hint
CLBLM_L.CLBLM_L_D.CLBLM_L_D2 hint
CLBLM_L.CLBLM_L_D.CLBLM_L_D3 hint
CLBLM_L.CLBLM_L_D.CLBLM_L_D4 hint
CLBLM_L.CLBLM_L_D.CLBLM_L_D5 hint
CLBLM_L.CLBLM_L_D.CLBLM_L_D6 hint
CLBLM_L.CLBLM_LOGIC_OUTS19.CLBLM_L_DMUX always
CLBLM_L.CLBLM_LOGIC_OUTS3.CLBLM_L_DQ always
CLBLM_L.CLBLM_LOGIC_OUTS12.CLBLM_M_A always
CLBLM_L.CLBLM_M_AMUX.CLBLM_M_A hint
CLBLM_L.CLBLM_M_A.CLBLM_M_A1 hint
CLBLM_L.CLBLM_M_A.CLBLM_M_A2 hint
CLBLM_L.CLBLM_M_A.CLBLM_M_A3 hint
CLBLM_L.CLBLM_M_A.CLBLM_M_A4 hint
CLBLM_L.CLBLM_M_A.CLBLM_M_A5 hint
CLBLM_L.CLBLM_M_A.CLBLM_M_A6 hint
CLBLM_L.CLBLM_LOGIC_OUTS20.CLBLM_M_AMUX always
CLBLM_L.CLBLM_LOGIC_OUTS4.CLBLM_M_AQ always
CLBLM_L.CLBLM_LOGIC_OUTS13.CLBLM_M_B always
CLBLM_L.CLBLM_M_BMUX.CLBLM_M_B hint
CLBLM_L.CLBLM_M_B.CLBLM_M_B1 hint
CLBLM_L.CLBLM_M_B.CLBLM_M_B2 hint
CLBLM_L.CLBLM_M_B.CLBLM_M_B3 hint
CLBLM_L.CLBLM_M_B.CLBLM_M_B4 hint
CLBLM_L.CLBLM_M_B.CLBLM_M_B5 hint
CLBLM_L.CLBLM_M_B.CLBLM_M_B6 hint
CLBLM_L.CLBLM_LOGIC_OUTS21.CLBLM_M_BMUX always
CLBLM_L.CLBLM_LOGIC_OUTS5.CLBLM_M_BQ always
CLBLM_L.CLBLM_LOGIC_OUTS14.CLBLM_M_C always
CLBLM_L.CLBLM_M_CMUX.CLBLM_M_C hint
CLBLM_L.CLBLM_M_C.CLBLM_M_C1 hint
CLBLM_L.CLBLM_M_C.CLBLM_M_C2 hint
CLBLM_L.CLBLM_M_C.CLBLM_M_C3 hint
CLBLM_L.CLBLM_M_C.CLBLM_M_C4 hint
CLBLM_L.CLBLM_M_C.CLBLM_M_C5 hint
CLBLM_L.CLBLM_M_C.CLBLM_M_C6 hint
CLBLM_L.CLBLM_LOGIC_OUTS22.CLBLM_M_CMUX always
CLBLM_L.CLBLM_M_COUT_N.CLBLM_M_COUT always
CLBLM_L.CLBLM_M_DMUX.CLBLM_M_COUT hint
CLBLM_L.CLBLM_LOGIC_OUTS6.CLBLM_M_CQ always
CLBLM_L.CLBLM_LOGIC_OUTS15.CLBLM_M_D always
CLBLM_L.CLBLM_M_DMUX.CLBLM_M_D hint
CLBLM_L.CLBLM_M_D.CLBLM_M_D1 hint
CLBLM_L.CLBLM_M_D.CLBLM_M_D2 hint
CLBLM_L.CLBLM_M_D.CLBLM_M_D3 hint
CLBLM_L.CLBLM_M_D.CLBLM_M_D4 hint
CLBLM_L.CLBLM_M_D.CLBLM_M_D5 hint
CLBLM_L.CLBLM_M_D.CLBLM_M_D6 hint
CLBLM_L.CLBLM_LOGIC_OUTS23.CLBLM_M_DMUX always
CLBLM_L.CLBLM_LOGIC_OUTS7.CLBLM_M_DQ always

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CLBLM_R.CLBLM_L_AX.CLBLM_BYP0 always
CLBLM_R.CLBLM_M_AX.CLBLM_BYP1 always
CLBLM_R.CLBLM_L_CX.CLBLM_BYP2 always
CLBLM_R.CLBLM_M_CX.CLBLM_BYP3 always
CLBLM_R.CLBLM_M_BX.CLBLM_BYP4 always
CLBLM_R.CLBLM_L_BX.CLBLM_BYP5 always
CLBLM_R.CLBLM_M_DX.CLBLM_BYP6 always
CLBLM_R.CLBLM_L_DX.CLBLM_BYP7 always
CLBLM_R.CLBLM_L_CLK.CLBLM_CLK0 always
CLBLM_R.CLBLM_M_CLK.CLBLM_CLK1 always
CLBLM_R.CLBLM_L_SR.CLBLM_CTRL0 always
CLBLM_R.CLBLM_M_SR.CLBLM_CTRL1 always
CLBLM_R.CLBLM_M_AI.CLBLM_FAN0 always
CLBLM_R.CLBLM_M_BI.CLBLM_FAN2 always
CLBLM_R.CLBLM_M_DI.CLBLM_FAN3 always
CLBLM_R.CLBLM_M_WE.CLBLM_FAN4 always
CLBLM_R.CLBLM_M_CI.CLBLM_FAN5 always
CLBLM_R.CLBLM_L_CE.CLBLM_FAN6 always
CLBLM_R.CLBLM_M_CE.CLBLM_FAN7 always
CLBLM_R.CLBLM_L_A3.CLBLM_IMUX0 always
CLBLM_R.CLBLM_L_A2.CLBLM_IMUX3 always
CLBLM_R.CLBLM_L_A6.CLBLM_IMUX5 always
CLBLM_R.CLBLM_L_A1.CLBLM_IMUX6 always
CLBLM_R.CLBLM_L_A5.CLBLM_IMUX9 always
CLBLM_R.CLBLM_L_A4.CLBLM_IMUX10 always
CLBLM_R.CLBLM_M_A3.CLBLM_IMUX1 always
CLBLM_R.CLBLM_M_A2.CLBLM_IMUX2 always
CLBLM_R.CLBLM_M_A6.CLBLM_IMUX4 always
CLBLM_R.CLBLM_M_A1.CLBLM_IMUX7 always
CLBLM_R.CLBLM_M_A5.CLBLM_IMUX8 always
CLBLM_R.CLBLM_M_A4.CLBLM_IMUX11 always
CLBLM_R.CLBLM_M_B6.CLBLM_IMUX12 always
CLBLM_R.CLBLM_M_B1.CLBLM_IMUX15 always
CLBLM_R.CLBLM_M_B3.CLBLM_IMUX17 always
CLBLM_R.CLBLM_M_B2.CLBLM_IMUX18 always
CLBLM_R.CLBLM_M_B5.CLBLM_IMUX24 always
CLBLM_R.CLBLM_M_B4.CLBLM_IMUX27 always
CLBLM_R.CLBLM_L_B6.CLBLM_IMUX13 always
CLBLM_R.CLBLM_L_B1.CLBLM_IMUX14 always
CLBLM_R.CLBLM_L_B3.CLBLM_IMUX16 always
CLBLM_R.CLBLM_L_B2.CLBLM_IMUX19 always
CLBLM_R.CLBLM_L_B5.CLBLM_IMUX25 always
CLBLM_R.CLBLM_L_B4.CLBLM_IMUX26 always
CLBLM_R.CLBLM_L_C2.CLBLM_IMUX20 always
CLBLM_R.CLBLM_L_C4.CLBLM_IMUX21 always
CLBLM_R.CLBLM_L_C3.CLBLM_IMUX23 always
CLBLM_R.CLBLM_L_C5.CLBLM_IMUX30 always
CLBLM_R.CLBLM_L_C1.CLBLM_IMUX33 always
CLBLM_R.CLBLM_L_C6.CLBLM_IMUX34 always
CLBLM_R.CLBLM_M_C3.CLBLM_IMUX22 always
CLBLM_R.CLBLM_M_C4.CLBLM_IMUX28 always
CLBLM_R.CLBLM_M_C2.CLBLM_IMUX29 always
CLBLM_R.CLBLM_M_C5.CLBLM_IMUX31 always
CLBLM_R.CLBLM_M_C1.CLBLM_IMUX32 always
CLBLM_R.CLBLM_M_C6.CLBLM_IMUX35 always
CLBLM_R.CLBLM_L_D2.CLBLM_IMUX36 always
CLBLM_R.CLBLM_L_D4.CLBLM_IMUX37 always
CLBLM_R.CLBLM_L_D3.CLBLM_IMUX39 always
CLBLM_R.CLBLM_L_D1.CLBLM_IMUX41 always
CLBLM_R.CLBLM_L_D6.CLBLM_IMUX42 always
CLBLM_R.CLBLM_L_D5.CLBLM_IMUX46 always
CLBLM_R.CLBLM_M_D3.CLBLM_IMUX38 always
CLBLM_R.CLBLM_M_D1.CLBLM_IMUX40 always
CLBLM_R.CLBLM_M_D6.CLBLM_IMUX43 always
CLBLM_R.CLBLM_M_D4.CLBLM_IMUX44 always
CLBLM_R.CLBLM_M_D2.CLBLM_IMUX45 always
CLBLM_R.CLBLM_M_D5.CLBLM_IMUX47 always
CLBLM_R.CLBLM_LOGIC_OUTS8.CLBLM_L_A always
CLBLM_R.CLBLM_L_AMUX.CLBLM_L_A hint
CLBLM_R.CLBLM_L_A.CLBLM_L_A1 hint
CLBLM_R.CLBLM_L_A.CLBLM_L_A2 hint
CLBLM_R.CLBLM_L_A.CLBLM_L_A3 hint
CLBLM_R.CLBLM_L_A.CLBLM_L_A4 hint
CLBLM_R.CLBLM_L_A.CLBLM_L_A5 hint
CLBLM_R.CLBLM_L_A.CLBLM_L_A6 hint
CLBLM_R.CLBLM_LOGIC_OUTS16.CLBLM_L_AMUX always
CLBLM_R.CLBLM_LOGIC_OUTS0.CLBLM_L_AQ always
CLBLM_R.CLBLM_LOGIC_OUTS9.CLBLM_L_B always
CLBLM_R.CLBLM_L_BMUX.CLBLM_L_B hint
CLBLM_R.CLBLM_L_B.CLBLM_L_B1 hint
CLBLM_R.CLBLM_L_B.CLBLM_L_B2 hint
CLBLM_R.CLBLM_L_B.CLBLM_L_B3 hint
CLBLM_R.CLBLM_L_B.CLBLM_L_B4 hint
CLBLM_R.CLBLM_L_B.CLBLM_L_B5 hint
CLBLM_R.CLBLM_L_B.CLBLM_L_B6 hint
CLBLM_R.CLBLM_LOGIC_OUTS17.CLBLM_L_BMUX always
CLBLM_R.CLBLM_LOGIC_OUTS1.CLBLM_L_BQ always
CLBLM_R.CLBLM_LOGIC_OUTS10.CLBLM_L_C always
CLBLM_R.CLBLM_L_CMUX.CLBLM_L_C hint
CLBLM_R.CLBLM_L_C.CLBLM_L_C1 hint
CLBLM_R.CLBLM_L_C.CLBLM_L_C2 hint
CLBLM_R.CLBLM_L_C.CLBLM_L_C3 hint
CLBLM_R.CLBLM_L_C.CLBLM_L_C4 hint
CLBLM_R.CLBLM_L_C.CLBLM_L_C5 hint
CLBLM_R.CLBLM_L_C.CLBLM_L_C6 hint
CLBLM_R.CLBLM_LOGIC_OUTS18.CLBLM_L_CMUX always
CLBLM_R.CLBLM_L_COUT_N.CLBLM_L_COUT always
CLBLM_R.CLBLM_L_DMUX.CLBLM_L_COUT hint
CLBLM_R.CLBLM_LOGIC_OUTS2.CLBLM_L_CQ always
CLBLM_R.CLBLM_LOGIC_OUTS11.CLBLM_L_D always
CLBLM_R.CLBLM_L_DMUX.CLBLM_L_D hint
CLBLM_R.CLBLM_L_D.CLBLM_L_D1 hint
CLBLM_R.CLBLM_L_D.CLBLM_L_D2 hint
CLBLM_R.CLBLM_L_D.CLBLM_L_D3 hint
CLBLM_R.CLBLM_L_D.CLBLM_L_D4 hint
CLBLM_R.CLBLM_L_D.CLBLM_L_D5 hint
CLBLM_R.CLBLM_L_D.CLBLM_L_D6 hint
CLBLM_R.CLBLM_LOGIC_OUTS19.CLBLM_L_DMUX always
CLBLM_R.CLBLM_LOGIC_OUTS3.CLBLM_L_DQ always
CLBLM_R.CLBLM_LOGIC_OUTS12.CLBLM_M_A always
CLBLM_R.CLBLM_M_AMUX.CLBLM_M_A hint
CLBLM_R.CLBLM_M_A.CLBLM_M_A1 hint
CLBLM_R.CLBLM_M_A.CLBLM_M_A2 hint
CLBLM_R.CLBLM_M_A.CLBLM_M_A3 hint
CLBLM_R.CLBLM_M_A.CLBLM_M_A4 hint
CLBLM_R.CLBLM_M_A.CLBLM_M_A5 hint
CLBLM_R.CLBLM_M_A.CLBLM_M_A6 hint
CLBLM_R.CLBLM_LOGIC_OUTS20.CLBLM_M_AMUX always
CLBLM_R.CLBLM_LOGIC_OUTS4.CLBLM_M_AQ always
CLBLM_R.CLBLM_LOGIC_OUTS13.CLBLM_M_B always
CLBLM_R.CLBLM_M_BMUX.CLBLM_M_B hint
CLBLM_R.CLBLM_M_B.CLBLM_M_B1 hint
CLBLM_R.CLBLM_M_B.CLBLM_M_B2 hint
CLBLM_R.CLBLM_M_B.CLBLM_M_B3 hint
CLBLM_R.CLBLM_M_B.CLBLM_M_B4 hint
CLBLM_R.CLBLM_M_B.CLBLM_M_B5 hint
CLBLM_R.CLBLM_M_B.CLBLM_M_B6 hint
CLBLM_R.CLBLM_LOGIC_OUTS21.CLBLM_M_BMUX always
CLBLM_R.CLBLM_LOGIC_OUTS5.CLBLM_M_BQ always
CLBLM_R.CLBLM_LOGIC_OUTS14.CLBLM_M_C always
CLBLM_R.CLBLM_M_CMUX.CLBLM_M_C hint
CLBLM_R.CLBLM_M_C.CLBLM_M_C1 hint
CLBLM_R.CLBLM_M_C.CLBLM_M_C2 hint
CLBLM_R.CLBLM_M_C.CLBLM_M_C3 hint
CLBLM_R.CLBLM_M_C.CLBLM_M_C4 hint
CLBLM_R.CLBLM_M_C.CLBLM_M_C5 hint
CLBLM_R.CLBLM_M_C.CLBLM_M_C6 hint
CLBLM_R.CLBLM_LOGIC_OUTS22.CLBLM_M_CMUX always
CLBLM_R.CLBLM_M_COUT_N.CLBLM_M_COUT always
CLBLM_R.CLBLM_M_DMUX.CLBLM_M_COUT hint
CLBLM_R.CLBLM_LOGIC_OUTS6.CLBLM_M_CQ always
CLBLM_R.CLBLM_LOGIC_OUTS15.CLBLM_M_D always
CLBLM_R.CLBLM_M_DMUX.CLBLM_M_D hint
CLBLM_R.CLBLM_M_D.CLBLM_M_D1 hint
CLBLM_R.CLBLM_M_D.CLBLM_M_D2 hint
CLBLM_R.CLBLM_M_D.CLBLM_M_D3 hint
CLBLM_R.CLBLM_M_D.CLBLM_M_D4 hint
CLBLM_R.CLBLM_M_D.CLBLM_M_D5 hint
CLBLM_R.CLBLM_M_D.CLBLM_M_D6 hint
CLBLM_R.CLBLM_LOGIC_OUTS23.CLBLM_M_DMUX always
CLBLM_R.CLBLM_LOGIC_OUTS7.CLBLM_M_DQ always

8
kintex7/ppips_hclk_l.db Normal file
View File

@ -0,0 +1,8 @@
HCLK.HCLK_CK_INOUT_L0.HCLK_CK_BUFHCLK8 always
HCLK.HCLK_CK_INOUT_L1.HCLK_CK_BUFHCLK9 always
HCLK.HCLK_CK_INOUT_L2.HCLK_CK_BUFHCLK10 always
HCLK.HCLK_CK_INOUT_L3.HCLK_CK_BUFHCLK11 always
HCLK.HCLK_CK_INOUT_L4.HCLK_CK_BUFRCLK0 always
HCLK.HCLK_CK_INOUT_L5.HCLK_CK_BUFRCLK1 always
HCLK.HCLK_CK_INOUT_L6.HCLK_CK_BUFRCLK2 always
HCLK.HCLK_CK_INOUT_L7.HCLK_CK_BUFRCLK3 always

8
kintex7/ppips_hclk_r.db Normal file
View File

@ -0,0 +1,8 @@
HCLK.HCLK_CK_INOUT_R0.HCLK_CK_BUFHCLK0 always
HCLK.HCLK_CK_INOUT_R1.HCLK_CK_BUFHCLK1 always
HCLK.HCLK_CK_INOUT_R2.HCLK_CK_BUFHCLK2 always
HCLK.HCLK_CK_INOUT_R3.HCLK_CK_BUFHCLK3 always
HCLK.HCLK_CK_INOUT_R4.HCLK_CK_BUFHCLK4 always
HCLK.HCLK_CK_INOUT_R5.HCLK_CK_BUFHCLK5 always
HCLK.HCLK_CK_INOUT_R6.HCLK_CK_BUFHCLK6 always
HCLK.HCLK_CK_INOUT_R7.HCLK_CK_BUFHCLK7 always

44
kintex7/ppips_int_l.db Normal file
View File

@ -0,0 +1,44 @@
INT_L.BYP_BOUNCE0.BYP_ALT0 always
INT_L.BYP_BOUNCE1.BYP_ALT1 always
INT_L.BYP_BOUNCE2.BYP_ALT2 always
INT_L.BYP_BOUNCE3.BYP_ALT3 always
INT_L.BYP_BOUNCE4.BYP_ALT4 always
INT_L.BYP_BOUNCE5.BYP_ALT5 always
INT_L.BYP_BOUNCE6.BYP_ALT6 always
INT_L.BYP_BOUNCE7.BYP_ALT7 always
INT_L.BYP_L0.BYP_ALT0 always
INT_L.BYP_L1.BYP_ALT1 always
INT_L.BYP_L2.BYP_ALT2 always
INT_L.BYP_L3.BYP_ALT3 always
INT_L.BYP_L4.BYP_ALT4 always
INT_L.BYP_L5.BYP_ALT5 always
INT_L.BYP_L6.BYP_ALT6 always
INT_L.BYP_L7.BYP_ALT7 always
INT_L.FAN_BOUNCE0.FAN_ALT0 always
INT_L.FAN_BOUNCE1.FAN_ALT1 always
INT_L.FAN_BOUNCE2.FAN_ALT2 always
INT_L.FAN_BOUNCE3.FAN_ALT3 always
INT_L.FAN_BOUNCE4.FAN_ALT4 always
INT_L.FAN_BOUNCE5.FAN_ALT5 always
INT_L.FAN_BOUNCE6.FAN_ALT6 always
INT_L.FAN_BOUNCE7.FAN_ALT7 always
INT_L.FAN_L0.FAN_ALT0 always
INT_L.FAN_L1.FAN_ALT1 always
INT_L.FAN_L2.FAN_ALT2 always
INT_L.FAN_L3.FAN_ALT3 always
INT_L.FAN_L4.FAN_ALT4 always
INT_L.FAN_L5.FAN_ALT5 always
INT_L.FAN_L6.FAN_ALT6 always
INT_L.FAN_L7.FAN_ALT7 always
INT_L.GCLK_L_B10_WEST.GCLK_L_B10 always
INT_L.GCLK_L_B10_EAST.GCLK_L_B10 always
INT_L.GCLK_L_B11_WEST.GCLK_L_B11 always
INT_L.GCLK_L_B11_EAST.GCLK_L_B11 always
INT_L.GCLK_L_B6_WEST.GCLK_L_B6 always
INT_L.GCLK_L_B6_EAST.GCLK_L_B6 always
INT_L.GCLK_L_B7_WEST.GCLK_L_B7 always
INT_L.GCLK_L_B7_EAST.GCLK_L_B7 always
INT_L.GCLK_L_B8_WEST.GCLK_L_B8 always
INT_L.GCLK_L_B8_EAST.GCLK_L_B8 always
INT_L.GCLK_L_B9_WEST.GCLK_L_B9 always
INT_L.GCLK_L_B9_EAST.GCLK_L_B9 always

44
kintex7/ppips_int_r.db Normal file
View File

@ -0,0 +1,44 @@
INT_R.BYP_BOUNCE0.BYP_ALT0 always
INT_R.BYP_BOUNCE1.BYP_ALT1 always
INT_R.BYP_BOUNCE2.BYP_ALT2 always
INT_R.BYP_BOUNCE3.BYP_ALT3 always
INT_R.BYP_BOUNCE4.BYP_ALT4 always
INT_R.BYP_BOUNCE5.BYP_ALT5 always
INT_R.BYP_BOUNCE6.BYP_ALT6 always
INT_R.BYP_BOUNCE7.BYP_ALT7 always
INT_R.BYP0.BYP_ALT0 always
INT_R.BYP1.BYP_ALT1 always
INT_R.BYP2.BYP_ALT2 always
INT_R.BYP3.BYP_ALT3 always
INT_R.BYP4.BYP_ALT4 always
INT_R.BYP5.BYP_ALT5 always
INT_R.BYP6.BYP_ALT6 always
INT_R.BYP7.BYP_ALT7 always
INT_R.FAN_BOUNCE0.FAN_ALT0 always
INT_R.FAN_BOUNCE1.FAN_ALT1 always
INT_R.FAN_BOUNCE2.FAN_ALT2 always
INT_R.FAN_BOUNCE3.FAN_ALT3 always
INT_R.FAN_BOUNCE4.FAN_ALT4 always
INT_R.FAN_BOUNCE5.FAN_ALT5 always
INT_R.FAN_BOUNCE6.FAN_ALT6 always
INT_R.FAN_BOUNCE7.FAN_ALT7 always
INT_R.FAN0.FAN_ALT0 always
INT_R.FAN1.FAN_ALT1 always
INT_R.FAN2.FAN_ALT2 always
INT_R.FAN3.FAN_ALT3 always
INT_R.FAN4.FAN_ALT4 always
INT_R.FAN5.FAN_ALT5 always
INT_R.FAN6.FAN_ALT6 always
INT_R.FAN7.FAN_ALT7 always
INT_R.GCLK_B0_EAST.GCLK_B0 always
INT_R.GCLK_B0_WEST.GCLK_B0 always
INT_R.GCLK_B1_EAST.GCLK_B1 always
INT_R.GCLK_B1_WEST.GCLK_B1 always
INT_R.GCLK_B2_EAST.GCLK_B2 always
INT_R.GCLK_B2_WEST.GCLK_B2 always
INT_R.GCLK_B3_EAST.GCLK_B3 always
INT_R.GCLK_B3_WEST.GCLK_B3 always
INT_R.GCLK_B4_EAST.GCLK_B4 always
INT_R.GCLK_B4_WEST.GCLK_B4 always
INT_R.GCLK_B5_EAST.GCLK_B5 always
INT_R.GCLK_B5_WEST.GCLK_B5 always

0
kintex7/segbits_bram_l.block_ram.db Normal file
View File

192
kintex7/segbits_bram_l.db Normal file
View File

@ -0,0 +1,192 @@
BRAM_L.RAMB18_Y0.INIT_A[0] 27_73
BRAM_L.RAMB18_Y0.INIT_A[10] 27_129
BRAM_L.RAMB18_Y0.INIT_A[11] 27_113
BRAM_L.RAMB18_Y0.INIT_A[12] 27_97
BRAM_L.RAMB18_Y0.INIT_A[1] 27_65
BRAM_L.RAMB18_Y0.INIT_A[13] 27_81
BRAM_L.RAMB18_Y0.INIT_A[14] 27_49
BRAM_L.RAMB18_Y0.INIT_A[15] 27_33
BRAM_L.RAMB18_Y0.INIT_A[16] 27_17
BRAM_L.RAMB18_Y0.INIT_A[17] 27_01
BRAM_L.RAMB18_Y0.INIT_A[2] 27_137
BRAM_L.RAMB18_Y0.INIT_A[3] 27_121
BRAM_L.RAMB18_Y0.INIT_A[4] 27_105
BRAM_L.RAMB18_Y0.INIT_A[5] 27_89
BRAM_L.RAMB18_Y0.INIT_A[6] 27_57
BRAM_L.RAMB18_Y0.INIT_A[7] 27_41
BRAM_L.RAMB18_Y0.INIT_A[8] 27_25
BRAM_L.RAMB18_Y0.INIT_A[9] 27_09
BRAM_L.RAMB18_Y0.INIT_B[0] 27_79
BRAM_L.RAMB18_Y0.INIT_B[10] 27_135
BRAM_L.RAMB18_Y0.INIT_B[11] 27_119
BRAM_L.RAMB18_Y0.INIT_B[12] 27_103
BRAM_L.RAMB18_Y0.INIT_B[1] 27_71
BRAM_L.RAMB18_Y0.INIT_B[13] 27_87
BRAM_L.RAMB18_Y0.INIT_B[14] 27_55
BRAM_L.RAMB18_Y0.INIT_B[15] 27_39
BRAM_L.RAMB18_Y0.INIT_B[16] 27_23
BRAM_L.RAMB18_Y0.INIT_B[17] 27_07
BRAM_L.RAMB18_Y0.INIT_B[2] 27_143
BRAM_L.RAMB18_Y0.INIT_B[3] 27_127
BRAM_L.RAMB18_Y0.INIT_B[4] 27_111
BRAM_L.RAMB18_Y0.INIT_B[5] 27_95
BRAM_L.RAMB18_Y0.INIT_B[6] 27_63
BRAM_L.RAMB18_Y0.INIT_B[7] 27_47
BRAM_L.RAMB18_Y0.INIT_B[8] 27_31
BRAM_L.RAMB18_Y0.INIT_B[9] 27_15
BRAM_L.RAMB18_Y0.READ_WIDTH_A_B0 27_35
BRAM_L.RAMB18_Y0.READ_WIDTH_A_B1 27_36
BRAM_L.RAMB18_Y0.READ_WIDTH_A_B2 27_37
BRAM_L.RAMB18_Y0.READ_WIDTH_B_B0 27_43
BRAM_L.RAMB18_Y0.READ_WIDTH_B_B1 27_44
BRAM_L.RAMB18_Y0.READ_WIDTH_B_B2 27_45
BRAM_L.RAMB18_Y0.SRVAL_A[0] 27_74
BRAM_L.RAMB18_Y0.SRVAL_A[10] 27_130
BRAM_L.RAMB18_Y0.SRVAL_A[11] 27_114
BRAM_L.RAMB18_Y0.SRVAL_A[12] 27_98
BRAM_L.RAMB18_Y0.SRVAL_A[1] 27_66
BRAM_L.RAMB18_Y0.SRVAL_A[13] 27_82
BRAM_L.RAMB18_Y0.SRVAL_A[14] 27_50
BRAM_L.RAMB18_Y0.SRVAL_A[15] 27_34
BRAM_L.RAMB18_Y0.SRVAL_A[16] 27_18
BRAM_L.RAMB18_Y0.SRVAL_A[17] 27_02
BRAM_L.RAMB18_Y0.SRVAL_A[2] 27_138
BRAM_L.RAMB18_Y0.SRVAL_A[3] 27_122
BRAM_L.RAMB18_Y0.SRVAL_A[4] 27_106
BRAM_L.RAMB18_Y0.SRVAL_A[5] 27_90
BRAM_L.RAMB18_Y0.SRVAL_A[6] 27_58
BRAM_L.RAMB18_Y0.SRVAL_A[7] 27_42
BRAM_L.RAMB18_Y0.SRVAL_A[8] 27_26
BRAM_L.RAMB18_Y0.SRVAL_A[9] 27_10
BRAM_L.RAMB18_Y0.SRVAL_B[0] 27_78
BRAM_L.RAMB18_Y0.SRVAL_B[10] 27_134
BRAM_L.RAMB18_Y0.SRVAL_B[11] 27_118
BRAM_L.RAMB18_Y0.SRVAL_B[12] 27_102
BRAM_L.RAMB18_Y0.SRVAL_B[1] 27_70
BRAM_L.RAMB18_Y0.SRVAL_B[13] 27_86
BRAM_L.RAMB18_Y0.SRVAL_B[14] 27_54
BRAM_L.RAMB18_Y0.SRVAL_B[15] 27_38
BRAM_L.RAMB18_Y0.SRVAL_B[16] 27_22
BRAM_L.RAMB18_Y0.SRVAL_B[17] 27_06
BRAM_L.RAMB18_Y0.SRVAL_B[2] 27_142
BRAM_L.RAMB18_Y0.SRVAL_B[3] 27_126
BRAM_L.RAMB18_Y0.SRVAL_B[4] 27_110
BRAM_L.RAMB18_Y0.SRVAL_B[5] 27_94
BRAM_L.RAMB18_Y0.SRVAL_B[6] 27_62
BRAM_L.RAMB18_Y0.SRVAL_B[7] 27_46
BRAM_L.RAMB18_Y0.SRVAL_B[8] 27_30
BRAM_L.RAMB18_Y0.SRVAL_B[9] 27_14
BRAM_L.RAMB18_Y0.WRITE_MODE_A_NO_CHANGE 27_64
BRAM_L.RAMB18_Y0.WRITE_MODE_A_READ_FIRST 27_56
BRAM_L.RAMB18_Y0.WRITE_MODE_B_NO_CHANGE 27_68
BRAM_L.RAMB18_Y0.WRITE_MODE_B_READ_FIRST 27_67
BRAM_L.RAMB18_Y0.WRITE_WIDTH_A_B0 27_51
BRAM_L.RAMB18_Y0.WRITE_WIDTH_A_B1 27_52
BRAM_L.RAMB18_Y0.WRITE_WIDTH_A_B2 27_53
BRAM_L.RAMB18_Y0.WRITE_WIDTH_B_B0 27_59
BRAM_L.RAMB18_Y0.WRITE_WIDTH_B_B1 27_60
BRAM_L.RAMB18_Y0.WRITE_WIDTH_B_B2 27_61
BRAM_L.RAMB18_Y0.ZINV_CLKARDCLK 27_107
BRAM_L.RAMB18_Y0.ZINV_CLKBWRCLK 27_109
BRAM_L.RAMB18_Y0.ZINV_ENARDEN 27_112
BRAM_L.RAMB18_Y0.ZINV_ENBWREN 27_115
BRAM_L.RAMB18_Y0.ZINV_RSTRAMARSTRAM 27_116
BRAM_L.RAMB18_Y0.ZINV_RSTRAMB 27_117
BRAM_L.RAMB18_Y0.ZINV_RSTREGARSTREG 27_120
BRAM_L.RAMB18_Y0.ZINV_RSTREGB 27_123
BRAM_L.RAMB18_Y1.INIT_A[0] 27_249
BRAM_L.RAMB18_Y1.INIT_A[10] 27_305
BRAM_L.RAMB18_Y1.INIT_A[11] 27_289
BRAM_L.RAMB18_Y1.INIT_A[12] 27_273
BRAM_L.RAMB18_Y1.INIT_A[1] 27_241
BRAM_L.RAMB18_Y1.INIT_A[13] 27_257
BRAM_L.RAMB18_Y1.INIT_A[14] 27_225
BRAM_L.RAMB18_Y1.INIT_A[15] 27_209
BRAM_L.RAMB18_Y1.INIT_A[16] 27_193
BRAM_L.RAMB18_Y1.INIT_A[17] 27_177
BRAM_L.RAMB18_Y1.INIT_A[2] 27_313
BRAM_L.RAMB18_Y1.INIT_A[3] 27_297
BRAM_L.RAMB18_Y1.INIT_A[4] 27_281
BRAM_L.RAMB18_Y1.INIT_A[5] 27_265
BRAM_L.RAMB18_Y1.INIT_A[6] 27_233
BRAM_L.RAMB18_Y1.INIT_A[7] 27_217
BRAM_L.RAMB18_Y1.INIT_A[8] 27_201
BRAM_L.RAMB18_Y1.INIT_A[9] 27_185
BRAM_L.RAMB18_Y1.INIT_B[0] 27_255
BRAM_L.RAMB18_Y1.INIT_B[10] 27_311
BRAM_L.RAMB18_Y1.INIT_B[11] 27_295
BRAM_L.RAMB18_Y1.INIT_B[12] 27_279
BRAM_L.RAMB18_Y1.INIT_B[1] 27_247
BRAM_L.RAMB18_Y1.INIT_B[13] 27_263
BRAM_L.RAMB18_Y1.INIT_B[14] 27_231
BRAM_L.RAMB18_Y1.INIT_B[15] 27_215
BRAM_L.RAMB18_Y1.INIT_B[16] 27_199
BRAM_L.RAMB18_Y1.INIT_B[17] 27_183
BRAM_L.RAMB18_Y1.INIT_B[2] 27_319
BRAM_L.RAMB18_Y1.INIT_B[3] 27_303
BRAM_L.RAMB18_Y1.INIT_B[4] 27_287
BRAM_L.RAMB18_Y1.INIT_B[5] 27_271
BRAM_L.RAMB18_Y1.INIT_B[6] 27_239
BRAM_L.RAMB18_Y1.INIT_B[7] 27_223
BRAM_L.RAMB18_Y1.INIT_B[8] 27_207
BRAM_L.RAMB18_Y1.INIT_B[9] 27_191
BRAM_L.RAMB18_Y1.READ_WIDTH_A_B0 27_285
BRAM_L.RAMB18_Y1.READ_WIDTH_A_B1 27_284
BRAM_L.RAMB18_Y1.READ_WIDTH_A_B2 27_283
BRAM_L.RAMB18_Y1.READ_WIDTH_B_B0 27_277
BRAM_L.RAMB18_Y1.READ_WIDTH_B_B1 27_276
BRAM_L.RAMB18_Y1.READ_WIDTH_B_B2 27_275
BRAM_L.RAMB18_Y1.SRVAL_A[0] 27_250
BRAM_L.RAMB18_Y1.SRVAL_A[10] 27_306
BRAM_L.RAMB18_Y1.SRVAL_A[11] 27_290
BRAM_L.RAMB18_Y1.SRVAL_A[12] 27_274
BRAM_L.RAMB18_Y1.SRVAL_A[1] 27_242
BRAM_L.RAMB18_Y1.SRVAL_A[13] 27_258
BRAM_L.RAMB18_Y1.SRVAL_A[14] 27_226
BRAM_L.RAMB18_Y1.SRVAL_A[15] 27_210
BRAM_L.RAMB18_Y1.SRVAL_A[16] 27_194
BRAM_L.RAMB18_Y1.SRVAL_A[17] 27_178
BRAM_L.RAMB18_Y1.SRVAL_A[2] 27_314
BRAM_L.RAMB18_Y1.SRVAL_A[3] 27_298
BRAM_L.RAMB18_Y1.SRVAL_A[4] 27_282
BRAM_L.RAMB18_Y1.SRVAL_A[5] 27_266
BRAM_L.RAMB18_Y1.SRVAL_A[6] 27_234
BRAM_L.RAMB18_Y1.SRVAL_A[7] 27_218
BRAM_L.RAMB18_Y1.SRVAL_A[8] 27_202
BRAM_L.RAMB18_Y1.SRVAL_A[9] 27_186
BRAM_L.RAMB18_Y1.SRVAL_B[0] 27_254
BRAM_L.RAMB18_Y1.SRVAL_B[10] 27_310
BRAM_L.RAMB18_Y1.SRVAL_B[11] 27_294
BRAM_L.RAMB18_Y1.SRVAL_B[12] 27_278
BRAM_L.RAMB18_Y1.SRVAL_B[1] 27_246
BRAM_L.RAMB18_Y1.SRVAL_B[13] 27_262
BRAM_L.RAMB18_Y1.SRVAL_B[14] 27_230
BRAM_L.RAMB18_Y1.SRVAL_B[15] 27_214
BRAM_L.RAMB18_Y1.SRVAL_B[16] 27_198
BRAM_L.RAMB18_Y1.SRVAL_B[17] 27_182
BRAM_L.RAMB18_Y1.SRVAL_B[2] 27_318
BRAM_L.RAMB18_Y1.SRVAL_B[3] 27_302
BRAM_L.RAMB18_Y1.SRVAL_B[4] 27_286
BRAM_L.RAMB18_Y1.SRVAL_B[5] 27_270
BRAM_L.RAMB18_Y1.SRVAL_B[6] 27_238
BRAM_L.RAMB18_Y1.SRVAL_B[7] 27_222
BRAM_L.RAMB18_Y1.SRVAL_B[8] 27_206
BRAM_L.RAMB18_Y1.SRVAL_B[9] 27_190
BRAM_L.RAMB18_Y1.WRITE_MODE_A_NO_CHANGE 27_256
BRAM_L.RAMB18_Y1.WRITE_MODE_A_READ_FIRST 27_264
BRAM_L.RAMB18_Y1.WRITE_MODE_B_NO_CHANGE 27_252
BRAM_L.RAMB18_Y1.WRITE_MODE_B_READ_FIRST 27_253
BRAM_L.RAMB18_Y1.WRITE_WIDTH_A_B0 27_269
BRAM_L.RAMB18_Y1.WRITE_WIDTH_A_B1 27_268
BRAM_L.RAMB18_Y1.WRITE_WIDTH_A_B2 27_267
BRAM_L.RAMB18_Y1.WRITE_WIDTH_B_B0 27_261
BRAM_L.RAMB18_Y1.WRITE_WIDTH_B_B1 27_260
BRAM_L.RAMB18_Y1.WRITE_WIDTH_B_B2 27_259
BRAM_L.RAMB18_Y1.ZINV_CLKARDCLK 27_213
BRAM_L.RAMB18_Y1.ZINV_CLKBWRCLK 27_211
BRAM_L.RAMB18_Y1.ZINV_ENARDEN 27_208
BRAM_L.RAMB18_Y1.ZINV_ENBWREN 27_205
BRAM_L.RAMB18_Y1.ZINV_RSTRAMARSTRAM 27_204
BRAM_L.RAMB18_Y1.ZINV_RSTRAMB 27_203
BRAM_L.RAMB18_Y1.ZINV_RSTREGARSTREG 27_200
BRAM_L.RAMB18_Y1.ZINV_RSTREGB 27_197

0
kintex7/segbits_bram_r.block_ram.db Normal file
View File

192
kintex7/segbits_bram_r.db Normal file
View File

@ -0,0 +1,192 @@
BRAM_R.RAMB18_Y0.INIT_A[0] 27_73
BRAM_R.RAMB18_Y0.INIT_A[10] 27_129
BRAM_R.RAMB18_Y0.INIT_A[11] 27_113
BRAM_R.RAMB18_Y0.INIT_A[12] 27_97
BRAM_R.RAMB18_Y0.INIT_A[1] 27_65
BRAM_R.RAMB18_Y0.INIT_A[13] 27_81
BRAM_R.RAMB18_Y0.INIT_A[14] 27_49
BRAM_R.RAMB18_Y0.INIT_A[15] 27_33
BRAM_R.RAMB18_Y0.INIT_A[16] 27_17
BRAM_R.RAMB18_Y0.INIT_A[17] 27_01
BRAM_R.RAMB18_Y0.INIT_A[2] 27_137
BRAM_R.RAMB18_Y0.INIT_A[3] 27_121
BRAM_R.RAMB18_Y0.INIT_A[4] 27_105
BRAM_R.RAMB18_Y0.INIT_A[5] 27_89
BRAM_R.RAMB18_Y0.INIT_A[6] 27_57
BRAM_R.RAMB18_Y0.INIT_A[7] 27_41
BRAM_R.RAMB18_Y0.INIT_A[8] 27_25
BRAM_R.RAMB18_Y0.INIT_A[9] 27_09
BRAM_R.RAMB18_Y0.INIT_B[0] 27_79
BRAM_R.RAMB18_Y0.INIT_B[10] 27_135
BRAM_R.RAMB18_Y0.INIT_B[11] 27_119
BRAM_R.RAMB18_Y0.INIT_B[12] 27_103
BRAM_R.RAMB18_Y0.INIT_B[1] 27_71
BRAM_R.RAMB18_Y0.INIT_B[13] 27_87
BRAM_R.RAMB18_Y0.INIT_B[14] 27_55
BRAM_R.RAMB18_Y0.INIT_B[15] 27_39
BRAM_R.RAMB18_Y0.INIT_B[16] 27_23
BRAM_R.RAMB18_Y0.INIT_B[17] 27_07
BRAM_R.RAMB18_Y0.INIT_B[2] 27_143
BRAM_R.RAMB18_Y0.INIT_B[3] 27_127
BRAM_R.RAMB18_Y0.INIT_B[4] 27_111
BRAM_R.RAMB18_Y0.INIT_B[5] 27_95
BRAM_R.RAMB18_Y0.INIT_B[6] 27_63
BRAM_R.RAMB18_Y0.INIT_B[7] 27_47
BRAM_R.RAMB18_Y0.INIT_B[8] 27_31
BRAM_R.RAMB18_Y0.INIT_B[9] 27_15
BRAM_R.RAMB18_Y0.READ_WIDTH_A_B0 27_35
BRAM_R.RAMB18_Y0.READ_WIDTH_A_B1 27_36
BRAM_R.RAMB18_Y0.READ_WIDTH_A_B2 27_37
BRAM_R.RAMB18_Y0.READ_WIDTH_B_B0 27_43
BRAM_R.RAMB18_Y0.READ_WIDTH_B_B1 27_44
BRAM_R.RAMB18_Y0.READ_WIDTH_B_B2 27_45
BRAM_R.RAMB18_Y0.SRVAL_A[0] 27_74
BRAM_R.RAMB18_Y0.SRVAL_A[10] 27_130
BRAM_R.RAMB18_Y0.SRVAL_A[11] 27_114
BRAM_R.RAMB18_Y0.SRVAL_A[12] 27_98
BRAM_R.RAMB18_Y0.SRVAL_A[1] 27_66
BRAM_R.RAMB18_Y0.SRVAL_A[13] 27_82
BRAM_R.RAMB18_Y0.SRVAL_A[14] 27_50
BRAM_R.RAMB18_Y0.SRVAL_A[15] 27_34
BRAM_R.RAMB18_Y0.SRVAL_A[16] 27_18
BRAM_R.RAMB18_Y0.SRVAL_A[17] 27_02
BRAM_R.RAMB18_Y0.SRVAL_A[2] 27_138
BRAM_R.RAMB18_Y0.SRVAL_A[3] 27_122
BRAM_R.RAMB18_Y0.SRVAL_A[4] 27_106
BRAM_R.RAMB18_Y0.SRVAL_A[5] 27_90
BRAM_R.RAMB18_Y0.SRVAL_A[6] 27_58
BRAM_R.RAMB18_Y0.SRVAL_A[7] 27_42
BRAM_R.RAMB18_Y0.SRVAL_A[8] 27_26
BRAM_R.RAMB18_Y0.SRVAL_A[9] 27_10
BRAM_R.RAMB18_Y0.SRVAL_B[0] 27_78
BRAM_R.RAMB18_Y0.SRVAL_B[10] 27_134
BRAM_R.RAMB18_Y0.SRVAL_B[11] 27_118
BRAM_R.RAMB18_Y0.SRVAL_B[12] 27_102
BRAM_R.RAMB18_Y0.SRVAL_B[1] 27_70
BRAM_R.RAMB18_Y0.SRVAL_B[13] 27_86
BRAM_R.RAMB18_Y0.SRVAL_B[14] 27_54
BRAM_R.RAMB18_Y0.SRVAL_B[15] 27_38
BRAM_R.RAMB18_Y0.SRVAL_B[16] 27_22
BRAM_R.RAMB18_Y0.SRVAL_B[17] 27_06
BRAM_R.RAMB18_Y0.SRVAL_B[2] 27_142
BRAM_R.RAMB18_Y0.SRVAL_B[3] 27_126
BRAM_R.RAMB18_Y0.SRVAL_B[4] 27_110
BRAM_R.RAMB18_Y0.SRVAL_B[5] 27_94
BRAM_R.RAMB18_Y0.SRVAL_B[6] 27_62
BRAM_R.RAMB18_Y0.SRVAL_B[7] 27_46
BRAM_R.RAMB18_Y0.SRVAL_B[8] 27_30
BRAM_R.RAMB18_Y0.SRVAL_B[9] 27_14
BRAM_R.RAMB18_Y0.WRITE_MODE_A_NO_CHANGE 27_64
BRAM_R.RAMB18_Y0.WRITE_MODE_A_READ_FIRST 27_56
BRAM_R.RAMB18_Y0.WRITE_MODE_B_NO_CHANGE 27_68
BRAM_R.RAMB18_Y0.WRITE_MODE_B_READ_FIRST 27_67
BRAM_R.RAMB18_Y0.WRITE_WIDTH_A_B0 27_51
BRAM_R.RAMB18_Y0.WRITE_WIDTH_A_B1 27_52
BRAM_R.RAMB18_Y0.WRITE_WIDTH_A_B2 27_53
BRAM_R.RAMB18_Y0.WRITE_WIDTH_B_B0 27_59
BRAM_R.RAMB18_Y0.WRITE_WIDTH_B_B1 27_60
BRAM_R.RAMB18_Y0.WRITE_WIDTH_B_B2 27_61
BRAM_R.RAMB18_Y0.ZINV_CLKARDCLK 27_107
BRAM_R.RAMB18_Y0.ZINV_CLKBWRCLK 27_109
BRAM_R.RAMB18_Y0.ZINV_ENARDEN 27_112
BRAM_R.RAMB18_Y0.ZINV_ENBWREN 27_115
BRAM_R.RAMB18_Y0.ZINV_RSTRAMARSTRAM 27_116
BRAM_R.RAMB18_Y0.ZINV_RSTRAMB 27_117
BRAM_R.RAMB18_Y0.ZINV_RSTREGARSTREG 27_120
BRAM_R.RAMB18_Y0.ZINV_RSTREGB 27_123
BRAM_R.RAMB18_Y1.INIT_A[0] 27_249
BRAM_R.RAMB18_Y1.INIT_A[10] 27_305
BRAM_R.RAMB18_Y1.INIT_A[11] 27_289
BRAM_R.RAMB18_Y1.INIT_A[12] 27_273
BRAM_R.RAMB18_Y1.INIT_A[1] 27_241
BRAM_R.RAMB18_Y1.INIT_A[13] 27_257
BRAM_R.RAMB18_Y1.INIT_A[14] 27_225
BRAM_R.RAMB18_Y1.INIT_A[15] 27_209
BRAM_R.RAMB18_Y1.INIT_A[16] 27_193
BRAM_R.RAMB18_Y1.INIT_A[17] 27_177
BRAM_R.RAMB18_Y1.INIT_A[2] 27_313
BRAM_R.RAMB18_Y1.INIT_A[3] 27_297
BRAM_R.RAMB18_Y1.INIT_A[4] 27_281
BRAM_R.RAMB18_Y1.INIT_A[5] 27_265
BRAM_R.RAMB18_Y1.INIT_A[6] 27_233
BRAM_R.RAMB18_Y1.INIT_A[7] 27_217
BRAM_R.RAMB18_Y1.INIT_A[8] 27_201
BRAM_R.RAMB18_Y1.INIT_A[9] 27_185
BRAM_R.RAMB18_Y1.INIT_B[0] 27_255
BRAM_R.RAMB18_Y1.INIT_B[10] 27_311
BRAM_R.RAMB18_Y1.INIT_B[11] 27_295
BRAM_R.RAMB18_Y1.INIT_B[12] 27_279
BRAM_R.RAMB18_Y1.INIT_B[1] 27_247
BRAM_R.RAMB18_Y1.INIT_B[13] 27_263
BRAM_R.RAMB18_Y1.INIT_B[14] 27_231
BRAM_R.RAMB18_Y1.INIT_B[15] 27_215
BRAM_R.RAMB18_Y1.INIT_B[16] 27_199
BRAM_R.RAMB18_Y1.INIT_B[17] 27_183
BRAM_R.RAMB18_Y1.INIT_B[2] 27_319
BRAM_R.RAMB18_Y1.INIT_B[3] 27_303
BRAM_R.RAMB18_Y1.INIT_B[4] 27_287
BRAM_R.RAMB18_Y1.INIT_B[5] 27_271
BRAM_R.RAMB18_Y1.INIT_B[6] 27_239
BRAM_R.RAMB18_Y1.INIT_B[7] 27_223
BRAM_R.RAMB18_Y1.INIT_B[8] 27_207
BRAM_R.RAMB18_Y1.INIT_B[9] 27_191
BRAM_R.RAMB18_Y1.READ_WIDTH_A_B0 27_285
BRAM_R.RAMB18_Y1.READ_WIDTH_A_B1 27_284
BRAM_R.RAMB18_Y1.READ_WIDTH_A_B2 27_283
BRAM_R.RAMB18_Y1.READ_WIDTH_B_B0 27_277
BRAM_R.RAMB18_Y1.READ_WIDTH_B_B1 27_276
BRAM_R.RAMB18_Y1.READ_WIDTH_B_B2 27_275
BRAM_R.RAMB18_Y1.SRVAL_A[0] 27_250
BRAM_R.RAMB18_Y1.SRVAL_A[10] 27_306
BRAM_R.RAMB18_Y1.SRVAL_A[11] 27_290
BRAM_R.RAMB18_Y1.SRVAL_A[12] 27_274
BRAM_R.RAMB18_Y1.SRVAL_A[1] 27_242
BRAM_R.RAMB18_Y1.SRVAL_A[13] 27_258
BRAM_R.RAMB18_Y1.SRVAL_A[14] 27_226
BRAM_R.RAMB18_Y1.SRVAL_A[15] 27_210
BRAM_R.RAMB18_Y1.SRVAL_A[16] 27_194
BRAM_R.RAMB18_Y1.SRVAL_A[17] 27_178
BRAM_R.RAMB18_Y1.SRVAL_A[2] 27_314
BRAM_R.RAMB18_Y1.SRVAL_A[3] 27_298
BRAM_R.RAMB18_Y1.SRVAL_A[4] 27_282
BRAM_R.RAMB18_Y1.SRVAL_A[5] 27_266
BRAM_R.RAMB18_Y1.SRVAL_A[6] 27_234
BRAM_R.RAMB18_Y1.SRVAL_A[7] 27_218
BRAM_R.RAMB18_Y1.SRVAL_A[8] 27_202
BRAM_R.RAMB18_Y1.SRVAL_A[9] 27_186
BRAM_R.RAMB18_Y1.SRVAL_B[0] 27_254
BRAM_R.RAMB18_Y1.SRVAL_B[10] 27_310
BRAM_R.RAMB18_Y1.SRVAL_B[11] 27_294
BRAM_R.RAMB18_Y1.SRVAL_B[12] 27_278
BRAM_R.RAMB18_Y1.SRVAL_B[1] 27_246
BRAM_R.RAMB18_Y1.SRVAL_B[13] 27_262
BRAM_R.RAMB18_Y1.SRVAL_B[14] 27_230
BRAM_R.RAMB18_Y1.SRVAL_B[15] 27_214
BRAM_R.RAMB18_Y1.SRVAL_B[16] 27_198
BRAM_R.RAMB18_Y1.SRVAL_B[17] 27_182
BRAM_R.RAMB18_Y1.SRVAL_B[2] 27_318
BRAM_R.RAMB18_Y1.SRVAL_B[3] 27_302
BRAM_R.RAMB18_Y1.SRVAL_B[4] 27_286
BRAM_R.RAMB18_Y1.SRVAL_B[5] 27_270
BRAM_R.RAMB18_Y1.SRVAL_B[6] 27_238
BRAM_R.RAMB18_Y1.SRVAL_B[7] 27_222
BRAM_R.RAMB18_Y1.SRVAL_B[8] 27_206
BRAM_R.RAMB18_Y1.SRVAL_B[9] 27_190
BRAM_R.RAMB18_Y1.WRITE_MODE_A_NO_CHANGE 27_256
BRAM_R.RAMB18_Y1.WRITE_MODE_A_READ_FIRST 27_264
BRAM_R.RAMB18_Y1.WRITE_MODE_B_NO_CHANGE 27_252
BRAM_R.RAMB18_Y1.WRITE_MODE_B_READ_FIRST 27_253
BRAM_R.RAMB18_Y1.WRITE_WIDTH_A_B0 27_269
BRAM_R.RAMB18_Y1.WRITE_WIDTH_A_B1 27_268
BRAM_R.RAMB18_Y1.WRITE_WIDTH_A_B2 27_267
BRAM_R.RAMB18_Y1.WRITE_WIDTH_B_B0 27_261
BRAM_R.RAMB18_Y1.WRITE_WIDTH_B_B1 27_260
BRAM_R.RAMB18_Y1.WRITE_WIDTH_B_B2 27_259
BRAM_R.RAMB18_Y1.ZINV_CLKARDCLK 27_213
BRAM_R.RAMB18_Y1.ZINV_CLKBWRCLK 27_211
BRAM_R.RAMB18_Y1.ZINV_ENARDEN 27_208
BRAM_R.RAMB18_Y1.ZINV_ENBWREN 27_205
BRAM_R.RAMB18_Y1.ZINV_RSTRAMARSTRAM 27_204
BRAM_R.RAMB18_Y1.ZINV_RSTRAMB 27_203
BRAM_R.RAMB18_Y1.ZINV_RSTREGARSTREG 27_200
BRAM_R.RAMB18_Y1.ZINV_RSTREGB 27_197

121
kintex7/segbits_clbll_l.db
View File

@ -1,7 +1,15 @@
CLBLL_L.SLICEL_X0.A5FF.ZINI 31_06
CLBLL_L.SLICEL_X0.A5FF.ZRST 01_07
CLBLL_L.SLICEL_X0.A5FFMUX.IN_A 30_09
CLBLL_L.SLICEL_X0.A5FFMUX.IN_B 30_10
CLBLL_L.SLICEL_X0.AFF.ZINI 31_03
CLBLL_L.SLICEL_X0.AFF.ZRST 30_12
CLBLL_L.SLICEL_X0.AFFMUX.AX !30_00 !30_02 !30_03 30_01
CLBLL_L.SLICEL_X0.AFFMUX.CY !30_01 !30_03 30_00 30_02
CLBLL_L.SLICEL_X0.AFFMUX.F7 !30_02 !30_03 30_00 30_01
CLBLL_L.SLICEL_X0.AFFMUX.O5 !30_01 !30_02 30_00 30_03
CLBLL_L.SLICEL_X0.AFFMUX.O6 !30_00 !30_01 !30_02 30_03
CLBLL_L.SLICEL_X0.AFFMUX.XOR !30_00 !30_01 !30_03 30_02
CLBLL_L.SLICEL_X0.ALUT.INIT[00] 32_15
CLBLL_L.SLICEL_X0.ALUT.INIT[01] 33_15
CLBLL_L.SLICEL_X0.ALUT.INIT[02] 32_14
@ -66,10 +74,26 @@ CLBLL_L.SLICEL_X0.ALUT.INIT[60] 35_01
CLBLL_L.SLICEL_X0.ALUT.INIT[61] 34_01
CLBLL_L.SLICEL_X0.ALUT.INIT[62] 35_00
CLBLL_L.SLICEL_X0.ALUT.INIT[63] 34_00
CLBLL_L.SLICEL_X0.ALUT.RAM 31_16
CLBLL_L.SLICEL_X0.ALUT.SMALL 00_04
CLBLL_L.SLICEL_X0.ALUT.SRL 30_16
CLBLL_L.SLICEL_X0.AOUTMUX.A5Q !30_06 !30_08 !30_11 30_07
CLBLL_L.SLICEL_X0.AOUTMUX.CY !30_07 !30_11 30_06 30_08
CLBLL_L.SLICEL_X0.AOUTMUX.F7 !30_08 !30_11 30_06 30_07
CLBLL_L.SLICEL_X0.AOUTMUX.O5 !30_07 !30_08 30_06 30_11
CLBLL_L.SLICEL_X0.AOUTMUX.XOR !30_06 !30_07 !30_11 30_08
CLBLL_L.SLICEL_X0.B5FF.ZINI 31_22
CLBLL_L.SLICEL_X0.B5FF.ZRST 01_19
CLBLL_L.SLICEL_X0.B5FFMUX.IN_A 30_19
CLBLL_L.SLICEL_X0.B5FFMUX.IN_B 30_18
CLBLL_L.SLICEL_X0.BFF.ZINI 31_28
CLBLL_L.SLICEL_X0.BFF.ZRST 30_30
CLBLL_L.SLICEL_X0.BFFMUX.BX !30_24 !30_25 !30_27 30_26
CLBLL_L.SLICEL_X0.BFFMUX.CY !30_24 !30_26 30_25 30_27
CLBLL_L.SLICEL_X0.BFFMUX.F8 !30_24 !30_25 30_26 30_27
CLBLL_L.SLICEL_X0.BFFMUX.O5 !30_25 !30_26 30_24 30_27
CLBLL_L.SLICEL_X0.BFFMUX.O6 !30_25 !30_26 !30_27 30_24
CLBLL_L.SLICEL_X0.BFFMUX.XOR !30_24 !30_26 !30_27 30_25
CLBLL_L.SLICEL_X0.BLUT.INIT[00] 32_31
CLBLL_L.SLICEL_X0.BLUT.INIT[01] 33_31
CLBLL_L.SLICEL_X0.BLUT.INIT[02] 32_30
@ -134,15 +158,34 @@ CLBLL_L.SLICEL_X0.BLUT.INIT[60] 35_17
CLBLL_L.SLICEL_X0.BLUT.INIT[61] 34_17
CLBLL_L.SLICEL_X0.BLUT.INIT[62] 35_16
CLBLL_L.SLICEL_X0.BLUT.INIT[63] 34_16
CLBLL_L.SLICEL_X0.BLUT.RAM 31_17
CLBLL_L.SLICEL_X0.BLUT.SMALL 00_24
CLBLL_L.SLICEL_X0.BLUT.SRL 30_17
CLBLL_L.SLICEL_X0.BOUTMUX.B5Q !30_20 !30_21 !30_22 30_23
CLBLL_L.SLICEL_X0.BOUTMUX.CY !30_20 !30_23 30_21 30_22
CLBLL_L.SLICEL_X0.BOUTMUX.F8 !30_20 !30_21 30_22 30_23
CLBLL_L.SLICEL_X0.BOUTMUX.O5 !30_21 !30_23 30_20 30_22
CLBLL_L.SLICEL_X0.BOUTMUX.XOR !30_20 !30_22 !30_23 30_21
CLBLL_L.SLICEL_X0.C5FF.ZINI 31_41
CLBLL_L.SLICEL_X0.C5FF.ZRST 01_47
CLBLL_L.SLICEL_X0.C5FFMUX.IN_A 31_45
CLBLL_L.SLICEL_X0.C5FFMUX.IN_B 30_39
CLBLL_L.SLICEL_X0.CARRY4.ACY0 !30_00 !30_02 !30_03 30_01 30_12 30_15 31_03
CLBLL_L.SLICEL_X0.CARRY4.ACY0 30_15
CLBLL_L.SLICEL_X0.CARRY4.BCY0 !30_24 !30_25 !30_27 01_15 30_26 30_30 31_28
CLBLL_L.SLICEL_X0.CARRY4.BCY0 01_15
CLBLL_L.SLICEL_X0.CARRY4.CCY0 !30_35 !30_37 !30_38 30_33 30_36 30_48 31_33
CLBLL_L.SLICEL_X0.CARRY4.CCY0 30_48
CLBLL_L.SLICEL_X0.CARRY4.DCY0 30_49
CLBLL_L.SLICEL_X0.CEUSEDMUX 01_39
CLBLL_L.SLICEL_X0.CFF.ZINI 31_33
CLBLL_L.SLICEL_X0.CFF.ZRST 30_33
CLBLL_L.SLICEL_X0.CFFMUX.CX !30_35 !30_37 !30_38 30_36
CLBLL_L.SLICEL_X0.CFFMUX.CY !30_36 !30_38 30_35 30_37
CLBLL_L.SLICEL_X0.CFFMUX.F7 !30_37 !30_38 30_35 30_36
CLBLL_L.SLICEL_X0.CFFMUX.O5 !30_36 !30_37 30_35 30_38
CLBLL_L.SLICEL_X0.CFFMUX.O6 !30_35 !30_36 !30_37 30_38
CLBLL_L.SLICEL_X0.CFFMUX.XOR !30_35 !30_36 !30_38 30_37
CLBLL_L.SLICEL_X0.CLKINV 01_51
CLBLL_L.SLICEL_X0.CLUT.INIT[00] 32_47
CLBLL_L.SLICEL_X0.CLUT.INIT[01] 33_47
@ -208,10 +251,25 @@ CLBLL_L.SLICEL_X0.CLUT.INIT[60] 35_33
CLBLL_L.SLICEL_X0.CLUT.INIT[61] 34_33
CLBLL_L.SLICEL_X0.CLUT.INIT[62] 35_32
CLBLL_L.SLICEL_X0.CLUT.INIT[63] 34_32
CLBLL_L.SLICEL_X0.CLUT.RAM 31_46
CLBLL_L.SLICEL_X0.CLUT.SMALL 00_28
CLBLL_L.SLICEL_X0.CLUT.SRL 30_46
CLBLL_L.SLICEL_X0.COUTMUX.C5Q !30_40 !30_44 !30_45 30_43
CLBLL_L.SLICEL_X0.COUTMUX.CY !30_43 !30_45 30_40 30_44
CLBLL_L.SLICEL_X0.COUTMUX.F7 !30_44 !30_45 30_40 30_43
CLBLL_L.SLICEL_X0.COUTMUX.O5 !30_43 !30_44 30_40 30_45
CLBLL_L.SLICEL_X0.COUTMUX.XOR !30_40 !30_43 !30_45 30_44
CLBLL_L.SLICEL_X0.D5FF.ZINI 31_51
CLBLL_L.SLICEL_X0.D5FF.ZRST 01_55
CLBLL_L.SLICEL_X0.D5FFMUX.IN_A 30_55
CLBLL_L.SLICEL_X0.D5FFMUX.IN_B 30_54
CLBLL_L.SLICEL_X0.DFF.ZINI 31_58
CLBLL_L.SLICEL_X0.DFF.ZRST 30_50
CLBLL_L.SLICEL_X0.DFFMUX.CY !30_59 !30_61 30_60 30_62
CLBLL_L.SLICEL_X0.DFFMUX.DX !30_59 !30_60 !30_62 30_61
CLBLL_L.SLICEL_X0.DFFMUX.O5 !30_60 !30_61 30_59 30_62
CLBLL_L.SLICEL_X0.DFFMUX.O6 !30_60 !30_61 !30_62 30_59
CLBLL_L.SLICEL_X0.DFFMUX.XOR !30_59 !30_61 !30_62 30_60
CLBLL_L.SLICEL_X0.DLUT.INIT[00] 32_63
CLBLL_L.SLICEL_X0.DLUT.INIT[01] 33_63
CLBLL_L.SLICEL_X0.DLUT.INIT[02] 32_62
@ -276,16 +334,34 @@ CLBLL_L.SLICEL_X0.DLUT.INIT[60] 35_49
CLBLL_L.SLICEL_X0.DLUT.INIT[61] 34_49
CLBLL_L.SLICEL_X0.DLUT.INIT[62] 35_48
CLBLL_L.SLICEL_X0.DLUT.INIT[63] 34_48
CLBLL_L.SLICEL_X0.DLUT.RAM 31_47
CLBLL_L.SLICEL_X0.DLUT.SMALL 01_59
CLBLL_L.SLICEL_X0.DLUT.SRL 30_47
CLBLL_L.SLICEL_X0.DOUTMUX.CY !30_56 !30_57 30_51 30_52
CLBLL_L.SLICEL_X0.DOUTMUX.D5Q !30_51 !30_52 !30_56 30_57
CLBLL_L.SLICEL_X0.DOUTMUX.O5 !30_51 !30_57 30_52 30_56
CLBLL_L.SLICEL_X0.DOUTMUX.XOR !30_52 !30_56 !30_57 30_51
CLBLL_L.SLICEL_X0.FFSYNC 00_48
CLBLL_L.SLICEL_X0.LATCH 30_32
CLBLL_L.SLICEL_X0.PRECYINIT.1 00_12
CLBLL_L.SLICEL_X0.PRECYINIT.AX 30_14
CLBLL_L.SLICEL_X0.PRECYINIT.CIN 30_13
CLBLL_L.SLICEL_X0.SRUSEDMUX 01_35
CLBLL_L.SLICEL_X0.WA7USED 00_40
CLBLL_L.SLICEL_X0.WA8USED 01_27
CLBLL_L.SLICEL_X0.WEMUX.CE 01_23
CLBLL_L.SLICEL_X1.A5FF.ZINI 31_05
CLBLL_L.SLICEL_X1.A5FF.ZRST 01_03
CLBLL_L.SLICEL_X1.A5FFMUX.IN_A 31_08
CLBLL_L.SLICEL_X1.A5FFMUX.IN_B 31_11
CLBLL_L.SLICEL_X1.AFF.ZINI 31_04
CLBLL_L.SLICEL_X1.AFF.ZRST 31_15
CLBLL_L.SLICEL_X1.AFFMUX.AX !30_04 !31_00 !31_02 31_01
CLBLL_L.SLICEL_X1.AFFMUX.CY !30_04 !31_01 31_00 31_02
CLBLL_L.SLICEL_X1.AFFMUX.F7 !30_04 !31_02 31_00 31_01
CLBLL_L.SLICEL_X1.AFFMUX.O5 !31_01 !31_02 30_04 31_00
CLBLL_L.SLICEL_X1.AFFMUX.O6 !31_00 !31_01 !31_02 30_04
CLBLL_L.SLICEL_X1.AFFMUX.XOR !30_04 !31_00 !31_01 31_02
CLBLL_L.SLICEL_X1.ALUT.INIT[00] 26_15
CLBLL_L.SLICEL_X1.ALUT.INIT[01] 27_15
CLBLL_L.SLICEL_X1.ALUT.INIT[02] 26_14
@ -350,10 +426,23 @@ CLBLL_L.SLICEL_X1.ALUT.INIT[60] 29_01
CLBLL_L.SLICEL_X1.ALUT.INIT[61] 28_01
CLBLL_L.SLICEL_X1.ALUT.INIT[62] 29_00
CLBLL_L.SLICEL_X1.ALUT.INIT[63] 28_00
CLBLL_L.SLICEL_X1.AOUTMUX.A5Q !31_07 !31_09 !31_10 30_05
CLBLL_L.SLICEL_X1.AOUTMUX.CY !30_05 !31_09 31_07 31_10
CLBLL_L.SLICEL_X1.AOUTMUX.F7 !31_07 !31_09 30_05 31_10
CLBLL_L.SLICEL_X1.AOUTMUX.O5 !30_05 !31_07 31_09 31_10
CLBLL_L.SLICEL_X1.AOUTMUX.XOR !30_05 !31_09 !31_10 31_07
CLBLL_L.SLICEL_X1.B5FF.ZINI 31_23
CLBLL_L.SLICEL_X1.B5FF.ZRST 00_16
CLBLL_L.SLICEL_X1.B5FFMUX.IN_A 31_19
CLBLL_L.SLICEL_X1.B5FFMUX.IN_B 31_18
CLBLL_L.SLICEL_X1.BFF.ZINI 31_29
CLBLL_L.SLICEL_X1.BFF.ZRST 31_30
CLBLL_L.SLICEL_X1.BFFMUX.BX !31_24 !31_25 !31_26 31_27
CLBLL_L.SLICEL_X1.BFFMUX.CY !31_24 !31_27 31_25 31_26
CLBLL_L.SLICEL_X1.BFFMUX.F8 !31_24 !31_26 31_25 31_27
CLBLL_L.SLICEL_X1.BFFMUX.O5 !31_26 !31_27 31_24 31_25
CLBLL_L.SLICEL_X1.BFFMUX.O6 !31_25 !31_26 !31_27 31_24
CLBLL_L.SLICEL_X1.BFFMUX.XOR !31_24 !31_25 !31_27 31_26
CLBLL_L.SLICEL_X1.BLUT.INIT[00] 26_31
CLBLL_L.SLICEL_X1.BLUT.INIT[01] 27_31
CLBLL_L.SLICEL_X1.BLUT.INIT[02] 26_30
@ -418,15 +507,31 @@ CLBLL_L.SLICEL_X1.BLUT.INIT[60] 29_17
CLBLL_L.SLICEL_X1.BLUT.INIT[61] 28_17
CLBLL_L.SLICEL_X1.BLUT.INIT[62] 29_16
CLBLL_L.SLICEL_X1.BLUT.INIT[63] 28_16
CLBLL_L.SLICEL_X1.BOUTMUX.B5Q !30_28 !31_20 !31_21 30_29
CLBLL_L.SLICEL_X1.BOUTMUX.CY !30_29 !31_20 30_28 31_21
CLBLL_L.SLICEL_X1.BOUTMUX.F8 !30_28 !31_20 30_29 31_21
CLBLL_L.SLICEL_X1.BOUTMUX.O5 !30_28 !30_29 31_20 31_21
CLBLL_L.SLICEL_X1.BOUTMUX.XOR !30_29 !31_20 !31_21 30_28
CLBLL_L.SLICEL_X1.C5FF.ZINI 31_42
CLBLL_L.SLICEL_X1.C5FF.ZRST 00_44
CLBLL_L.SLICEL_X1.C5FFMUX.IN_A 31_44
CLBLL_L.SLICEL_X1.C5FFMUX.IN_B 31_39
CLBLL_L.SLICEL_X1.CARRY4.ACY0 !30_04 !31_00 !31_02 31_01 31_04 31_14 31_15
CLBLL_L.SLICEL_X1.CARRY4.ACY0 31_14
CLBLL_L.SLICEL_X1.CARRY4.BCY0 !31_24 !31_25 !31_26 00_08 31_27 31_29 31_30
CLBLL_L.SLICEL_X1.CARRY4.BCY0 00_08
CLBLL_L.SLICEL_X1.CARRY4.CCY0 !31_35 !31_36 !31_37 30_34 31_34 31_38 31_48
CLBLL_L.SLICEL_X1.CARRY4.CCY0 31_48
CLBLL_L.SLICEL_X1.CARRY4.DCY0 31_49
CLBLL_L.SLICEL_X1.CEUSEDMUX 00_36
CLBLL_L.SLICEL_X1.CFF.ZINI 31_34
CLBLL_L.SLICEL_X1.CFF.ZRST 30_34
CLBLL_L.SLICEL_X1.CFFMUX.CX !31_35 !31_36 !31_37 31_38
CLBLL_L.SLICEL_X1.CFFMUX.CY !31_36 !31_38 31_35 31_37
CLBLL_L.SLICEL_X1.CFFMUX.F7 !31_36 !31_37 31_35 31_38
CLBLL_L.SLICEL_X1.CFFMUX.O5 !31_37 !31_38 31_35 31_36
CLBLL_L.SLICEL_X1.CFFMUX.O6 !31_35 !31_37 !31_38 31_36
CLBLL_L.SLICEL_X1.CFFMUX.XOR !31_35 !31_36 !31_38 31_37
CLBLL_L.SLICEL_X1.CLKINV 00_52
CLBLL_L.SLICEL_X1.CLUT.INIT[00] 26_47
CLBLL_L.SLICEL_X1.CLUT.INIT[01] 27_47
@ -492,10 +597,22 @@ CLBLL_L.SLICEL_X1.CLUT.INIT[60] 29_33
CLBLL_L.SLICEL_X1.CLUT.INIT[61] 28_33
CLBLL_L.SLICEL_X1.CLUT.INIT[62] 29_32
CLBLL_L.SLICEL_X1.CLUT.INIT[63] 28_32
CLBLL_L.SLICEL_X1.COUTMUX.C5Q !30_42 !31_40 !31_43 30_41
CLBLL_L.SLICEL_X1.COUTMUX.CY !30_41 !31_43 30_42 31_40
CLBLL_L.SLICEL_X1.COUTMUX.F7 !30_42 !31_43 30_41 31_40
CLBLL_L.SLICEL_X1.COUTMUX.O5 !30_41 !30_42 31_40 31_43
CLBLL_L.SLICEL_X1.COUTMUX.XOR !30_41 !31_40 !31_43 30_42
CLBLL_L.SLICEL_X1.D5FF.ZINI 31_52
CLBLL_L.SLICEL_X1.D5FF.ZRST 00_56
CLBLL_L.SLICEL_X1.D5FFMUX.IN_A 31_55
CLBLL_L.SLICEL_X1.D5FFMUX.IN_B 31_54
CLBLL_L.SLICEL_X1.DFF.ZINI 31_59
CLBLL_L.SLICEL_X1.DFF.ZRST 31_50
CLBLL_L.SLICEL_X1.DFFMUX.CY !31_60 !31_61 30_58 31_62
CLBLL_L.SLICEL_X1.DFFMUX.DX !30_58 !31_60 !31_62 31_61
CLBLL_L.SLICEL_X1.DFFMUX.O5 !31_61 !31_62 30_58 31_60
CLBLL_L.SLICEL_X1.DFFMUX.O6 !30_58 !31_61 !31_62 31_60
CLBLL_L.SLICEL_X1.DFFMUX.XOR !30_58 !31_60 !31_61 31_62
CLBLL_L.SLICEL_X1.DLUT.INIT[00] 26_63
CLBLL_L.SLICEL_X1.DLUT.INIT[01] 27_63
CLBLL_L.SLICEL_X1.DLUT.INIT[02] 26_62
@ -560,6 +677,10 @@ CLBLL_L.SLICEL_X1.DLUT.INIT[60] 29_49
CLBLL_L.SLICEL_X1.DLUT.INIT[61] 28_49
CLBLL_L.SLICEL_X1.DLUT.INIT[62] 29_48
CLBLL_L.SLICEL_X1.DLUT.INIT[63] 28_48
CLBLL_L.SLICEL_X1.DOUTMUX.CY !31_53 !31_56 30_53 31_57
CLBLL_L.SLICEL_X1.DOUTMUX.D5Q !30_53 !31_56 !31_57 31_53
CLBLL_L.SLICEL_X1.DOUTMUX.O5 !30_53 !31_53 31_56 31_57
CLBLL_L.SLICEL_X1.DOUTMUX.XOR !31_53 !31_56 !31_57 30_53
CLBLL_L.SLICEL_X1.FFSYNC 01_31
CLBLL_L.SLICEL_X1.LATCH 31_32
CLBLL_L.SLICEL_X1.PRECYINIT.1 01_11

121
kintex7/segbits_clbll_r.db
View File

@ -1,7 +1,15 @@
CLBLL_R.SLICEL_X0.A5FF.ZINI 31_06
CLBLL_R.SLICEL_X0.A5FF.ZRST 01_07
CLBLL_R.SLICEL_X0.A5FFMUX.IN_A 30_09
CLBLL_R.SLICEL_X0.A5FFMUX.IN_B 30_10
CLBLL_R.SLICEL_X0.AFF.ZINI 31_03
CLBLL_R.SLICEL_X0.AFF.ZRST 30_12
CLBLL_R.SLICEL_X0.AFFMUX.AX !30_00 !30_02 !30_03 30_01
CLBLL_R.SLICEL_X0.AFFMUX.CY !30_01 !30_03 30_00 30_02
CLBLL_R.SLICEL_X0.AFFMUX.F7 !30_02 !30_03 30_00 30_01
CLBLL_R.SLICEL_X0.AFFMUX.O5 !30_01 !30_02 30_00 30_03
CLBLL_R.SLICEL_X0.AFFMUX.O6 !30_00 !30_01 !30_02 30_03
CLBLL_R.SLICEL_X0.AFFMUX.XOR !30_00 !30_01 !30_03 30_02
CLBLL_R.SLICEL_X0.ALUT.INIT[00] 32_15
CLBLL_R.SLICEL_X0.ALUT.INIT[01] 33_15
CLBLL_R.SLICEL_X0.ALUT.INIT[02] 32_14
@ -66,10 +74,26 @@ CLBLL_R.SLICEL_X0.ALUT.INIT[60] 35_01
CLBLL_R.SLICEL_X0.ALUT.INIT[61] 34_01
CLBLL_R.SLICEL_X0.ALUT.INIT[62] 35_00
CLBLL_R.SLICEL_X0.ALUT.INIT[63] 34_00
CLBLL_R.SLICEL_X0.ALUT.RAM 31_16
CLBLL_R.SLICEL_X0.ALUT.SMALL 00_04
CLBLL_R.SLICEL_X0.ALUT.SRL 30_16
CLBLL_R.SLICEL_X0.AOUTMUX.A5Q !30_06 !30_08 !30_11 30_07
CLBLL_R.SLICEL_X0.AOUTMUX.CY !30_07 !30_11 30_06 30_08
CLBLL_R.SLICEL_X0.AOUTMUX.F7 !30_08 !30_11 30_06 30_07
CLBLL_R.SLICEL_X0.AOUTMUX.O5 !30_07 !30_08 30_06 30_11
CLBLL_R.SLICEL_X0.AOUTMUX.XOR !30_06 !30_07 !30_11 30_08
CLBLL_R.SLICEL_X0.B5FF.ZINI 31_22
CLBLL_R.SLICEL_X0.B5FF.ZRST 01_19
CLBLL_R.SLICEL_X0.B5FFMUX.IN_A 30_19
CLBLL_R.SLICEL_X0.B5FFMUX.IN_B 30_18
CLBLL_R.SLICEL_X0.BFF.ZINI 31_28
CLBLL_R.SLICEL_X0.BFF.ZRST 30_30
CLBLL_R.SLICEL_X0.BFFMUX.BX !30_24 !30_25 !30_27 30_26
CLBLL_R.SLICEL_X0.BFFMUX.CY !30_24 !30_26 30_25 30_27
CLBLL_R.SLICEL_X0.BFFMUX.F8 !30_24 !30_25 30_26 30_27
CLBLL_R.SLICEL_X0.BFFMUX.O5 !30_25 !30_26 30_24 30_27
CLBLL_R.SLICEL_X0.BFFMUX.O6 !30_25 !30_26 !30_27 30_24
CLBLL_R.SLICEL_X0.BFFMUX.XOR !30_24 !30_26 !30_27 30_25
CLBLL_R.SLICEL_X0.BLUT.INIT[00] 32_31
CLBLL_R.SLICEL_X0.BLUT.INIT[01] 33_31
CLBLL_R.SLICEL_X0.BLUT.INIT[02] 32_30
@ -134,15 +158,34 @@ CLBLL_R.SLICEL_X0.BLUT.INIT[60] 35_17
CLBLL_R.SLICEL_X0.BLUT.INIT[61] 34_17
CLBLL_R.SLICEL_X0.BLUT.INIT[62] 35_16
CLBLL_R.SLICEL_X0.BLUT.INIT[63] 34_16
CLBLL_R.SLICEL_X0.BLUT.RAM 31_17
CLBLL_R.SLICEL_X0.BLUT.SMALL 00_24
CLBLL_R.SLICEL_X0.BLUT.SRL 30_17
CLBLL_R.SLICEL_X0.BOUTMUX.B5Q !30_20 !30_21 !30_22 30_23
CLBLL_R.SLICEL_X0.BOUTMUX.CY !30_20 !30_23 30_21 30_22
CLBLL_R.SLICEL_X0.BOUTMUX.F8 !30_20 !30_21 30_22 30_23
CLBLL_R.SLICEL_X0.BOUTMUX.O5 !30_21 !30_23 30_20 30_22
CLBLL_R.SLICEL_X0.BOUTMUX.XOR !30_20 !30_22 !30_23 30_21
CLBLL_R.SLICEL_X0.C5FF.ZINI 31_41
CLBLL_R.SLICEL_X0.C5FF.ZRST 01_47
CLBLL_R.SLICEL_X0.C5FFMUX.IN_A 31_45
CLBLL_R.SLICEL_X0.C5FFMUX.IN_B 30_39
CLBLL_R.SLICEL_X0.CARRY4.ACY0 !30_00 !30_02 !30_03 30_01 30_12 30_15 31_03
CLBLL_R.SLICEL_X0.CARRY4.ACY0 30_15
CLBLL_R.SLICEL_X0.CARRY4.BCY0 !30_24 !30_25 !30_27 01_15 30_26 30_30 31_28
CLBLL_R.SLICEL_X0.CARRY4.BCY0 01_15
CLBLL_R.SLICEL_X0.CARRY4.CCY0 !30_35 !30_37 !30_38 30_33 30_36 30_48 31_33
CLBLL_R.SLICEL_X0.CARRY4.CCY0 30_48
CLBLL_R.SLICEL_X0.CARRY4.DCY0 30_49
CLBLL_R.SLICEL_X0.CEUSEDMUX 01_39
CLBLL_R.SLICEL_X0.CFF.ZINI 31_33
CLBLL_R.SLICEL_X0.CFF.ZRST 30_33
CLBLL_R.SLICEL_X0.CFFMUX.CX !30_35 !30_37 !30_38 30_36
CLBLL_R.SLICEL_X0.CFFMUX.CY !30_36 !30_38 30_35 30_37
CLBLL_R.SLICEL_X0.CFFMUX.F7 !30_37 !30_38 30_35 30_36
CLBLL_R.SLICEL_X0.CFFMUX.O5 !30_36 !30_37 30_35 30_38
CLBLL_R.SLICEL_X0.CFFMUX.O6 !30_35 !30_36 !30_37 30_38
CLBLL_R.SLICEL_X0.CFFMUX.XOR !30_35 !30_36 !30_38 30_37
CLBLL_R.SLICEL_X0.CLKINV 01_51
CLBLL_R.SLICEL_X0.CLUT.INIT[00] 32_47
CLBLL_R.SLICEL_X0.CLUT.INIT[01] 33_47
@ -208,10 +251,25 @@ CLBLL_R.SLICEL_X0.CLUT.INIT[60] 35_33
CLBLL_R.SLICEL_X0.CLUT.INIT[61] 34_33
CLBLL_R.SLICEL_X0.CLUT.INIT[62] 35_32
CLBLL_R.SLICEL_X0.CLUT.INIT[63] 34_32
CLBLL_R.SLICEL_X0.CLUT.RAM 31_46
CLBLL_R.SLICEL_X0.CLUT.SMALL 00_28
CLBLL_R.SLICEL_X0.CLUT.SRL 30_46
CLBLL_R.SLICEL_X0.COUTMUX.C5Q !30_40 !30_44 !30_45 30_43
CLBLL_R.SLICEL_X0.COUTMUX.CY !30_43 !30_45 30_40 30_44
CLBLL_R.SLICEL_X0.COUTMUX.F7 !30_44 !30_45 30_40 30_43
CLBLL_R.SLICEL_X0.COUTMUX.O5 !30_43 !30_44 30_40 30_45
CLBLL_R.SLICEL_X0.COUTMUX.XOR !30_40 !30_43 !30_45 30_44
CLBLL_R.SLICEL_X0.D5FF.ZINI 31_51
CLBLL_R.SLICEL_X0.D5FF.ZRST 01_55
CLBLL_R.SLICEL_X0.D5FFMUX.IN_A 30_55
CLBLL_R.SLICEL_X0.D5FFMUX.IN_B 30_54
CLBLL_R.SLICEL_X0.DFF.ZINI 31_58
CLBLL_R.SLICEL_X0.DFF.ZRST 30_50
CLBLL_R.SLICEL_X0.DFFMUX.CY !30_59 !30_61 30_60 30_62
CLBLL_R.SLICEL_X0.DFFMUX.DX !30_59 !30_60 !30_62 30_61
CLBLL_R.SLICEL_X0.DFFMUX.O5 !30_60 !30_61 30_59 30_62
CLBLL_R.SLICEL_X0.DFFMUX.O6 !30_60 !30_61 !30_62 30_59
CLBLL_R.SLICEL_X0.DFFMUX.XOR !30_59 !30_61 !30_62 30_60
CLBLL_R.SLICEL_X0.DLUT.INIT[00] 32_63
CLBLL_R.SLICEL_X0.DLUT.INIT[01] 33_63
CLBLL_R.SLICEL_X0.DLUT.INIT[02] 32_62
@ -276,16 +334,34 @@ CLBLL_R.SLICEL_X0.DLUT.INIT[60] 35_49
CLBLL_R.SLICEL_X0.DLUT.INIT[61] 34_49
CLBLL_R.SLICEL_X0.DLUT.INIT[62] 35_48
CLBLL_R.SLICEL_X0.DLUT.INIT[63] 34_48
CLBLL_R.SLICEL_X0.DLUT.RAM 31_47
CLBLL_R.SLICEL_X0.DLUT.SMALL 01_59
CLBLL_R.SLICEL_X0.DLUT.SRL 30_47
CLBLL_R.SLICEL_X0.DOUTMUX.CY !30_56 !30_57 30_51 30_52
CLBLL_R.SLICEL_X0.DOUTMUX.D5Q !30_51 !30_52 !30_56 30_57
CLBLL_R.SLICEL_X0.DOUTMUX.O5 !30_51 !30_57 30_52 30_56
CLBLL_R.SLICEL_X0.DOUTMUX.XOR !30_52 !30_56 !30_57 30_51
CLBLL_R.SLICEL_X0.FFSYNC 00_48
CLBLL_R.SLICEL_X0.LATCH 30_32
CLBLL_R.SLICEL_X0.PRECYINIT.1 00_12
CLBLL_R.SLICEL_X0.PRECYINIT.AX 30_14
CLBLL_R.SLICEL_X0.PRECYINIT.CIN 30_13
CLBLL_R.SLICEL_X0.SRUSEDMUX 01_35
CLBLL_R.SLICEL_X0.WA7USED 00_40
CLBLL_R.SLICEL_X0.WA8USED 01_27
CLBLL_R.SLICEL_X0.WEMUX.CE 01_23
CLBLL_R.SLICEL_X1.A5FF.ZINI 31_05
CLBLL_R.SLICEL_X1.A5FF.ZRST 01_03
CLBLL_R.SLICEL_X1.A5FFMUX.IN_A 31_08
CLBLL_R.SLICEL_X1.A5FFMUX.IN_B 31_11
CLBLL_R.SLICEL_X1.AFF.ZINI 31_04
CLBLL_R.SLICEL_X1.AFF.ZRST 31_15
CLBLL_R.SLICEL_X1.AFFMUX.AX !30_04 !31_00 !31_02 31_01
CLBLL_R.SLICEL_X1.AFFMUX.CY !30_04 !31_01 31_00 31_02
CLBLL_R.SLICEL_X1.AFFMUX.F7 !30_04 !31_02 31_00 31_01
CLBLL_R.SLICEL_X1.AFFMUX.O5 !31_01 !31_02 30_04 31_00
CLBLL_R.SLICEL_X1.AFFMUX.O6 !31_00 !31_01 !31_02 30_04
CLBLL_R.SLICEL_X1.AFFMUX.XOR !30_04 !31_00 !31_01 31_02
CLBLL_R.SLICEL_X1.ALUT.INIT[00] 26_15
CLBLL_R.SLICEL_X1.ALUT.INIT[01] 27_15
CLBLL_R.SLICEL_X1.ALUT.INIT[02] 26_14
@ -350,10 +426,23 @@ CLBLL_R.SLICEL_X1.ALUT.INIT[60] 29_01
CLBLL_R.SLICEL_X1.ALUT.INIT[61] 28_01
CLBLL_R.SLICEL_X1.ALUT.INIT[62] 29_00
CLBLL_R.SLICEL_X1.ALUT.INIT[63] 28_00
CLBLL_R.SLICEL_X1.AOUTMUX.A5Q !31_07 !31_09 !31_10 30_05
CLBLL_R.SLICEL_X1.AOUTMUX.CY !30_05 !31_09 31_07 31_10
CLBLL_R.SLICEL_X1.AOUTMUX.F7 !31_07 !31_09 30_05 31_10
CLBLL_R.SLICEL_X1.AOUTMUX.O5 !30_05 !31_07 31_09 31_10
CLBLL_R.SLICEL_X1.AOUTMUX.XOR !30_05 !31_09 !31_10 31_07
CLBLL_R.SLICEL_X1.B5FF.ZINI 31_23
CLBLL_R.SLICEL_X1.B5FF.ZRST 00_16
CLBLL_R.SLICEL_X1.B5FFMUX.IN_A 31_19
CLBLL_R.SLICEL_X1.B5FFMUX.IN_B 31_18
CLBLL_R.SLICEL_X1.BFF.ZINI 31_29
CLBLL_R.SLICEL_X1.BFF.ZRST 31_30
CLBLL_R.SLICEL_X1.BFFMUX.BX !31_24 !31_25 !31_26 31_27
CLBLL_R.SLICEL_X1.BFFMUX.CY !31_24 !31_27 31_25 31_26
CLBLL_R.SLICEL_X1.BFFMUX.F8 !31_24 !31_26 31_25 31_27
CLBLL_R.SLICEL_X1.BFFMUX.O5 !31_26 !31_27 31_24 31_25
CLBLL_R.SLICEL_X1.BFFMUX.O6 !31_25 !31_26 !31_27 31_24
CLBLL_R.SLICEL_X1.BFFMUX.XOR !31_24 !31_25 !31_27 31_26
CLBLL_R.SLICEL_X1.BLUT.INIT[00] 26_31
CLBLL_R.SLICEL_X1.BLUT.INIT[01] 27_31
CLBLL_R.SLICEL_X1.BLUT.INIT[02] 26_30
@ -418,15 +507,31 @@ CLBLL_R.SLICEL_X1.BLUT.INIT[60] 29_17
CLBLL_R.SLICEL_X1.BLUT.INIT[61] 28_17
CLBLL_R.SLICEL_X1.BLUT.INIT[62] 29_16
CLBLL_R.SLICEL_X1.BLUT.INIT[63] 28_16
CLBLL_R.SLICEL_X1.BOUTMUX.B5Q !30_28 !31_20 !31_21 30_29
CLBLL_R.SLICEL_X1.BOUTMUX.CY !30_29 !31_20 30_28 31_21
CLBLL_R.SLICEL_X1.BOUTMUX.F8 !30_28 !31_20 30_29 31_21
CLBLL_R.SLICEL_X1.BOUTMUX.O5 !30_28 !30_29 31_20 31_21
CLBLL_R.SLICEL_X1.BOUTMUX.XOR !30_29 !31_20 !31_21 30_28
CLBLL_R.SLICEL_X1.C5FF.ZINI 31_42
CLBLL_R.SLICEL_X1.C5FF.ZRST 00_44
CLBLL_R.SLICEL_X1.C5FFMUX.IN_A 31_44
CLBLL_R.SLICEL_X1.C5FFMUX.IN_B 31_39
CLBLL_R.SLICEL_X1.CARRY4.ACY0 !30_04 !31_00 !31_02 31_01 31_04 31_14 31_15
CLBLL_R.SLICEL_X1.CARRY4.ACY0 31_14
CLBLL_R.SLICEL_X1.CARRY4.BCY0 !31_24 !31_25 !31_26 00_08 31_27 31_29 31_30
CLBLL_R.SLICEL_X1.CARRY4.BCY0 00_08
CLBLL_R.SLICEL_X1.CARRY4.CCY0 !31_35 !31_36 !31_37 30_34 31_34 31_38 31_48
CLBLL_R.SLICEL_X1.CARRY4.CCY0 31_48
CLBLL_R.SLICEL_X1.CARRY4.DCY0 31_49
CLBLL_R.SLICEL_X1.CEUSEDMUX 00_36
CLBLL_R.SLICEL_X1.CFF.ZINI 31_34
CLBLL_R.SLICEL_X1.CFF.ZRST 30_34
CLBLL_R.SLICEL_X1.CFFMUX.CX !31_35 !31_36 !31_37 31_38
CLBLL_R.SLICEL_X1.CFFMUX.CY !31_36 !31_38 31_35 31_37
CLBLL_R.SLICEL_X1.CFFMUX.F7 !31_36 !31_37 31_35 31_38
CLBLL_R.SLICEL_X1.CFFMUX.O5 !31_37 !31_38 31_35 31_36
CLBLL_R.SLICEL_X1.CFFMUX.O6 !31_35 !31_37 !31_38 31_36
CLBLL_R.SLICEL_X1.CFFMUX.XOR !31_35 !31_36 !31_38 31_37
CLBLL_R.SLICEL_X1.CLKINV 00_52
CLBLL_R.SLICEL_X1.CLUT.INIT[00] 26_47
CLBLL_R.SLICEL_X1.CLUT.INIT[01] 27_47
@ -492,10 +597,22 @@ CLBLL_R.SLICEL_X1.CLUT.INIT[60] 29_33
CLBLL_R.SLICEL_X1.CLUT.INIT[61] 28_33
CLBLL_R.SLICEL_X1.CLUT.INIT[62] 29_32
CLBLL_R.SLICEL_X1.CLUT.INIT[63] 28_32
CLBLL_R.SLICEL_X1.COUTMUX.C5Q !30_42 !31_40 !31_43 30_41
CLBLL_R.SLICEL_X1.COUTMUX.CY !30_41 !31_43 30_42 31_40
CLBLL_R.SLICEL_X1.COUTMUX.F7 !30_42 !31_43 30_41 31_40
CLBLL_R.SLICEL_X1.COUTMUX.O5 !30_41 !30_42 31_40 31_43
CLBLL_R.SLICEL_X1.COUTMUX.XOR !30_41 !31_40 !31_43 30_42
CLBLL_R.SLICEL_X1.D5FF.ZINI 31_52
CLBLL_R.SLICEL_X1.D5FF.ZRST 00_56
CLBLL_R.SLICEL_X1.D5FFMUX.IN_A 31_55
CLBLL_R.SLICEL_X1.D5FFMUX.IN_B 31_54
CLBLL_R.SLICEL_X1.DFF.ZINI 31_59
CLBLL_R.SLICEL_X1.DFF.ZRST 31_50
CLBLL_R.SLICEL_X1.DFFMUX.CY !31_60 !31_61 30_58 31_62
CLBLL_R.SLICEL_X1.DFFMUX.DX !30_58 !31_60 !31_62 31_61
CLBLL_R.SLICEL_X1.DFFMUX.O5 !31_61 !31_62 30_58 31_60
CLBLL_R.SLICEL_X1.DFFMUX.O6 !30_58 !31_61 !31_62 31_60
CLBLL_R.SLICEL_X1.DFFMUX.XOR !30_58 !31_60 !31_61 31_62
CLBLL_R.SLICEL_X1.DLUT.INIT[00] 26_63
CLBLL_R.SLICEL_X1.DLUT.INIT[01] 27_63
CLBLL_R.SLICEL_X1.DLUT.INIT[02] 26_62
@ -560,6 +677,10 @@ CLBLL_R.SLICEL_X1.DLUT.INIT[60] 29_49
CLBLL_R.SLICEL_X1.DLUT.INIT[61] 28_49
CLBLL_R.SLICEL_X1.DLUT.INIT[62] 29_48
CLBLL_R.SLICEL_X1.DLUT.INIT[63] 28_48
CLBLL_R.SLICEL_X1.DOUTMUX.CY !31_53 !31_56 30_53 31_57
CLBLL_R.SLICEL_X1.DOUTMUX.D5Q !30_53 !31_56 !31_57 31_53
CLBLL_R.SLICEL_X1.DOUTMUX.O5 !30_53 !31_53 31_56 31_57
CLBLL_R.SLICEL_X1.DOUTMUX.XOR !31_53 !31_56 !31_57 30_53
CLBLL_R.SLICEL_X1.FFSYNC 01_31
CLBLL_R.SLICEL_X1.LATCH 31_32
CLBLL_R.SLICEL_X1.PRECYINIT.1 01_11

127
kintex7/segbits_clblm_l.db
View File

@ -1,7 +1,15 @@
CLBLM_L.SLICEL_X1.A5FF.ZINI 31_05
CLBLM_L.SLICEL_X1.A5FF.ZRST 01_03
CLBLM_L.SLICEL_X1.A5FFMUX.IN_A 31_08
CLBLM_L.SLICEL_X1.A5FFMUX.IN_B 31_11
CLBLM_L.SLICEL_X1.AFF.ZINI 31_04
CLBLM_L.SLICEL_X1.AFF.ZRST 31_15
CLBLM_L.SLICEL_X1.AFFMUX.AX !30_04 !31_00 !31_02 31_01
CLBLM_L.SLICEL_X1.AFFMUX.CY !30_04 !31_01 31_00 31_02
CLBLM_L.SLICEL_X1.AFFMUX.F7 !30_04 !31_02 31_00 31_01
CLBLM_L.SLICEL_X1.AFFMUX.O5 !31_01 !31_02 30_04 31_00
CLBLM_L.SLICEL_X1.AFFMUX.O6 !31_00 !31_01 !31_02 30_04
CLBLM_L.SLICEL_X1.AFFMUX.XOR !30_04 !31_00 !31_01 31_02
CLBLM_L.SLICEL_X1.ALUT.INIT[00] 26_15
CLBLM_L.SLICEL_X1.ALUT.INIT[01] 27_15
CLBLM_L.SLICEL_X1.ALUT.INIT[02] 26_14
@ -66,10 +74,23 @@ CLBLM_L.SLICEL_X1.ALUT.INIT[60] 29_01
CLBLM_L.SLICEL_X1.ALUT.INIT[61] 28_01
CLBLM_L.SLICEL_X1.ALUT.INIT[62] 29_00
CLBLM_L.SLICEL_X1.ALUT.INIT[63] 28_00
CLBLM_L.SLICEL_X1.AOUTMUX.A5Q !31_07 !31_09 !31_10 30_05
CLBLM_L.SLICEL_X1.AOUTMUX.CY !30_05 !31_09 31_07 31_10
CLBLM_L.SLICEL_X1.AOUTMUX.F7 !31_07 !31_09 30_05 31_10
CLBLM_L.SLICEL_X1.AOUTMUX.O5 !30_05 !31_07 31_09 31_10
CLBLM_L.SLICEL_X1.AOUTMUX.XOR !30_05 !31_09 !31_10 31_07
CLBLM_L.SLICEL_X1.B5FF.ZINI 31_23
CLBLM_L.SLICEL_X1.B5FF.ZRST 00_16
CLBLM_L.SLICEL_X1.B5FFMUX.IN_A 31_19
CLBLM_L.SLICEL_X1.B5FFMUX.IN_B 31_18
CLBLM_L.SLICEL_X1.BFF.ZINI 31_29
CLBLM_L.SLICEL_X1.BFF.ZRST 31_30
CLBLM_L.SLICEL_X1.BFFMUX.BX !31_24 !31_25 !31_26 31_27
CLBLM_L.SLICEL_X1.BFFMUX.CY !31_24 !31_27 31_25 31_26
CLBLM_L.SLICEL_X1.BFFMUX.F8 !31_24 !31_26 31_25 31_27
CLBLM_L.SLICEL_X1.BFFMUX.O5 !31_26 !31_27 31_24 31_25
CLBLM_L.SLICEL_X1.BFFMUX.O6 !31_25 !31_26 !31_27 31_24
CLBLM_L.SLICEL_X1.BFFMUX.XOR !31_24 !31_25 !31_27 31_26
CLBLM_L.SLICEL_X1.BLUT.INIT[00] 26_31
CLBLM_L.SLICEL_X1.BLUT.INIT[01] 27_31
CLBLM_L.SLICEL_X1.BLUT.INIT[02] 26_30
@ -134,15 +155,31 @@ CLBLM_L.SLICEL_X1.BLUT.INIT[60] 29_17
CLBLM_L.SLICEL_X1.BLUT.INIT[61] 28_17
CLBLM_L.SLICEL_X1.BLUT.INIT[62] 29_16
CLBLM_L.SLICEL_X1.BLUT.INIT[63] 28_16
CLBLM_L.SLICEL_X1.BOUTMUX.B5Q !30_28 !31_20 !31_21 30_29
CLBLM_L.SLICEL_X1.BOUTMUX.CY !30_29 !31_20 30_28 31_21
CLBLM_L.SLICEL_X1.BOUTMUX.F8 !30_28 !31_20 30_29 31_21
CLBLM_L.SLICEL_X1.BOUTMUX.O5 !30_28 !30_29 31_20 31_21
CLBLM_L.SLICEL_X1.BOUTMUX.XOR !30_29 !31_20 !31_21 30_28
CLBLM_L.SLICEL_X1.C5FF.ZINI 31_42
CLBLM_L.SLICEL_X1.C5FF.ZRST 00_44
CLBLM_L.SLICEL_X1.C5FFMUX.IN_A 31_44
CLBLM_L.SLICEL_X1.C5FFMUX.IN_B 31_39
CLBLM_L.SLICEL_X1.CARRY4.ACY0 !30_04 !31_00 !31_02 31_01 31_04 31_14 31_15
CLBLM_L.SLICEL_X1.CARRY4.ACY0 31_14
CLBLM_L.SLICEL_X1.CARRY4.BCY0 !31_24 !31_25 !31_26 00_08 31_27 31_29 31_30
CLBLM_L.SLICEL_X1.CARRY4.BCY0 00_08
CLBLM_L.SLICEL_X1.CARRY4.CCY0 !31_35 !31_36 !31_37 30_34 31_34 31_38 31_48
CLBLM_L.SLICEL_X1.CARRY4.CCY0 31_48
CLBLM_L.SLICEL_X1.CARRY4.DCY0 31_49
CLBLM_L.SLICEL_X1.CEUSEDMUX 00_36
CLBLM_L.SLICEL_X1.CFF.ZINI 31_34
CLBLM_L.SLICEL_X1.CFF.ZRST 30_34
CLBLM_L.SLICEL_X1.CFFMUX.CX !31_35 !31_36 !31_37 31_38
CLBLM_L.SLICEL_X1.CFFMUX.CY !31_36 !31_38 31_35 31_37
CLBLM_L.SLICEL_X1.CFFMUX.F7 !31_36 !31_37 31_35 31_38
CLBLM_L.SLICEL_X1.CFFMUX.O5 !31_37 !31_38 31_35 31_36
CLBLM_L.SLICEL_X1.CFFMUX.O6 !31_35 !31_37 !31_38 31_36
CLBLM_L.SLICEL_X1.CFFMUX.XOR !31_35 !31_36 !31_38 31_37
CLBLM_L.SLICEL_X1.CLKINV 00_52
CLBLM_L.SLICEL_X1.CLUT.INIT[00] 26_47
CLBLM_L.SLICEL_X1.CLUT.INIT[01] 27_47
@ -208,10 +245,22 @@ CLBLM_L.SLICEL_X1.CLUT.INIT[60] 29_33
CLBLM_L.SLICEL_X1.CLUT.INIT[61] 28_33
CLBLM_L.SLICEL_X1.CLUT.INIT[62] 29_32
CLBLM_L.SLICEL_X1.CLUT.INIT[63] 28_32
CLBLM_L.SLICEL_X1.COUTMUX.C5Q !30_42 !31_40 !31_43 30_41
CLBLM_L.SLICEL_X1.COUTMUX.CY !30_41 !31_43 30_42 31_40
CLBLM_L.SLICEL_X1.COUTMUX.F7 !30_42 !31_43 30_41 31_40
CLBLM_L.SLICEL_X1.COUTMUX.O5 !30_41 !30_42 31_40 31_43
CLBLM_L.SLICEL_X1.COUTMUX.XOR !30_41 !31_40 !31_43 30_42
CLBLM_L.SLICEL_X1.D5FF.ZINI 31_52
CLBLM_L.SLICEL_X1.D5FF.ZRST 00_56
CLBLM_L.SLICEL_X1.D5FFMUX.IN_A 31_55
CLBLM_L.SLICEL_X1.D5FFMUX.IN_B 31_54
CLBLM_L.SLICEL_X1.DFF.ZINI 31_59
CLBLM_L.SLICEL_X1.DFF.ZRST 31_50
CLBLM_L.SLICEL_X1.DFFMUX.CY !31_60 !31_61 30_58 31_62
CLBLM_L.SLICEL_X1.DFFMUX.DX !30_58 !31_60 !31_62 31_61
CLBLM_L.SLICEL_X1.DFFMUX.O5 !31_61 !31_62 30_58 31_60
CLBLM_L.SLICEL_X1.DFFMUX.O6 !30_58 !31_61 !31_62 31_60
CLBLM_L.SLICEL_X1.DFFMUX.XOR !30_58 !31_60 !31_61 31_62
CLBLM_L.SLICEL_X1.DLUT.INIT[00] 26_63
CLBLM_L.SLICEL_X1.DLUT.INIT[01] 27_63
CLBLM_L.SLICEL_X1.DLUT.INIT[02] 26_62
@ -276,6 +325,10 @@ CLBLM_L.SLICEL_X1.DLUT.INIT[60] 29_49
CLBLM_L.SLICEL_X1.DLUT.INIT[61] 28_49
CLBLM_L.SLICEL_X1.DLUT.INIT[62] 29_48
CLBLM_L.SLICEL_X1.DLUT.INIT[63] 28_48
CLBLM_L.SLICEL_X1.DOUTMUX.CY !31_53 !31_56 30_53 31_57
CLBLM_L.SLICEL_X1.DOUTMUX.D5Q !30_53 !31_56 !31_57 31_53
CLBLM_L.SLICEL_X1.DOUTMUX.O5 !30_53 !31_53 31_56 31_57
CLBLM_L.SLICEL_X1.DOUTMUX.XOR !31_53 !31_56 !31_57 30_53
CLBLM_L.SLICEL_X1.FFSYNC 01_31
CLBLM_L.SLICEL_X1.LATCH 31_32
CLBLM_L.SLICEL_X1.PRECYINIT.1 01_11
@ -284,8 +337,18 @@ CLBLM_L.SLICEL_X1.PRECYINIT.CIN 31_12
CLBLM_L.SLICEL_X1.SRUSEDMUX 00_32
CLBLM_L.SLICEM_X0.A5FF.ZINI 31_06
CLBLM_L.SLICEM_X0.A5FF.ZRST 01_07
CLBLM_L.SLICEM_X0.A5FFMUX.IN_A 30_09
CLBLM_L.SLICEM_X0.A5FFMUX.IN_B 30_10
CLBLM_L.SLICEM_X0.ADI1MUX.AI !22_00 !23_00 !24_00 00_00 25_00
CLBLM_L.SLICEM_X0.AFF.ZINI 31_03
CLBLM_L.SLICEM_X0.AFF.ZRST 30_12
CLBLM_L.SLICEM_X0.AFFMUX.AX !30_00 !30_02 !30_03 30_01
CLBLM_L.SLICEM_X0.AFFMUX.CY !30_01 !30_03 30_00 30_02
CLBLM_L.SLICEM_X0.AFFMUX.F7 !30_02 !30_03 30_00 30_01
CLBLM_L.SLICEM_X0.AFFMUX.O5 !30_01 !30_02 30_00 30_03
CLBLM_L.SLICEM_X0.AFFMUX.O6 !30_00 !30_01 !30_02 30_03
CLBLM_L.SLICEM_X0.AFFMUX.XOR !30_00 !30_01 !30_03 30_02
CLBLM_L.SLICEM_X0.ALUT.DI1MUX.AI 00_00
CLBLM_L.SLICEM_X0.ALUT.INIT[00] 34_15
CLBLM_L.SLICEM_X0.ALUT.INIT[01] 35_15
CLBLM_L.SLICEM_X0.ALUT.INIT[02] 34_14
@ -350,10 +413,28 @@ CLBLM_L.SLICEM_X0.ALUT.INIT[60] 32_01
CLBLM_L.SLICEM_X0.ALUT.INIT[61] 33_01
CLBLM_L.SLICEM_X0.ALUT.INIT[62] 32_00
CLBLM_L.SLICEM_X0.ALUT.INIT[63] 33_00
CLBLM_L.SLICEM_X0.ALUT.RAM 31_16
CLBLM_L.SLICEM_X0.ALUT.SMALL 00_04
CLBLM_L.SLICEM_X0.ALUT.SRL 30_16
CLBLM_L.SLICEM_X0.AOUTMUX.A5Q !30_06 !30_08 !30_11 30_07
CLBLM_L.SLICEM_X0.AOUTMUX.CY !30_07 !30_11 30_06 30_08
CLBLM_L.SLICEM_X0.AOUTMUX.F7 !30_08 !30_11 30_06 30_07
CLBLM_L.SLICEM_X0.AOUTMUX.O5 !30_07 !30_08 30_06 30_11
CLBLM_L.SLICEM_X0.AOUTMUX.XOR !30_06 !30_07 !30_11 30_08
CLBLM_L.SLICEM_X0.B5FF.ZINI 31_22
CLBLM_L.SLICEM_X0.B5FF.ZRST 01_19
CLBLM_L.SLICEM_X0.B5FFMUX.IN_A 30_19
CLBLM_L.SLICEM_X0.B5FFMUX.IN_B 30_18
CLBLM_L.SLICEM_X0.BDI1MUX.BI 00_20
CLBLM_L.SLICEM_X0.BFF.ZINI 31_28
CLBLM_L.SLICEM_X0.BFF.ZRST 30_30
CLBLM_L.SLICEM_X0.BFFMUX.BX !30_24 !30_25 !30_27 30_26
CLBLM_L.SLICEM_X0.BFFMUX.CY !30_24 !30_26 30_25 30_27
CLBLM_L.SLICEM_X0.BFFMUX.F8 !30_24 !30_25 30_26 30_27
CLBLM_L.SLICEM_X0.BFFMUX.O5 !30_25 !30_26 30_24 30_27
CLBLM_L.SLICEM_X0.BFFMUX.O6 !30_25 !30_26 !30_27 30_24
CLBLM_L.SLICEM_X0.BFFMUX.XOR !30_24 !30_26 !30_27 30_25
CLBLM_L.SLICEM_X0.BLUT.DI1MUX.BI 00_20
CLBLM_L.SLICEM_X0.BLUT.INIT[00] 34_31
CLBLM_L.SLICEM_X0.BLUT.INIT[01] 35_31
CLBLM_L.SLICEM_X0.BLUT.INIT[02] 34_30
@ -418,16 +499,37 @@ CLBLM_L.SLICEM_X0.BLUT.INIT[60] 32_17
CLBLM_L.SLICEM_X0.BLUT.INIT[61] 33_17
CLBLM_L.SLICEM_X0.BLUT.INIT[62] 32_16
CLBLM_L.SLICEM_X0.BLUT.INIT[63] 33_16
CLBLM_L.SLICEM_X0.BLUT.RAM 31_17
CLBLM_L.SLICEM_X0.BLUT.SMALL 00_24
CLBLM_L.SLICEM_X0.BLUT.SRL 30_17
CLBLM_L.SLICEM_X0.BOUTMUX.B5Q !30_20 !30_21 !30_22 30_23
CLBLM_L.SLICEM_X0.BOUTMUX.CY !30_20 !30_23 30_21 30_22
CLBLM_L.SLICEM_X0.BOUTMUX.F8 !30_20 !30_21 30_22 30_23
CLBLM_L.SLICEM_X0.BOUTMUX.O5 !30_21 !30_23 30_20 30_22
CLBLM_L.SLICEM_X0.BOUTMUX.XOR !30_20 !30_22 !30_23 30_21
CLBLM_L.SLICEM_X0.C5FF.ZINI 31_41
CLBLM_L.SLICEM_X0.C5FF.ZRST 01_47
CLBLM_L.SLICEM_X0.C5FFMUX.IN_A 31_45
CLBLM_L.SLICEM_X0.C5FFMUX.IN_B 30_39
CLBLM_L.SLICEM_X0.CARRY4.ACY0 !30_00 !30_02 !30_03 30_01 30_12 30_15 31_03
CLBLM_L.SLICEM_X0.CARRY4.ACY0 30_15
CLBLM_L.SLICEM_X0.CARRY4.BCY0 !30_24 !30_25 !30_27 01_15 30_26 30_30 31_28
CLBLM_L.SLICEM_X0.CARRY4.BCY0 01_15
CLBLM_L.SLICEM_X0.CARRY4.CCY0 !30_35 !30_37 !30_38 30_33 30_36 30_48 31_33
CLBLM_L.SLICEM_X0.CARRY4.CCY0 30_48
CLBLM_L.SLICEM_X0.CARRY4.DCY0 30_49
CLBLM_L.SLICEM_X0.CDI1MUX.CI 01_43
CLBLM_L.SLICEM_X0.CEUSEDMUX 01_39
CLBLM_L.SLICEM_X0.CFF.ZINI 31_33
CLBLM_L.SLICEM_X0.CFF.ZRST 30_33
CLBLM_L.SLICEM_X0.CFFMUX.CX !30_35 !30_37 !30_38 30_36
CLBLM_L.SLICEM_X0.CFFMUX.CY !30_36 !30_38 30_35 30_37
CLBLM_L.SLICEM_X0.CFFMUX.F7 !30_37 !30_38 30_35 30_36
CLBLM_L.SLICEM_X0.CFFMUX.O5 !30_36 !30_37 30_35 30_38
CLBLM_L.SLICEM_X0.CFFMUX.O6 !30_35 !30_36 !30_37 30_38
CLBLM_L.SLICEM_X0.CFFMUX.XOR !30_35 !30_36 !30_38 30_37
CLBLM_L.SLICEM_X0.CLKINV 01_51
CLBLM_L.SLICEM_X0.CLUT.DI1MUX.CI 01_43
CLBLM_L.SLICEM_X0.CLUT.INIT[00] 34_47
CLBLM_L.SLICEM_X0.CLUT.INIT[01] 35_47
CLBLM_L.SLICEM_X0.CLUT.INIT[02] 34_46
@ -492,10 +594,25 @@ CLBLM_L.SLICEM_X0.CLUT.INIT[60] 32_33
CLBLM_L.SLICEM_X0.CLUT.INIT[61] 33_33
CLBLM_L.SLICEM_X0.CLUT.INIT[62] 32_32
CLBLM_L.SLICEM_X0.CLUT.INIT[63] 33_32
CLBLM_L.SLICEM_X0.CLUT.RAM 31_46
CLBLM_L.SLICEM_X0.CLUT.SMALL 00_28
CLBLM_L.SLICEM_X0.CLUT.SRL 30_46
CLBLM_L.SLICEM_X0.COUTMUX.C5Q !30_40 !30_44 !30_45 30_43
CLBLM_L.SLICEM_X0.COUTMUX.CY !30_43 !30_45 30_40 30_44
CLBLM_L.SLICEM_X0.COUTMUX.F7 !30_44 !30_45 30_40 30_43
CLBLM_L.SLICEM_X0.COUTMUX.O5 !30_43 !30_44 30_40 30_45
CLBLM_L.SLICEM_X0.COUTMUX.XOR !30_40 !30_43 !30_45 30_44
CLBLM_L.SLICEM_X0.D5FF.ZINI 31_51
CLBLM_L.SLICEM_X0.D5FF.ZRST 01_55
CLBLM_L.SLICEM_X0.D5FFMUX.IN_A 30_55
CLBLM_L.SLICEM_X0.D5FFMUX.IN_B 30_54
CLBLM_L.SLICEM_X0.DFF.ZINI 31_58
CLBLM_L.SLICEM_X0.DFF.ZRST 30_50
CLBLM_L.SLICEM_X0.DFFMUX.CY !30_59 !30_61 30_60 30_62
CLBLM_L.SLICEM_X0.DFFMUX.DX !30_59 !30_60 !30_62 30_61
CLBLM_L.SLICEM_X0.DFFMUX.O5 !30_60 !30_61 30_59 30_62
CLBLM_L.SLICEM_X0.DFFMUX.O6 !30_60 !30_61 !30_62 30_59
CLBLM_L.SLICEM_X0.DFFMUX.XOR !30_59 !30_61 !30_62 30_60
CLBLM_L.SLICEM_X0.DLUT.INIT[00] 34_63
CLBLM_L.SLICEM_X0.DLUT.INIT[01] 35_63
CLBLM_L.SLICEM_X0.DLUT.INIT[02] 34_62
@ -560,9 +677,19 @@ CLBLM_L.SLICEM_X0.DLUT.INIT[60] 32_49
CLBLM_L.SLICEM_X0.DLUT.INIT[61] 33_49
CLBLM_L.SLICEM_X0.DLUT.INIT[62] 32_48
CLBLM_L.SLICEM_X0.DLUT.INIT[63] 33_48
CLBLM_L.SLICEM_X0.DLUT.RAM 31_47
CLBLM_L.SLICEM_X0.DLUT.SMALL 01_59
CLBLM_L.SLICEM_X0.DLUT.SRL 30_47
CLBLM_L.SLICEM_X0.DOUTMUX.CY !30_56 !30_57 30_51 30_52
CLBLM_L.SLICEM_X0.DOUTMUX.D5Q !30_51 !30_52 !30_56 30_57
CLBLM_L.SLICEM_X0.DOUTMUX.O5 !30_51 !30_57 30_52 30_56
CLBLM_L.SLICEM_X0.DOUTMUX.XOR !30_52 !30_56 !30_57 30_51
CLBLM_L.SLICEM_X0.FFSYNC 00_48
CLBLM_L.SLICEM_X0.LATCH 30_32
CLBLM_L.SLICEM_X0.PRECYINIT.1 00_12
CLBLM_L.SLICEM_X0.PRECYINIT.AX 30_14
CLBLM_L.SLICEM_X0.PRECYINIT.CIN 30_13
CLBLM_L.SLICEM_X0.SRUSEDMUX 01_35
CLBLM_L.SLICEM_X0.WA7USED 00_40
CLBLM_L.SLICEM_X0.WA8USED 01_27
CLBLM_L.SLICEM_X0.WEMUX.CE 01_23

127
kintex7/segbits_clblm_r.db
View File

@ -1,7 +1,15 @@
CLBLM_R.SLICEL_X1.A5FF.ZINI 31_05
CLBLM_R.SLICEL_X1.A5FF.ZRST 01_03
CLBLM_R.SLICEL_X1.A5FFMUX.IN_A 31_08
CLBLM_R.SLICEL_X1.A5FFMUX.IN_B 31_11
CLBLM_R.SLICEL_X1.AFF.ZINI 31_04
CLBLM_R.SLICEL_X1.AFF.ZRST 31_15
CLBLM_R.SLICEL_X1.AFFMUX.AX !30_04 !31_00 !31_02 31_01
CLBLM_R.SLICEL_X1.AFFMUX.CY !30_04 !31_01 31_00 31_02
CLBLM_R.SLICEL_X1.AFFMUX.F7 !30_04 !31_02 31_00 31_01
CLBLM_R.SLICEL_X1.AFFMUX.O5 !31_01 !31_02 30_04 31_00
CLBLM_R.SLICEL_X1.AFFMUX.O6 !31_00 !31_01 !31_02 30_04
CLBLM_R.SLICEL_X1.AFFMUX.XOR !30_04 !31_00 !31_01 31_02
CLBLM_R.SLICEL_X1.ALUT.INIT[00] 26_15
CLBLM_R.SLICEL_X1.ALUT.INIT[01] 27_15
CLBLM_R.SLICEL_X1.ALUT.INIT[02] 26_14
@ -66,10 +74,23 @@ CLBLM_R.SLICEL_X1.ALUT.INIT[60] 29_01
CLBLM_R.SLICEL_X1.ALUT.INIT[61] 28_01
CLBLM_R.SLICEL_X1.ALUT.INIT[62] 29_00
CLBLM_R.SLICEL_X1.ALUT.INIT[63] 28_00
CLBLM_R.SLICEL_X1.AOUTMUX.A5Q !31_07 !31_09 !31_10 30_05
CLBLM_R.SLICEL_X1.AOUTMUX.CY !30_05 !31_09 31_07 31_10
CLBLM_R.SLICEL_X1.AOUTMUX.F7 !31_07 !31_09 30_05 31_10
CLBLM_R.SLICEL_X1.AOUTMUX.O5 !30_05 !31_07 31_09 31_10
CLBLM_R.SLICEL_X1.AOUTMUX.XOR !30_05 !31_09 !31_10 31_07
CLBLM_R.SLICEL_X1.B5FF.ZINI 31_23
CLBLM_R.SLICEL_X1.B5FF.ZRST 00_16
CLBLM_R.SLICEL_X1.B5FFMUX.IN_A 31_19
CLBLM_R.SLICEL_X1.B5FFMUX.IN_B 31_18
CLBLM_R.SLICEL_X1.BFF.ZINI 31_29
CLBLM_R.SLICEL_X1.BFF.ZRST 31_30
CLBLM_R.SLICEL_X1.BFFMUX.BX !31_24 !31_25 !31_26 31_27
CLBLM_R.SLICEL_X1.BFFMUX.CY !31_24 !31_27 31_25 31_26
CLBLM_R.SLICEL_X1.BFFMUX.F8 !31_24 !31_26 31_25 31_27
CLBLM_R.SLICEL_X1.BFFMUX.O5 !31_26 !31_27 31_24 31_25
CLBLM_R.SLICEL_X1.BFFMUX.O6 !31_25 !31_26 !31_27 31_24
CLBLM_R.SLICEL_X1.BFFMUX.XOR !31_24 !31_25 !31_27 31_26
CLBLM_R.SLICEL_X1.BLUT.INIT[00] 26_31
CLBLM_R.SLICEL_X1.BLUT.INIT[01] 27_31
CLBLM_R.SLICEL_X1.BLUT.INIT[02] 26_30
@ -134,15 +155,31 @@ CLBLM_R.SLICEL_X1.BLUT.INIT[60] 29_17
CLBLM_R.SLICEL_X1.BLUT.INIT[61] 28_17
CLBLM_R.SLICEL_X1.BLUT.INIT[62] 29_16
CLBLM_R.SLICEL_X1.BLUT.INIT[63] 28_16
CLBLM_R.SLICEL_X1.BOUTMUX.B5Q !30_28 !31_20 !31_21 30_29
CLBLM_R.SLICEL_X1.BOUTMUX.CY !30_29 !31_20 30_28 31_21
CLBLM_R.SLICEL_X1.BOUTMUX.F8 !30_28 !31_20 30_29 31_21
CLBLM_R.SLICEL_X1.BOUTMUX.O5 !30_28 !30_29 31_20 31_21
CLBLM_R.SLICEL_X1.BOUTMUX.XOR !30_29 !31_20 !31_21 30_28
CLBLM_R.SLICEL_X1.C5FF.ZINI 31_42
CLBLM_R.SLICEL_X1.C5FF.ZRST 00_44
CLBLM_R.SLICEL_X1.C5FFMUX.IN_A 31_44
CLBLM_R.SLICEL_X1.C5FFMUX.IN_B 31_39
CLBLM_R.SLICEL_X1.CARRY4.ACY0 !30_04 !31_00 !31_02 31_01 31_04 31_14 31_15
CLBLM_R.SLICEL_X1.CARRY4.ACY0 31_14
CLBLM_R.SLICEL_X1.CARRY4.BCY0 !31_24 !31_25 !31_26 00_08 31_27 31_29 31_30
CLBLM_R.SLICEL_X1.CARRY4.BCY0 00_08
CLBLM_R.SLICEL_X1.CARRY4.CCY0 !31_35 !31_36 !31_37 30_34 31_34 31_38 31_48
CLBLM_R.SLICEL_X1.CARRY4.CCY0 31_48
CLBLM_R.SLICEL_X1.CARRY4.DCY0 31_49
CLBLM_R.SLICEL_X1.CEUSEDMUX 00_36
CLBLM_R.SLICEL_X1.CFF.ZINI 31_34
CLBLM_R.SLICEL_X1.CFF.ZRST 30_34
CLBLM_R.SLICEL_X1.CFFMUX.CX !31_35 !31_36 !31_37 31_38
CLBLM_R.SLICEL_X1.CFFMUX.CY !31_36 !31_38 31_35 31_37
CLBLM_R.SLICEL_X1.CFFMUX.F7 !31_36 !31_37 31_35 31_38
CLBLM_R.SLICEL_X1.CFFMUX.O5 !31_37 !31_38 31_35 31_36
CLBLM_R.SLICEL_X1.CFFMUX.O6 !31_35 !31_37 !31_38 31_36
CLBLM_R.SLICEL_X1.CFFMUX.XOR !31_35 !31_36 !31_38 31_37
CLBLM_R.SLICEL_X1.CLKINV 00_52
CLBLM_R.SLICEL_X1.CLUT.INIT[00] 26_47
CLBLM_R.SLICEL_X1.CLUT.INIT[01] 27_47
@ -208,10 +245,22 @@ CLBLM_R.SLICEL_X1.CLUT.INIT[60] 29_33
CLBLM_R.SLICEL_X1.CLUT.INIT[61] 28_33
CLBLM_R.SLICEL_X1.CLUT.INIT[62] 29_32
CLBLM_R.SLICEL_X1.CLUT.INIT[63] 28_32
CLBLM_R.SLICEL_X1.COUTMUX.C5Q !30_42 !31_40 !31_43 30_41
CLBLM_R.SLICEL_X1.COUTMUX.CY !30_41 !31_43 30_42 31_40
CLBLM_R.SLICEL_X1.COUTMUX.F7 !30_42 !31_43 30_41 31_40
CLBLM_R.SLICEL_X1.COUTMUX.O5 !30_41 !30_42 31_40 31_43
CLBLM_R.SLICEL_X1.COUTMUX.XOR !30_41 !31_40 !31_43 30_42
CLBLM_R.SLICEL_X1.D5FF.ZINI 31_52
CLBLM_R.SLICEL_X1.D5FF.ZRST 00_56
CLBLM_R.SLICEL_X1.D5FFMUX.IN_A 31_55
CLBLM_R.SLICEL_X1.D5FFMUX.IN_B 31_54
CLBLM_R.SLICEL_X1.DFF.ZINI 31_59
CLBLM_R.SLICEL_X1.DFF.ZRST 31_50
CLBLM_R.SLICEL_X1.DFFMUX.CY !31_60 !31_61 30_58 31_62
CLBLM_R.SLICEL_X1.DFFMUX.DX !30_58 !31_60 !31_62 31_61
CLBLM_R.SLICEL_X1.DFFMUX.O5 !31_61 !31_62 30_58 31_60
CLBLM_R.SLICEL_X1.DFFMUX.O6 !30_58 !31_61 !31_62 31_60
CLBLM_R.SLICEL_X1.DFFMUX.XOR !30_58 !31_60 !31_61 31_62
CLBLM_R.SLICEL_X1.DLUT.INIT[00] 26_63
CLBLM_R.SLICEL_X1.DLUT.INIT[01] 27_63
CLBLM_R.SLICEL_X1.DLUT.INIT[02] 26_62
@ -276,6 +325,10 @@ CLBLM_R.SLICEL_X1.DLUT.INIT[60] 29_49
CLBLM_R.SLICEL_X1.DLUT.INIT[61] 28_49
CLBLM_R.SLICEL_X1.DLUT.INIT[62] 29_48
CLBLM_R.SLICEL_X1.DLUT.INIT[63] 28_48
CLBLM_R.SLICEL_X1.DOUTMUX.CY !31_53 !31_56 30_53 31_57
CLBLM_R.SLICEL_X1.DOUTMUX.D5Q !30_53 !31_56 !31_57 31_53
CLBLM_R.SLICEL_X1.DOUTMUX.O5 !30_53 !31_53 31_56 31_57
CLBLM_R.SLICEL_X1.DOUTMUX.XOR !31_53 !31_56 !31_57 30_53
CLBLM_R.SLICEL_X1.FFSYNC 01_31
CLBLM_R.SLICEL_X1.LATCH 31_32
CLBLM_R.SLICEL_X1.PRECYINIT.1 01_11
@ -284,8 +337,18 @@ CLBLM_R.SLICEL_X1.PRECYINIT.CIN 31_12
CLBLM_R.SLICEL_X1.SRUSEDMUX 00_32
CLBLM_R.SLICEM_X0.A5FF.ZINI 31_06
CLBLM_R.SLICEM_X0.A5FF.ZRST 01_07
CLBLM_R.SLICEM_X0.A5FFMUX.IN_A 30_09
CLBLM_R.SLICEM_X0.A5FFMUX.IN_B 30_10
CLBLM_R.SLICEM_X0.ADI1MUX.AI !22_00 !23_00 !24_00 00_00 25_00
CLBLM_R.SLICEM_X0.AFF.ZINI 31_03
CLBLM_R.SLICEM_X0.AFF.ZRST 30_12
CLBLM_R.SLICEM_X0.AFFMUX.AX !30_00 !30_02 !30_03 30_01
CLBLM_R.SLICEM_X0.AFFMUX.CY !30_01 !30_03 30_00 30_02
CLBLM_R.SLICEM_X0.AFFMUX.F7 !30_02 !30_03 30_00 30_01
CLBLM_R.SLICEM_X0.AFFMUX.O5 !30_01 !30_02 30_00 30_03
CLBLM_R.SLICEM_X0.AFFMUX.O6 !30_00 !30_01 !30_02 30_03
CLBLM_R.SLICEM_X0.AFFMUX.XOR !30_00 !30_01 !30_03 30_02
CLBLM_R.SLICEM_X0.ALUT.DI1MUX.AI 00_00
CLBLM_R.SLICEM_X0.ALUT.INIT[00] 34_15
CLBLM_R.SLICEM_X0.ALUT.INIT[01] 35_15
CLBLM_R.SLICEM_X0.ALUT.INIT[02] 34_14
@ -350,10 +413,28 @@ CLBLM_R.SLICEM_X0.ALUT.INIT[60] 32_01
CLBLM_R.SLICEM_X0.ALUT.INIT[61] 33_01
CLBLM_R.SLICEM_X0.ALUT.INIT[62] 32_00
CLBLM_R.SLICEM_X0.ALUT.INIT[63] 33_00
CLBLM_R.SLICEM_X0.ALUT.RAM 31_16
CLBLM_R.SLICEM_X0.ALUT.SMALL 00_04
CLBLM_R.SLICEM_X0.ALUT.SRL 30_16
CLBLM_R.SLICEM_X0.AOUTMUX.A5Q !30_06 !30_08 !30_11 30_07
CLBLM_R.SLICEM_X0.AOUTMUX.CY !30_07 !30_11 30_06 30_08
CLBLM_R.SLICEM_X0.AOUTMUX.F7 !30_08 !30_11 30_06 30_07
CLBLM_R.SLICEM_X0.AOUTMUX.O5 !30_07 !30_08 30_06 30_11
CLBLM_R.SLICEM_X0.AOUTMUX.XOR !30_06 !30_07 !30_11 30_08
CLBLM_R.SLICEM_X0.B5FF.ZINI 31_22
CLBLM_R.SLICEM_X0.B5FF.ZRST 01_19
CLBLM_R.SLICEM_X0.B5FFMUX.IN_A 30_19
CLBLM_R.SLICEM_X0.B5FFMUX.IN_B 30_18
CLBLM_R.SLICEM_X0.BDI1MUX.BI 00_20
CLBLM_R.SLICEM_X0.BFF.ZINI 31_28
CLBLM_R.SLICEM_X0.BFF.ZRST 30_30
CLBLM_R.SLICEM_X0.BFFMUX.BX !30_24 !30_25 !30_27 30_26
CLBLM_R.SLICEM_X0.BFFMUX.CY !30_24 !30_26 30_25 30_27
CLBLM_R.SLICEM_X0.BFFMUX.F8 !30_24 !30_25 30_26 30_27
CLBLM_R.SLICEM_X0.BFFMUX.O5 !30_25 !30_26 30_24 30_27
CLBLM_R.SLICEM_X0.BFFMUX.O6 !30_25 !30_26 !30_27 30_24
CLBLM_R.SLICEM_X0.BFFMUX.XOR !30_24 !30_26 !30_27 30_25
CLBLM_R.SLICEM_X0.BLUT.DI1MUX.BI 00_20
CLBLM_R.SLICEM_X0.BLUT.INIT[00] 34_31
CLBLM_R.SLICEM_X0.BLUT.INIT[01] 35_31
CLBLM_R.SLICEM_X0.BLUT.INIT[02] 34_30
@ -418,16 +499,37 @@ CLBLM_R.SLICEM_X0.BLUT.INIT[60] 32_17
CLBLM_R.SLICEM_X0.BLUT.INIT[61] 33_17
CLBLM_R.SLICEM_X0.BLUT.INIT[62] 32_16
CLBLM_R.SLICEM_X0.BLUT.INIT[63] 33_16
CLBLM_R.SLICEM_X0.BLUT.RAM 31_17
CLBLM_R.SLICEM_X0.BLUT.SMALL 00_24
CLBLM_R.SLICEM_X0.BLUT.SRL 30_17
CLBLM_R.SLICEM_X0.BOUTMUX.B5Q !30_20 !30_21 !30_22 30_23
CLBLM_R.SLICEM_X0.BOUTMUX.CY !30_20 !30_23 30_21 30_22
CLBLM_R.SLICEM_X0.BOUTMUX.F8 !30_20 !30_21 30_22 30_23
CLBLM_R.SLICEM_X0.BOUTMUX.O5 !30_21 !30_23 30_20 30_22
CLBLM_R.SLICEM_X0.BOUTMUX.XOR !30_20 !30_22 !30_23 30_21
CLBLM_R.SLICEM_X0.C5FF.ZINI 31_41
CLBLM_R.SLICEM_X0.C5FF.ZRST 01_47
CLBLM_R.SLICEM_X0.C5FFMUX.IN_A 31_45
CLBLM_R.SLICEM_X0.C5FFMUX.IN_B 30_39
CLBLM_R.SLICEM_X0.CARRY4.ACY0 !30_00 !30_02 !30_03 30_01 30_12 30_15 31_03
CLBLM_R.SLICEM_X0.CARRY4.ACY0 30_15
CLBLM_R.SLICEM_X0.CARRY4.BCY0 !30_24 !30_25 !30_27 01_15 30_26 30_30 31_28
CLBLM_R.SLICEM_X0.CARRY4.BCY0 01_15
CLBLM_R.SLICEM_X0.CARRY4.CCY0 !30_35 !30_37 !30_38 30_33 30_36 30_48 31_33
CLBLM_R.SLICEM_X0.CARRY4.CCY0 30_48
CLBLM_R.SLICEM_X0.CARRY4.DCY0 30_49
CLBLM_R.SLICEM_X0.CDI1MUX.CI 01_43
CLBLM_R.SLICEM_X0.CEUSEDMUX 01_39
CLBLM_R.SLICEM_X0.CFF.ZINI 31_33
CLBLM_R.SLICEM_X0.CFF.ZRST 30_33
CLBLM_R.SLICEM_X0.CFFMUX.CX !30_35 !30_37 !30_38 30_36
CLBLM_R.SLICEM_X0.CFFMUX.CY !30_36 !30_38 30_35 30_37
CLBLM_R.SLICEM_X0.CFFMUX.F7 !30_37 !30_38 30_35 30_36
CLBLM_R.SLICEM_X0.CFFMUX.O5 !30_36 !30_37 30_35 30_38
CLBLM_R.SLICEM_X0.CFFMUX.O6 !30_35 !30_36 !30_37 30_38
CLBLM_R.SLICEM_X0.CFFMUX.XOR !30_35 !30_36 !30_38 30_37
CLBLM_R.SLICEM_X0.CLKINV 01_51
CLBLM_R.SLICEM_X0.CLUT.DI1MUX.CI 01_43
CLBLM_R.SLICEM_X0.CLUT.INIT[00] 34_47
CLBLM_R.SLICEM_X0.CLUT.INIT[01] 35_47
CLBLM_R.SLICEM_X0.CLUT.INIT[02] 34_46
@ -492,10 +594,25 @@ CLBLM_R.SLICEM_X0.CLUT.INIT[60] 32_33
CLBLM_R.SLICEM_X0.CLUT.INIT[61] 33_33
CLBLM_R.SLICEM_X0.CLUT.INIT[62] 32_32
CLBLM_R.SLICEM_X0.CLUT.INIT[63] 33_32
CLBLM_R.SLICEM_X0.CLUT.RAM 31_46
CLBLM_R.SLICEM_X0.CLUT.SMALL 00_28
CLBLM_R.SLICEM_X0.CLUT.SRL 30_46
CLBLM_R.SLICEM_X0.COUTMUX.C5Q !30_40 !30_44 !30_45 30_43
CLBLM_R.SLICEM_X0.COUTMUX.CY !30_43 !30_45 30_40 30_44
CLBLM_R.SLICEM_X0.COUTMUX.F7 !30_44 !30_45 30_40 30_43
CLBLM_R.SLICEM_X0.COUTMUX.O5 !30_43 !30_44 30_40 30_45
CLBLM_R.SLICEM_X0.COUTMUX.XOR !30_40 !30_43 !30_45 30_44
CLBLM_R.SLICEM_X0.D5FF.ZINI 31_51
CLBLM_R.SLICEM_X0.D5FF.ZRST 01_55
CLBLM_R.SLICEM_X0.D5FFMUX.IN_A 30_55
CLBLM_R.SLICEM_X0.D5FFMUX.IN_B 30_54
CLBLM_R.SLICEM_X0.DFF.ZINI 31_58
CLBLM_R.SLICEM_X0.DFF.ZRST 30_50
CLBLM_R.SLICEM_X0.DFFMUX.CY !30_59 !30_61 30_60 30_62
CLBLM_R.SLICEM_X0.DFFMUX.DX !30_59 !30_60 !30_62 30_61
CLBLM_R.SLICEM_X0.DFFMUX.O5 !30_60 !30_61 30_59 30_62
CLBLM_R.SLICEM_X0.DFFMUX.O6 !30_60 !30_61 !30_62 30_59
CLBLM_R.SLICEM_X0.DFFMUX.XOR !30_59 !30_61 !30_62 30_60
CLBLM_R.SLICEM_X0.DLUT.INIT[00] 34_63
CLBLM_R.SLICEM_X0.DLUT.INIT[01] 35_63
CLBLM_R.SLICEM_X0.DLUT.INIT[02] 34_62
@ -560,9 +677,19 @@ CLBLM_R.SLICEM_X0.DLUT.INIT[60] 32_49
CLBLM_R.SLICEM_X0.DLUT.INIT[61] 33_49
CLBLM_R.SLICEM_X0.DLUT.INIT[62] 32_48
CLBLM_R.SLICEM_X0.DLUT.INIT[63] 33_48
CLBLM_R.SLICEM_X0.DLUT.RAM 31_47
CLBLM_R.SLICEM_X0.DLUT.SMALL 01_59
CLBLM_R.SLICEM_X0.DLUT.SRL 30_47
CLBLM_R.SLICEM_X0.DOUTMUX.CY !30_56 !30_57 30_51 30_52
CLBLM_R.SLICEM_X0.DOUTMUX.D5Q !30_51 !30_52 !30_56 30_57
CLBLM_R.SLICEM_X0.DOUTMUX.O5 !30_51 !30_57 30_52 30_56
CLBLM_R.SLICEM_X0.DOUTMUX.XOR !30_52 !30_56 !30_57 30_51
CLBLM_R.SLICEM_X0.FFSYNC 00_48
CLBLM_R.SLICEM_X0.LATCH 30_32
CLBLM_R.SLICEM_X0.PRECYINIT.1 00_12
CLBLM_R.SLICEM_X0.PRECYINIT.AX 30_14
CLBLM_R.SLICEM_X0.PRECYINIT.CIN 30_13
CLBLM_R.SLICEM_X0.SRUSEDMUX 01_35
CLBLM_R.SLICEM_X0.WA7USED 00_40
CLBLM_R.SLICEM_X0.WA8USED 01_27
CLBLM_R.SLICEM_X0.WEMUX.CE 01_23

196
kintex7/segbits_hclk_l.db Normal file
View File

@ -0,0 +1,196 @@
HCLK_L.ENABLE_BUFFER.HCLK_CK_BUFHCLK10 00_22
HCLK_L.ENABLE_BUFFER.HCLK_CK_BUFHCLK11 01_22
HCLK_L.ENABLE_BUFFER.HCLK_CK_BUFHCLK8 00_14
HCLK_L.ENABLE_BUFFER.HCLK_CK_BUFHCLK9 01_19
HCLK_L.HCLK_LEAF_CLK_B_BOTL0.HCLK_CK_BUFHCLK10 01_15 04_15
HCLK_L.HCLK_LEAF_CLK_B_BOTL0.HCLK_CK_BUFHCLK11 01_15 03_15
HCLK_L.HCLK_LEAF_CLK_B_BOTL0.HCLK_CK_BUFHCLK8 01_15 04_14
HCLK_L.HCLK_LEAF_CLK_B_BOTL0.HCLK_CK_BUFHCLK9 01_15 03_14
HCLK_L.HCLK_LEAF_CLK_B_BOTL0.HCLK_CK_BUFRCLK0 00_16 04_14
HCLK_L.HCLK_LEAF_CLK_B_BOTL0.HCLK_CK_BUFRCLK1 00_16 03_14
HCLK_L.HCLK_LEAF_CLK_B_BOTL0.HCLK_CK_BUFRCLK2 00_16 04_15
HCLK_L.HCLK_LEAF_CLK_B_BOTL0.HCLK_CK_BUFRCLK3 00_16 03_15
HCLK_L.HCLK_LEAF_CLK_B_BOTL0.HCLK_CK_OUTIN_L0 01_14 04_14
HCLK_L.HCLK_LEAF_CLK_B_BOTL0.HCLK_CK_OUTIN_L1 01_14 03_14
HCLK_L.HCLK_LEAF_CLK_B_BOTL0.HCLK_CK_OUTIN_L2 01_14 04_15
HCLK_L.HCLK_LEAF_CLK_B_BOTL0.HCLK_CK_OUTIN_L3 01_14 03_15
HCLK_L.HCLK_LEAF_CLK_B_BOTL0.HCLK_CK_OUTIN_L4 00_15 04_14
HCLK_L.HCLK_LEAF_CLK_B_BOTL0.HCLK_CK_OUTIN_L5 00_15 03_14
HCLK_L.HCLK_LEAF_CLK_B_BOTL0.HCLK_CK_OUTIN_L6 00_15 04_15
HCLK_L.HCLK_LEAF_CLK_B_BOTL0.HCLK_CK_OUTIN_L7 00_15 03_15
HCLK_L.HCLK_LEAF_CLK_B_BOTL1.HCLK_CK_BUFHCLK10 02_15 04_16
HCLK_L.HCLK_LEAF_CLK_B_BOTL1.HCLK_CK_BUFHCLK11 04_16 05_15
HCLK_L.HCLK_LEAF_CLK_B_BOTL1.HCLK_CK_BUFHCLK8 02_14 04_16
HCLK_L.HCLK_LEAF_CLK_B_BOTL1.HCLK_CK_BUFHCLK9 04_16 05_14
HCLK_L.HCLK_LEAF_CLK_B_BOTL1.HCLK_CK_BUFRCLK0 02_14 02_16
HCLK_L.HCLK_LEAF_CLK_B_BOTL1.HCLK_CK_BUFRCLK1 02_16 05_14
HCLK_L.HCLK_LEAF_CLK_B_BOTL1.HCLK_CK_BUFRCLK2 02_15 02_16
HCLK_L.HCLK_LEAF_CLK_B_BOTL1.HCLK_CK_BUFRCLK3 02_16 05_15
HCLK_L.HCLK_LEAF_CLK_B_BOTL1.HCLK_CK_OUTIN_L0 02_14 03_16
HCLK_L.HCLK_LEAF_CLK_B_BOTL1.HCLK_CK_OUTIN_L1 03_16 05_14
HCLK_L.HCLK_LEAF_CLK_B_BOTL1.HCLK_CK_OUTIN_L2 02_15 03_16
HCLK_L.HCLK_LEAF_CLK_B_BOTL1.HCLK_CK_OUTIN_L3 03_16 05_15
HCLK_L.HCLK_LEAF_CLK_B_BOTL1.HCLK_CK_OUTIN_L4 02_14 05_16
HCLK_L.HCLK_LEAF_CLK_B_BOTL1.HCLK_CK_OUTIN_L5 05_14 05_16
HCLK_L.HCLK_LEAF_CLK_B_BOTL1.HCLK_CK_OUTIN_L6 02_15 05_16
HCLK_L.HCLK_LEAF_CLK_B_BOTL1.HCLK_CK_OUTIN_L7 05_15 05_16
HCLK_L.HCLK_LEAF_CLK_B_BOTL2.HCLK_CK_BUFHCLK10 00_17 05_18
HCLK_L.HCLK_LEAF_CLK_B_BOTL2.HCLK_CK_BUFHCLK11 00_17 02_18
HCLK_L.HCLK_LEAF_CLK_B_BOTL2.HCLK_CK_BUFHCLK8 00_17 05_19
HCLK_L.HCLK_LEAF_CLK_B_BOTL2.HCLK_CK_BUFHCLK9 00_17 02_19
HCLK_L.HCLK_LEAF_CLK_B_BOTL2.HCLK_CK_BUFRCLK0 01_16 05_19
HCLK_L.HCLK_LEAF_CLK_B_BOTL2.HCLK_CK_BUFRCLK1 01_16 02_19
HCLK_L.HCLK_LEAF_CLK_B_BOTL2.HCLK_CK_BUFRCLK2 01_16 05_18
HCLK_L.HCLK_LEAF_CLK_B_BOTL2.HCLK_CK_BUFRCLK3 01_16 02_18
HCLK_L.HCLK_LEAF_CLK_B_BOTL2.HCLK_CK_OUTIN_L0 00_18 05_19
HCLK_L.HCLK_LEAF_CLK_B_BOTL2.HCLK_CK_OUTIN_L1 00_18 02_19
HCLK_L.HCLK_LEAF_CLK_B_BOTL2.HCLK_CK_OUTIN_L2 00_18 05_18
HCLK_L.HCLK_LEAF_CLK_B_BOTL2.HCLK_CK_OUTIN_L3 00_18 02_18
HCLK_L.HCLK_LEAF_CLK_B_BOTL2.HCLK_CK_OUTIN_L4 01_17 05_19
HCLK_L.HCLK_LEAF_CLK_B_BOTL2.HCLK_CK_OUTIN_L5 01_17 02_19
HCLK_L.HCLK_LEAF_CLK_B_BOTL2.HCLK_CK_OUTIN_L6 01_17 05_18
HCLK_L.HCLK_LEAF_CLK_B_BOTL2.HCLK_CK_OUTIN_L7 01_17 02_18
HCLK_L.HCLK_LEAF_CLK_B_BOTL3.HCLK_CK_BUFHCLK10 03_18 05_17
HCLK_L.HCLK_LEAF_CLK_B_BOTL3.HCLK_CK_BUFHCLK11 04_18 05_17
HCLK_L.HCLK_LEAF_CLK_B_BOTL3.HCLK_CK_BUFHCLK8 03_19 05_17
HCLK_L.HCLK_LEAF_CLK_B_BOTL3.HCLK_CK_BUFHCLK9 04_19 05_17
HCLK_L.HCLK_LEAF_CLK_B_BOTL3.HCLK_CK_BUFRCLK0 03_17 03_19
HCLK_L.HCLK_LEAF_CLK_B_BOTL3.HCLK_CK_BUFRCLK1 03_17 04_19
HCLK_L.HCLK_LEAF_CLK_B_BOTL3.HCLK_CK_BUFRCLK2 03_17 03_18
HCLK_L.HCLK_LEAF_CLK_B_BOTL3.HCLK_CK_BUFRCLK3 03_17 04_18
HCLK_L.HCLK_LEAF_CLK_B_BOTL3.HCLK_CK_OUTIN_L0 02_17 03_19
HCLK_L.HCLK_LEAF_CLK_B_BOTL3.HCLK_CK_OUTIN_L1 02_17 04_19
HCLK_L.HCLK_LEAF_CLK_B_BOTL3.HCLK_CK_OUTIN_L2 02_17 03_18
HCLK_L.HCLK_LEAF_CLK_B_BOTL3.HCLK_CK_OUTIN_L3 02_17 04_18
HCLK_L.HCLK_LEAF_CLK_B_BOTL3.HCLK_CK_OUTIN_L4 03_19 04_17
HCLK_L.HCLK_LEAF_CLK_B_BOTL3.HCLK_CK_OUTIN_L5 04_17 04_19
HCLK_L.HCLK_LEAF_CLK_B_BOTL3.HCLK_CK_OUTIN_L6 03_18 04_17
HCLK_L.HCLK_LEAF_CLK_B_BOTL3.HCLK_CK_OUTIN_L7 04_17 04_18
HCLK_L.HCLK_LEAF_CLK_B_BOTL4.HCLK_CK_BUFHCLK10 00_21 04_21
HCLK_L.HCLK_LEAF_CLK_B_BOTL4.HCLK_CK_BUFHCLK11 00_21 03_21
HCLK_L.HCLK_LEAF_CLK_B_BOTL4.HCLK_CK_BUFHCLK8 00_21 04_20
HCLK_L.HCLK_LEAF_CLK_B_BOTL4.HCLK_CK_BUFHCLK9 00_21 03_20
HCLK_L.HCLK_LEAF_CLK_B_BOTL4.HCLK_CK_BUFRCLK0 01_21 04_20
HCLK_L.HCLK_LEAF_CLK_B_BOTL4.HCLK_CK_BUFRCLK1 01_21 03_20
HCLK_L.HCLK_LEAF_CLK_B_BOTL4.HCLK_CK_BUFRCLK2 01_21 04_21
HCLK_L.HCLK_LEAF_CLK_B_BOTL4.HCLK_CK_BUFRCLK3 01_21 03_21
HCLK_L.HCLK_LEAF_CLK_B_BOTL4.HCLK_CK_OUTIN_L0 00_20 04_20
HCLK_L.HCLK_LEAF_CLK_B_BOTL4.HCLK_CK_OUTIN_L1 00_20 03_20
HCLK_L.HCLK_LEAF_CLK_B_BOTL4.HCLK_CK_OUTIN_L2 00_20 04_21
HCLK_L.HCLK_LEAF_CLK_B_BOTL4.HCLK_CK_OUTIN_L3 00_20 03_21
HCLK_L.HCLK_LEAF_CLK_B_BOTL4.HCLK_CK_OUTIN_L4 01_20 04_20
HCLK_L.HCLK_LEAF_CLK_B_BOTL4.HCLK_CK_OUTIN_L5 01_20 03_20
HCLK_L.HCLK_LEAF_CLK_B_BOTL4.HCLK_CK_OUTIN_L6 01_20 04_21
HCLK_L.HCLK_LEAF_CLK_B_BOTL4.HCLK_CK_OUTIN_L7 01_20 03_21
HCLK_L.HCLK_LEAF_CLK_B_BOTL5.HCLK_CK_BUFHCLK10 02_21 04_22
HCLK_L.HCLK_LEAF_CLK_B_BOTL5.HCLK_CK_BUFHCLK11 04_22 05_21
HCLK_L.HCLK_LEAF_CLK_B_BOTL5.HCLK_CK_BUFHCLK8 02_20 04_22
HCLK_L.HCLK_LEAF_CLK_B_BOTL5.HCLK_CK_BUFHCLK9 04_22 05_20
HCLK_L.HCLK_LEAF_CLK_B_BOTL5.HCLK_CK_BUFRCLK0 02_20 02_22
HCLK_L.HCLK_LEAF_CLK_B_BOTL5.HCLK_CK_BUFRCLK1 02_22 05_20
HCLK_L.HCLK_LEAF_CLK_B_BOTL5.HCLK_CK_BUFRCLK2 02_21 02_22
HCLK_L.HCLK_LEAF_CLK_B_BOTL5.HCLK_CK_BUFRCLK3 02_22 05_21
HCLK_L.HCLK_LEAF_CLK_B_BOTL5.HCLK_CK_OUTIN_L0 02_20 03_22
HCLK_L.HCLK_LEAF_CLK_B_BOTL5.HCLK_CK_OUTIN_L1 03_22 05_20
HCLK_L.HCLK_LEAF_CLK_B_BOTL5.HCLK_CK_OUTIN_L2 02_21 03_22
HCLK_L.HCLK_LEAF_CLK_B_BOTL5.HCLK_CK_OUTIN_L3 03_22 05_21
HCLK_L.HCLK_LEAF_CLK_B_BOTL5.HCLK_CK_OUTIN_L4 02_20 05_22
HCLK_L.HCLK_LEAF_CLK_B_BOTL5.HCLK_CK_OUTIN_L5 05_20 05_22
HCLK_L.HCLK_LEAF_CLK_B_BOTL5.HCLK_CK_OUTIN_L6 02_21 05_22
HCLK_L.HCLK_LEAF_CLK_B_BOTL5.HCLK_CK_OUTIN_L7 05_21 05_22
HCLK_L.HCLK_LEAF_CLK_B_TOPL0.HCLK_CK_BUFHCLK10 01_29 05_30
HCLK_L.HCLK_LEAF_CLK_B_TOPL0.HCLK_CK_BUFHCLK11 01_29 02_30
HCLK_L.HCLK_LEAF_CLK_B_TOPL0.HCLK_CK_BUFHCLK8 01_29 05_31
HCLK_L.HCLK_LEAF_CLK_B_TOPL0.HCLK_CK_BUFHCLK9 01_29 02_31
HCLK_L.HCLK_LEAF_CLK_B_TOPL0.HCLK_CK_BUFRCLK0 00_29 05_31
HCLK_L.HCLK_LEAF_CLK_B_TOPL0.HCLK_CK_BUFRCLK1 00_29 02_31
HCLK_L.HCLK_LEAF_CLK_B_TOPL0.HCLK_CK_BUFRCLK2 00_29 05_30
HCLK_L.HCLK_LEAF_CLK_B_TOPL0.HCLK_CK_BUFRCLK3 00_29 02_30
HCLK_L.HCLK_LEAF_CLK_B_TOPL0.HCLK_CK_OUTIN_L0 01_30 05_31
HCLK_L.HCLK_LEAF_CLK_B_TOPL0.HCLK_CK_OUTIN_L1 01_30 02_31
HCLK_L.HCLK_LEAF_CLK_B_TOPL0.HCLK_CK_OUTIN_L2 01_30 05_30
HCLK_L.HCLK_LEAF_CLK_B_TOPL0.HCLK_CK_OUTIN_L3 01_30 02_30
HCLK_L.HCLK_LEAF_CLK_B_TOPL0.HCLK_CK_OUTIN_L4 00_30 05_31
HCLK_L.HCLK_LEAF_CLK_B_TOPL0.HCLK_CK_OUTIN_L5 00_30 02_31
HCLK_L.HCLK_LEAF_CLK_B_TOPL0.HCLK_CK_OUTIN_L6 00_30 05_30
HCLK_L.HCLK_LEAF_CLK_B_TOPL0.HCLK_CK_OUTIN_L7 00_30 02_30
HCLK_L.HCLK_LEAF_CLK_B_TOPL1.HCLK_CK_BUFHCLK10 03_30 05_29
HCLK_L.HCLK_LEAF_CLK_B_TOPL1.HCLK_CK_BUFHCLK11 04_30 05_29
HCLK_L.HCLK_LEAF_CLK_B_TOPL1.HCLK_CK_BUFHCLK8 03_31 05_29
HCLK_L.HCLK_LEAF_CLK_B_TOPL1.HCLK_CK_BUFHCLK9 04_31 05_29
HCLK_L.HCLK_LEAF_CLK_B_TOPL1.HCLK_CK_BUFRCLK0 03_29 03_31
HCLK_L.HCLK_LEAF_CLK_B_TOPL1.HCLK_CK_BUFRCLK1 03_29 04_31
HCLK_L.HCLK_LEAF_CLK_B_TOPL1.HCLK_CK_BUFRCLK2 03_29 03_30
HCLK_L.HCLK_LEAF_CLK_B_TOPL1.HCLK_CK_BUFRCLK3 03_29 04_30
HCLK_L.HCLK_LEAF_CLK_B_TOPL1.HCLK_CK_OUTIN_L0 02_29 03_31
HCLK_L.HCLK_LEAF_CLK_B_TOPL1.HCLK_CK_OUTIN_L1 02_29 04_31
HCLK_L.HCLK_LEAF_CLK_B_TOPL1.HCLK_CK_OUTIN_L2 02_29 03_30
HCLK_L.HCLK_LEAF_CLK_B_TOPL1.HCLK_CK_OUTIN_L3 02_29 04_30
HCLK_L.HCLK_LEAF_CLK_B_TOPL1.HCLK_CK_OUTIN_L4 03_31 04_29
HCLK_L.HCLK_LEAF_CLK_B_TOPL1.HCLK_CK_OUTIN_L5 04_29 04_31
HCLK_L.HCLK_LEAF_CLK_B_TOPL1.HCLK_CK_OUTIN_L6 03_30 04_29
HCLK_L.HCLK_LEAF_CLK_B_TOPL1.HCLK_CK_OUTIN_L7 04_29 04_30
HCLK_L.HCLK_LEAF_CLK_B_TOPL2.HCLK_CK_BUFHCLK10 00_28 04_27
HCLK_L.HCLK_LEAF_CLK_B_TOPL2.HCLK_CK_BUFHCLK11 00_28 03_27
HCLK_L.HCLK_LEAF_CLK_B_TOPL2.HCLK_CK_BUFHCLK8 00_28 04_26
HCLK_L.HCLK_LEAF_CLK_B_TOPL2.HCLK_CK_BUFHCLK9 00_28 03_26
HCLK_L.HCLK_LEAF_CLK_B_TOPL2.HCLK_CK_BUFRCLK0 01_28 04_26
HCLK_L.HCLK_LEAF_CLK_B_TOPL2.HCLK_CK_BUFRCLK1 01_28 03_26
HCLK_L.HCLK_LEAF_CLK_B_TOPL2.HCLK_CK_BUFRCLK2 01_28 04_27
HCLK_L.HCLK_LEAF_CLK_B_TOPL2.HCLK_CK_BUFRCLK3 01_28 03_27
HCLK_L.HCLK_LEAF_CLK_B_TOPL2.HCLK_CK_OUTIN_L0 00_26 04_26
HCLK_L.HCLK_LEAF_CLK_B_TOPL2.HCLK_CK_OUTIN_L1 00_26 03_26
HCLK_L.HCLK_LEAF_CLK_B_TOPL2.HCLK_CK_OUTIN_L2 00_26 04_27
HCLK_L.HCLK_LEAF_CLK_B_TOPL2.HCLK_CK_OUTIN_L3 00_26 03_27
HCLK_L.HCLK_LEAF_CLK_B_TOPL2.HCLK_CK_OUTIN_L4 01_26 04_26
HCLK_L.HCLK_LEAF_CLK_B_TOPL2.HCLK_CK_OUTIN_L5 01_26 03_26
HCLK_L.HCLK_LEAF_CLK_B_TOPL2.HCLK_CK_OUTIN_L6 01_26 04_27
HCLK_L.HCLK_LEAF_CLK_B_TOPL2.HCLK_CK_OUTIN_L7 01_26 03_27
HCLK_L.HCLK_LEAF_CLK_B_TOPL3.HCLK_CK_BUFHCLK10 02_27 04_28
HCLK_L.HCLK_LEAF_CLK_B_TOPL3.HCLK_CK_BUFHCLK11 04_28 05_27
HCLK_L.HCLK_LEAF_CLK_B_TOPL3.HCLK_CK_BUFHCLK8 02_26 04_28
HCLK_L.HCLK_LEAF_CLK_B_TOPL3.HCLK_CK_BUFHCLK9 04_28 05_26
HCLK_L.HCLK_LEAF_CLK_B_TOPL3.HCLK_CK_BUFRCLK0 02_26 02_28
HCLK_L.HCLK_LEAF_CLK_B_TOPL3.HCLK_CK_BUFRCLK1 02_28 05_26
HCLK_L.HCLK_LEAF_CLK_B_TOPL3.HCLK_CK_BUFRCLK2 02_27 02_28
HCLK_L.HCLK_LEAF_CLK_B_TOPL3.HCLK_CK_BUFRCLK3 02_28 05_27
HCLK_L.HCLK_LEAF_CLK_B_TOPL3.HCLK_CK_OUTIN_L0 02_26 03_28
HCLK_L.HCLK_LEAF_CLK_B_TOPL3.HCLK_CK_OUTIN_L1 03_28 05_26
HCLK_L.HCLK_LEAF_CLK_B_TOPL3.HCLK_CK_OUTIN_L2 02_27 03_28
HCLK_L.HCLK_LEAF_CLK_B_TOPL3.HCLK_CK_OUTIN_L3 03_28 05_27
HCLK_L.HCLK_LEAF_CLK_B_TOPL3.HCLK_CK_OUTIN_L4 02_26 05_28
HCLK_L.HCLK_LEAF_CLK_B_TOPL3.HCLK_CK_OUTIN_L5 05_26 05_28
HCLK_L.HCLK_LEAF_CLK_B_TOPL3.HCLK_CK_OUTIN_L6 02_27 05_28
HCLK_L.HCLK_LEAF_CLK_B_TOPL3.HCLK_CK_OUTIN_L7 05_27 05_28
HCLK_L.HCLK_LEAF_CLK_B_TOPL4.HCLK_CK_BUFHCLK10 01_24 05_24
HCLK_L.HCLK_LEAF_CLK_B_TOPL4.HCLK_CK_BUFHCLK11 01_24 02_24
HCLK_L.HCLK_LEAF_CLK_B_TOPL4.HCLK_CK_BUFHCLK8 01_24 05_25
HCLK_L.HCLK_LEAF_CLK_B_TOPL4.HCLK_CK_BUFHCLK9 01_24 02_25
HCLK_L.HCLK_LEAF_CLK_B_TOPL4.HCLK_CK_BUFRCLK0 00_24 05_25
HCLK_L.HCLK_LEAF_CLK_B_TOPL4.HCLK_CK_BUFRCLK1 00_24 02_25
HCLK_L.HCLK_LEAF_CLK_B_TOPL4.HCLK_CK_BUFRCLK2 00_24 05_24
HCLK_L.HCLK_LEAF_CLK_B_TOPL4.HCLK_CK_BUFRCLK3 00_24 02_24
HCLK_L.HCLK_LEAF_CLK_B_TOPL4.HCLK_CK_OUTIN_L0 01_25 05_25
HCLK_L.HCLK_LEAF_CLK_B_TOPL4.HCLK_CK_OUTIN_L1 01_25 02_25
HCLK_L.HCLK_LEAF_CLK_B_TOPL4.HCLK_CK_OUTIN_L2 01_25 05_24
HCLK_L.HCLK_LEAF_CLK_B_TOPL4.HCLK_CK_OUTIN_L3 01_25 02_24
HCLK_L.HCLK_LEAF_CLK_B_TOPL4.HCLK_CK_OUTIN_L4 00_25 05_25
HCLK_L.HCLK_LEAF_CLK_B_TOPL4.HCLK_CK_OUTIN_L5 00_25 02_25
HCLK_L.HCLK_LEAF_CLK_B_TOPL4.HCLK_CK_OUTIN_L6 00_25 05_24
HCLK_L.HCLK_LEAF_CLK_B_TOPL4.HCLK_CK_OUTIN_L7 00_25 02_24
HCLK_L.HCLK_LEAF_CLK_B_TOPL5.HCLK_CK_BUFHCLK10 03_24 05_23
HCLK_L.HCLK_LEAF_CLK_B_TOPL5.HCLK_CK_BUFHCLK11 04_24 05_23
HCLK_L.HCLK_LEAF_CLK_B_TOPL5.HCLK_CK_BUFHCLK8 03_25 05_23
HCLK_L.HCLK_LEAF_CLK_B_TOPL5.HCLK_CK_BUFHCLK9 04_25 05_23
HCLK_L.HCLK_LEAF_CLK_B_TOPL5.HCLK_CK_BUFRCLK0 03_23 03_25
HCLK_L.HCLK_LEAF_CLK_B_TOPL5.HCLK_CK_BUFRCLK1 03_23 04_25
HCLK_L.HCLK_LEAF_CLK_B_TOPL5.HCLK_CK_BUFRCLK2 03_23 03_24
HCLK_L.HCLK_LEAF_CLK_B_TOPL5.HCLK_CK_BUFRCLK3 03_23 04_24
HCLK_L.HCLK_LEAF_CLK_B_TOPL5.HCLK_CK_OUTIN_L0 02_23 03_25
HCLK_L.HCLK_LEAF_CLK_B_TOPL5.HCLK_CK_OUTIN_L1 02_23 04_25
HCLK_L.HCLK_LEAF_CLK_B_TOPL5.HCLK_CK_OUTIN_L2 02_23 03_24
HCLK_L.HCLK_LEAF_CLK_B_TOPL5.HCLK_CK_OUTIN_L3 02_23 04_24
HCLK_L.HCLK_LEAF_CLK_B_TOPL5.HCLK_CK_OUTIN_L4 03_25 04_23
HCLK_L.HCLK_LEAF_CLK_B_TOPL5.HCLK_CK_OUTIN_L5 04_23 04_25
HCLK_L.HCLK_LEAF_CLK_B_TOPL5.HCLK_CK_OUTIN_L6 03_24 04_23
HCLK_L.HCLK_LEAF_CLK_B_TOPL5.HCLK_CK_OUTIN_L7 04_23 04_24

200
kintex7/segbits_hclk_r.db Normal file
View File

@ -0,0 +1,200 @@
HCLK_R.ENABLE_BUFFER.HCLK_CK_BUFHCLK0 00_14
HCLK_R.ENABLE_BUFFER.HCLK_CK_BUFHCLK1 01_19
HCLK_R.ENABLE_BUFFER.HCLK_CK_BUFHCLK2 00_22
HCLK_R.ENABLE_BUFFER.HCLK_CK_BUFHCLK3 01_22
HCLK_R.ENABLE_BUFFER.HCLK_CK_BUFHCLK4 00_23
HCLK_R.ENABLE_BUFFER.HCLK_CK_BUFHCLK5 01_23
HCLK_R.ENABLE_BUFFER.HCLK_CK_BUFHCLK6 00_31
HCLK_R.ENABLE_BUFFER.HCLK_CK_BUFHCLK7 01_31
HCLK_R.HCLK_LEAF_CLK_B_BOT0.HCLK_CK_BUFHCLK0 01_14 04_14
HCLK_R.HCLK_LEAF_CLK_B_BOT0.HCLK_CK_BUFHCLK1 01_14 03_14
HCLK_R.HCLK_LEAF_CLK_B_BOT0.HCLK_CK_BUFHCLK2 01_14 04_15
HCLK_R.HCLK_LEAF_CLK_B_BOT0.HCLK_CK_BUFHCLK3 01_14 03_15
HCLK_R.HCLK_LEAF_CLK_B_BOT0.HCLK_CK_BUFHCLK4 00_15 04_14
HCLK_R.HCLK_LEAF_CLK_B_BOT0.HCLK_CK_BUFHCLK5 00_15 03_14
HCLK_R.HCLK_LEAF_CLK_B_BOT0.HCLK_CK_BUFHCLK6 00_15 04_15
HCLK_R.HCLK_LEAF_CLK_B_BOT0.HCLK_CK_BUFHCLK7 00_15 03_15
HCLK_R.HCLK_LEAF_CLK_B_BOT0.HCLK_CK_OUTIN_R0 00_16 04_14
HCLK_R.HCLK_LEAF_CLK_B_BOT0.HCLK_CK_OUTIN_R1 00_16 03_14
HCLK_R.HCLK_LEAF_CLK_B_BOT0.HCLK_CK_OUTIN_R2 00_16 04_15
HCLK_R.HCLK_LEAF_CLK_B_BOT0.HCLK_CK_OUTIN_R3 00_16 03_15
HCLK_R.HCLK_LEAF_CLK_B_BOT0.HCLK_CK_OUTIN_R4 01_15 04_14
HCLK_R.HCLK_LEAF_CLK_B_BOT0.HCLK_CK_OUTIN_R5 01_15 03_14
HCLK_R.HCLK_LEAF_CLK_B_BOT0.HCLK_CK_OUTIN_R6 01_15 04_15
HCLK_R.HCLK_LEAF_CLK_B_BOT0.HCLK_CK_OUTIN_R7 01_15 03_15
HCLK_R.HCLK_LEAF_CLK_B_BOT1.HCLK_CK_BUFHCLK0 02_14 03_16
HCLK_R.HCLK_LEAF_CLK_B_BOT1.HCLK_CK_BUFHCLK1 03_16 05_14
HCLK_R.HCLK_LEAF_CLK_B_BOT1.HCLK_CK_BUFHCLK2 02_15 03_16
HCLK_R.HCLK_LEAF_CLK_B_BOT1.HCLK_CK_BUFHCLK3 03_16 05_15
HCLK_R.HCLK_LEAF_CLK_B_BOT1.HCLK_CK_BUFHCLK4 02_14 05_16
HCLK_R.HCLK_LEAF_CLK_B_BOT1.HCLK_CK_BUFHCLK5 05_14 05_16
HCLK_R.HCLK_LEAF_CLK_B_BOT1.HCLK_CK_BUFHCLK6 02_15 05_16
HCLK_R.HCLK_LEAF_CLK_B_BOT1.HCLK_CK_BUFHCLK7 05_15 05_16
HCLK_R.HCLK_LEAF_CLK_B_BOT1.HCLK_CK_OUTIN_R0 02_14 02_16
HCLK_R.HCLK_LEAF_CLK_B_BOT1.HCLK_CK_OUTIN_R1 02_16 05_14
HCLK_R.HCLK_LEAF_CLK_B_BOT1.HCLK_CK_OUTIN_R2 02_15 02_16
HCLK_R.HCLK_LEAF_CLK_B_BOT1.HCLK_CK_OUTIN_R3 02_16 05_15
HCLK_R.HCLK_LEAF_CLK_B_BOT1.HCLK_CK_OUTIN_R4 02_14 04_16
HCLK_R.HCLK_LEAF_CLK_B_BOT1.HCLK_CK_OUTIN_R5 04_16 05_14
HCLK_R.HCLK_LEAF_CLK_B_BOT1.HCLK_CK_OUTIN_R6 02_15 04_16
HCLK_R.HCLK_LEAF_CLK_B_BOT1.HCLK_CK_OUTIN_R7 04_16 05_15
HCLK_R.HCLK_LEAF_CLK_B_BOT2.HCLK_CK_BUFHCLK0 00_18 05_19
HCLK_R.HCLK_LEAF_CLK_B_BOT2.HCLK_CK_BUFHCLK1 00_18 02_19
HCLK_R.HCLK_LEAF_CLK_B_BOT2.HCLK_CK_BUFHCLK2 00_18 05_18
HCLK_R.HCLK_LEAF_CLK_B_BOT2.HCLK_CK_BUFHCLK3 00_18 02_18
HCLK_R.HCLK_LEAF_CLK_B_BOT2.HCLK_CK_BUFHCLK4 01_17 05_19
HCLK_R.HCLK_LEAF_CLK_B_BOT2.HCLK_CK_BUFHCLK5 01_17 02_19
HCLK_R.HCLK_LEAF_CLK_B_BOT2.HCLK_CK_BUFHCLK6 01_17 05_18
HCLK_R.HCLK_LEAF_CLK_B_BOT2.HCLK_CK_BUFHCLK7 01_17 02_18
HCLK_R.HCLK_LEAF_CLK_B_BOT2.HCLK_CK_OUTIN_R0 01_16 05_19
HCLK_R.HCLK_LEAF_CLK_B_BOT2.HCLK_CK_OUTIN_R1 01_16 02_19
HCLK_R.HCLK_LEAF_CLK_B_BOT2.HCLK_CK_OUTIN_R2 01_16 05_18
HCLK_R.HCLK_LEAF_CLK_B_BOT2.HCLK_CK_OUTIN_R3 01_16 02_18
HCLK_R.HCLK_LEAF_CLK_B_BOT2.HCLK_CK_OUTIN_R4 00_17 05_19
HCLK_R.HCLK_LEAF_CLK_B_BOT2.HCLK_CK_OUTIN_R5 00_17 02_19
HCLK_R.HCLK_LEAF_CLK_B_BOT2.HCLK_CK_OUTIN_R6 00_17 05_18
HCLK_R.HCLK_LEAF_CLK_B_BOT2.HCLK_CK_OUTIN_R7 00_17 02_18
HCLK_R.HCLK_LEAF_CLK_B_BOT3.HCLK_CK_BUFHCLK0 02_17 03_19
HCLK_R.HCLK_LEAF_CLK_B_BOT3.HCLK_CK_BUFHCLK1 02_17 04_19
HCLK_R.HCLK_LEAF_CLK_B_BOT3.HCLK_CK_BUFHCLK2 02_17 03_18
HCLK_R.HCLK_LEAF_CLK_B_BOT3.HCLK_CK_BUFHCLK3 02_17 04_18
HCLK_R.HCLK_LEAF_CLK_B_BOT3.HCLK_CK_BUFHCLK4 03_19 04_17
HCLK_R.HCLK_LEAF_CLK_B_BOT3.HCLK_CK_BUFHCLK5 04_17 04_19
HCLK_R.HCLK_LEAF_CLK_B_BOT3.HCLK_CK_BUFHCLK6 03_18 04_17
HCLK_R.HCLK_LEAF_CLK_B_BOT3.HCLK_CK_BUFHCLK7 04_17 04_18
HCLK_R.HCLK_LEAF_CLK_B_BOT3.HCLK_CK_OUTIN_R0 03_17 03_19
HCLK_R.HCLK_LEAF_CLK_B_BOT3.HCLK_CK_OUTIN_R1 03_17 04_19
HCLK_R.HCLK_LEAF_CLK_B_BOT3.HCLK_CK_OUTIN_R2 03_17 03_18
HCLK_R.HCLK_LEAF_CLK_B_BOT3.HCLK_CK_OUTIN_R3 03_17 04_18
HCLK_R.HCLK_LEAF_CLK_B_BOT3.HCLK_CK_OUTIN_R4 03_19 05_17
HCLK_R.HCLK_LEAF_CLK_B_BOT3.HCLK_CK_OUTIN_R5 04_19 05_17
HCLK_R.HCLK_LEAF_CLK_B_BOT3.HCLK_CK_OUTIN_R6 03_18 05_17
HCLK_R.HCLK_LEAF_CLK_B_BOT3.HCLK_CK_OUTIN_R7 04_18 05_17
HCLK_R.HCLK_LEAF_CLK_B_BOT4.HCLK_CK_BUFHCLK0 00_20 04_20
HCLK_R.HCLK_LEAF_CLK_B_BOT4.HCLK_CK_BUFHCLK1 00_20 03_20
HCLK_R.HCLK_LEAF_CLK_B_BOT4.HCLK_CK_BUFHCLK2 00_20 04_21
HCLK_R.HCLK_LEAF_CLK_B_BOT4.HCLK_CK_BUFHCLK3 00_20 03_21
HCLK_R.HCLK_LEAF_CLK_B_BOT4.HCLK_CK_BUFHCLK4 01_20 04_20
HCLK_R.HCLK_LEAF_CLK_B_BOT4.HCLK_CK_BUFHCLK5 01_20 03_20
HCLK_R.HCLK_LEAF_CLK_B_BOT4.HCLK_CK_BUFHCLK6 01_20 04_21
HCLK_R.HCLK_LEAF_CLK_B_BOT4.HCLK_CK_BUFHCLK7 01_20 03_21
HCLK_R.HCLK_LEAF_CLK_B_BOT4.HCLK_CK_OUTIN_R0 01_21 04_20
HCLK_R.HCLK_LEAF_CLK_B_BOT4.HCLK_CK_OUTIN_R1 01_21 03_20
HCLK_R.HCLK_LEAF_CLK_B_BOT4.HCLK_CK_OUTIN_R2 01_21 04_21
HCLK_R.HCLK_LEAF_CLK_B_BOT4.HCLK_CK_OUTIN_R3 01_21 03_21
HCLK_R.HCLK_LEAF_CLK_B_BOT4.HCLK_CK_OUTIN_R4 00_21 04_20
HCLK_R.HCLK_LEAF_CLK_B_BOT4.HCLK_CK_OUTIN_R5 00_21 03_20
HCLK_R.HCLK_LEAF_CLK_B_BOT4.HCLK_CK_OUTIN_R6 00_21 04_21
HCLK_R.HCLK_LEAF_CLK_B_BOT4.HCLK_CK_OUTIN_R7 00_21 03_21
HCLK_R.HCLK_LEAF_CLK_B_BOT5.HCLK_CK_BUFHCLK0 02_20 03_22
HCLK_R.HCLK_LEAF_CLK_B_BOT5.HCLK_CK_BUFHCLK1 03_22 05_20
HCLK_R.HCLK_LEAF_CLK_B_BOT5.HCLK_CK_BUFHCLK2 02_21 03_22
HCLK_R.HCLK_LEAF_CLK_B_BOT5.HCLK_CK_BUFHCLK3 03_22 05_21
HCLK_R.HCLK_LEAF_CLK_B_BOT5.HCLK_CK_BUFHCLK4 02_20 05_22
HCLK_R.HCLK_LEAF_CLK_B_BOT5.HCLK_CK_BUFHCLK5 05_20 05_22
HCLK_R.HCLK_LEAF_CLK_B_BOT5.HCLK_CK_BUFHCLK6 02_21 05_22
HCLK_R.HCLK_LEAF_CLK_B_BOT5.HCLK_CK_BUFHCLK7 05_21 05_22
HCLK_R.HCLK_LEAF_CLK_B_BOT5.HCLK_CK_OUTIN_R0 02_20 02_22
HCLK_R.HCLK_LEAF_CLK_B_BOT5.HCLK_CK_OUTIN_R1 02_22 05_20
HCLK_R.HCLK_LEAF_CLK_B_BOT5.HCLK_CK_OUTIN_R2 02_21 02_22
HCLK_R.HCLK_LEAF_CLK_B_BOT5.HCLK_CK_OUTIN_R3 02_22 05_21
HCLK_R.HCLK_LEAF_CLK_B_BOT5.HCLK_CK_OUTIN_R4 02_20 04_22
HCLK_R.HCLK_LEAF_CLK_B_BOT5.HCLK_CK_OUTIN_R5 04_22 05_20
HCLK_R.HCLK_LEAF_CLK_B_BOT5.HCLK_CK_OUTIN_R6 02_21 04_22
HCLK_R.HCLK_LEAF_CLK_B_BOT5.HCLK_CK_OUTIN_R7 04_22 05_21
HCLK_R.HCLK_LEAF_CLK_B_TOP0.HCLK_CK_BUFHCLK0 01_30 05_31
HCLK_R.HCLK_LEAF_CLK_B_TOP0.HCLK_CK_BUFHCLK1 01_30 02_31
HCLK_R.HCLK_LEAF_CLK_B_TOP0.HCLK_CK_BUFHCLK2 01_30 05_30
HCLK_R.HCLK_LEAF_CLK_B_TOP0.HCLK_CK_BUFHCLK3 01_30 02_30
HCLK_R.HCLK_LEAF_CLK_B_TOP0.HCLK_CK_BUFHCLK4 00_30 05_31
HCLK_R.HCLK_LEAF_CLK_B_TOP0.HCLK_CK_BUFHCLK5 00_30 02_31
HCLK_R.HCLK_LEAF_CLK_B_TOP0.HCLK_CK_BUFHCLK6 00_30 05_30
HCLK_R.HCLK_LEAF_CLK_B_TOP0.HCLK_CK_BUFHCLK7 00_30 02_30
HCLK_R.HCLK_LEAF_CLK_B_TOP0.HCLK_CK_OUTIN_R0 00_29 05_31
HCLK_R.HCLK_LEAF_CLK_B_TOP0.HCLK_CK_OUTIN_R1 00_29 02_31
HCLK_R.HCLK_LEAF_CLK_B_TOP0.HCLK_CK_OUTIN_R2 00_29 05_30
HCLK_R.HCLK_LEAF_CLK_B_TOP0.HCLK_CK_OUTIN_R3 00_29 02_30
HCLK_R.HCLK_LEAF_CLK_B_TOP0.HCLK_CK_OUTIN_R4 01_29 05_31
HCLK_R.HCLK_LEAF_CLK_B_TOP0.HCLK_CK_OUTIN_R5 01_29 02_31
HCLK_R.HCLK_LEAF_CLK_B_TOP0.HCLK_CK_OUTIN_R6 01_29 05_30
HCLK_R.HCLK_LEAF_CLK_B_TOP0.HCLK_CK_OUTIN_R7 01_29 02_30
HCLK_R.HCLK_LEAF_CLK_B_TOP1.HCLK_CK_BUFHCLK0 02_29 03_31
HCLK_R.HCLK_LEAF_CLK_B_TOP1.HCLK_CK_BUFHCLK1 02_29 04_31
HCLK_R.HCLK_LEAF_CLK_B_TOP1.HCLK_CK_BUFHCLK2 02_29 03_30
HCLK_R.HCLK_LEAF_CLK_B_TOP1.HCLK_CK_BUFHCLK3 02_29 04_30
HCLK_R.HCLK_LEAF_CLK_B_TOP1.HCLK_CK_BUFHCLK4 03_31 04_29
HCLK_R.HCLK_LEAF_CLK_B_TOP1.HCLK_CK_BUFHCLK5 04_29 04_31
HCLK_R.HCLK_LEAF_CLK_B_TOP1.HCLK_CK_BUFHCLK6 03_30 04_29
HCLK_R.HCLK_LEAF_CLK_B_TOP1.HCLK_CK_BUFHCLK7 04_29 04_30
HCLK_R.HCLK_LEAF_CLK_B_TOP1.HCLK_CK_OUTIN_R0 03_29 03_31
HCLK_R.HCLK_LEAF_CLK_B_TOP1.HCLK_CK_OUTIN_R1 03_29 04_31
HCLK_R.HCLK_LEAF_CLK_B_TOP1.HCLK_CK_OUTIN_R2 03_29 03_30
HCLK_R.HCLK_LEAF_CLK_B_TOP1.HCLK_CK_OUTIN_R3 03_29 04_30
HCLK_R.HCLK_LEAF_CLK_B_TOP1.HCLK_CK_OUTIN_R4 03_31 05_29
HCLK_R.HCLK_LEAF_CLK_B_TOP1.HCLK_CK_OUTIN_R5 04_31 05_29
HCLK_R.HCLK_LEAF_CLK_B_TOP1.HCLK_CK_OUTIN_R6 03_30 05_29
HCLK_R.HCLK_LEAF_CLK_B_TOP1.HCLK_CK_OUTIN_R7 04_30 05_29
HCLK_R.HCLK_LEAF_CLK_B_TOP2.HCLK_CK_BUFHCLK0 00_26 04_26
HCLK_R.HCLK_LEAF_CLK_B_TOP2.HCLK_CK_BUFHCLK1 00_26 03_26
HCLK_R.HCLK_LEAF_CLK_B_TOP2.HCLK_CK_BUFHCLK2 00_26 04_27
HCLK_R.HCLK_LEAF_CLK_B_TOP2.HCLK_CK_BUFHCLK3 00_26 03_27
HCLK_R.HCLK_LEAF_CLK_B_TOP2.HCLK_CK_BUFHCLK4 01_26 04_26
HCLK_R.HCLK_LEAF_CLK_B_TOP2.HCLK_CK_BUFHCLK5 01_26 03_26
HCLK_R.HCLK_LEAF_CLK_B_TOP2.HCLK_CK_BUFHCLK6 01_26 04_27
HCLK_R.HCLK_LEAF_CLK_B_TOP2.HCLK_CK_BUFHCLK7 01_26 03_27
HCLK_R.HCLK_LEAF_CLK_B_TOP2.HCLK_CK_OUTIN_R0 01_28 04_26
HCLK_R.HCLK_LEAF_CLK_B_TOP2.HCLK_CK_OUTIN_R1 01_28 03_26
HCLK_R.HCLK_LEAF_CLK_B_TOP2.HCLK_CK_OUTIN_R2 01_28 04_27
HCLK_R.HCLK_LEAF_CLK_B_TOP2.HCLK_CK_OUTIN_R3 01_28 03_27
HCLK_R.HCLK_LEAF_CLK_B_TOP2.HCLK_CK_OUTIN_R4 00_28 04_26
HCLK_R.HCLK_LEAF_CLK_B_TOP2.HCLK_CK_OUTIN_R5 00_28 03_26
HCLK_R.HCLK_LEAF_CLK_B_TOP2.HCLK_CK_OUTIN_R6 00_28 04_27
HCLK_R.HCLK_LEAF_CLK_B_TOP2.HCLK_CK_OUTIN_R7 00_28 03_27
HCLK_R.HCLK_LEAF_CLK_B_TOP3.HCLK_CK_BUFHCLK0 02_26 03_28
HCLK_R.HCLK_LEAF_CLK_B_TOP3.HCLK_CK_BUFHCLK1 03_28 05_26
HCLK_R.HCLK_LEAF_CLK_B_TOP3.HCLK_CK_BUFHCLK2 02_27 03_28
HCLK_R.HCLK_LEAF_CLK_B_TOP3.HCLK_CK_BUFHCLK3 03_28 05_27
HCLK_R.HCLK_LEAF_CLK_B_TOP3.HCLK_CK_BUFHCLK4 02_26 05_28
HCLK_R.HCLK_LEAF_CLK_B_TOP3.HCLK_CK_BUFHCLK5 05_26 05_28
HCLK_R.HCLK_LEAF_CLK_B_TOP3.HCLK_CK_BUFHCLK6 02_27 05_28
HCLK_R.HCLK_LEAF_CLK_B_TOP3.HCLK_CK_BUFHCLK7 05_27 05_28
HCLK_R.HCLK_LEAF_CLK_B_TOP3.HCLK_CK_OUTIN_R0 02_26 02_28
HCLK_R.HCLK_LEAF_CLK_B_TOP3.HCLK_CK_OUTIN_R1 02_28 05_26
HCLK_R.HCLK_LEAF_CLK_B_TOP3.HCLK_CK_OUTIN_R2 02_27 02_28
HCLK_R.HCLK_LEAF_CLK_B_TOP3.HCLK_CK_OUTIN_R3 02_28 05_27
HCLK_R.HCLK_LEAF_CLK_B_TOP3.HCLK_CK_OUTIN_R4 02_26 04_28
HCLK_R.HCLK_LEAF_CLK_B_TOP3.HCLK_CK_OUTIN_R5 04_28 05_26
HCLK_R.HCLK_LEAF_CLK_B_TOP3.HCLK_CK_OUTIN_R6 02_27 04_28
HCLK_R.HCLK_LEAF_CLK_B_TOP3.HCLK_CK_OUTIN_R7 04_28 05_27
HCLK_R.HCLK_LEAF_CLK_B_TOP4.HCLK_CK_BUFHCLK0 01_25 05_25
HCLK_R.HCLK_LEAF_CLK_B_TOP4.HCLK_CK_BUFHCLK1 01_25 02_25
HCLK_R.HCLK_LEAF_CLK_B_TOP4.HCLK_CK_BUFHCLK2 01_25 05_24
HCLK_R.HCLK_LEAF_CLK_B_TOP4.HCLK_CK_BUFHCLK3 01_25 02_24
HCLK_R.HCLK_LEAF_CLK_B_TOP4.HCLK_CK_BUFHCLK4 00_25 05_25
HCLK_R.HCLK_LEAF_CLK_B_TOP4.HCLK_CK_BUFHCLK5 00_25 02_25
HCLK_R.HCLK_LEAF_CLK_B_TOP4.HCLK_CK_BUFHCLK6 00_25 05_24
HCLK_R.HCLK_LEAF_CLK_B_TOP4.HCLK_CK_BUFHCLK7 00_25 02_24
HCLK_R.HCLK_LEAF_CLK_B_TOP4.HCLK_CK_OUTIN_R0 00_24 05_25
HCLK_R.HCLK_LEAF_CLK_B_TOP4.HCLK_CK_OUTIN_R1 00_24 02_25
HCLK_R.HCLK_LEAF_CLK_B_TOP4.HCLK_CK_OUTIN_R2 00_24 05_24
HCLK_R.HCLK_LEAF_CLK_B_TOP4.HCLK_CK_OUTIN_R3 00_24 02_24
HCLK_R.HCLK_LEAF_CLK_B_TOP4.HCLK_CK_OUTIN_R4 01_24 05_25
HCLK_R.HCLK_LEAF_CLK_B_TOP4.HCLK_CK_OUTIN_R5 01_24 02_25
HCLK_R.HCLK_LEAF_CLK_B_TOP4.HCLK_CK_OUTIN_R6 01_24 05_24
HCLK_R.HCLK_LEAF_CLK_B_TOP4.HCLK_CK_OUTIN_R7 01_24 02_24
HCLK_R.HCLK_LEAF_CLK_B_TOP5.HCLK_CK_BUFHCLK0 02_23 03_25
HCLK_R.HCLK_LEAF_CLK_B_TOP5.HCLK_CK_BUFHCLK1 02_23 04_25
HCLK_R.HCLK_LEAF_CLK_B_TOP5.HCLK_CK_BUFHCLK2 02_23 03_24
HCLK_R.HCLK_LEAF_CLK_B_TOP5.HCLK_CK_BUFHCLK3 02_23 04_24
HCLK_R.HCLK_LEAF_CLK_B_TOP5.HCLK_CK_BUFHCLK4 03_25 04_23
HCLK_R.HCLK_LEAF_CLK_B_TOP5.HCLK_CK_BUFHCLK5 04_23 04_25
HCLK_R.HCLK_LEAF_CLK_B_TOP5.HCLK_CK_BUFHCLK6 03_24 04_23
HCLK_R.HCLK_LEAF_CLK_B_TOP5.HCLK_CK_BUFHCLK7 04_23 04_24
HCLK_R.HCLK_LEAF_CLK_B_TOP5.HCLK_CK_OUTIN_R0 03_23 03_25
HCLK_R.HCLK_LEAF_CLK_B_TOP5.HCLK_CK_OUTIN_R1 03_23 04_25
HCLK_R.HCLK_LEAF_CLK_B_TOP5.HCLK_CK_OUTIN_R2 03_23 03_24
HCLK_R.HCLK_LEAF_CLK_B_TOP5.HCLK_CK_OUTIN_R3 03_23 04_24
HCLK_R.HCLK_LEAF_CLK_B_TOP5.HCLK_CK_OUTIN_R4 03_25 05_23
HCLK_R.HCLK_LEAF_CLK_B_TOP5.HCLK_CK_OUTIN_R5 04_25 05_23
HCLK_R.HCLK_LEAF_CLK_B_TOP5.HCLK_CK_OUTIN_R6 03_24 05_23
HCLK_R.HCLK_LEAF_CLK_B_TOP5.HCLK_CK_OUTIN_R7 04_24 05_23

154
kintex7/segbits_int_l.db
View File

@ -19,6 +19,7 @@ INT_L.BYP_ALT0.SL1END0 !23_07 19_06 22_07 24_07 25_07
INT_L.BYP_ALT0.SR1END_N3_3 !22_07 18_06 23_07 24_07 25_07
INT_L.BYP_ALT0.SS2END0 !22_07 !23_07 !25_07 16_07 24_07
INT_L.BYP_ALT0.SW2END0 !22_07 !23_07 !24_07 16_07 25_07
INT_L.BYP_ALT0.VCC_WIRE !30_04 !30_58 !31_00 !31_01 !31_24 !31_25 !31_27 !31_35 !31_36 !31_38 !31_60 !31_61 31_02 31_26 31_37 31_62
INT_L.BYP_ALT0.WL1END0 !23_07 17_07 22_07 24_07 25_07
INT_L.BYP_ALT0.WR1END0 !22_07 16_07 23_07 24_07 25_07
INT_L.BYP_ALT0.WW2END_N0_3 !22_07 !23_07 !25_07 17_07 24_07
@ -43,6 +44,7 @@ INT_L.BYP_ALT1.SL1END0 !23_15 19_14 22_15 24_15 25_15
INT_L.BYP_ALT1.SR1BEG_S0 !22_15 18_14 23_15 24_15 25_15
INT_L.BYP_ALT1.SS2END0 !22_15 !23_15 !25_15 19_14 24_15
INT_L.BYP_ALT1.SW2END0 !22_15 !23_15 !24_15 19_14 25_15
INT_L.BYP_ALT1.VCC_WIRE !30_00 !30_01 !30_03 !30_24 !30_26 !30_27 !30_35 !30_36 !30_38 !30_59 !30_61 !30_62 30_02 30_25 30_37 30_60
INT_L.BYP_ALT1.WL1END0 !23_15 16_15 22_15 24_15 25_15
INT_L.BYP_ALT1.WR1END1 !22_15 17_15 23_15 24_15 25_15
INT_L.BYP_ALT1.WW2END0 !22_15 !23_15 !25_15 18_14 24_15
@ -336,12 +338,14 @@ INT_L.EE2BEG3.SS2END3 09_55 14_54
INT_L.EE2BEG3.SS6END3 09_55 13_54
INT_L.EE4BEG0.EE2END0 03_08 03_09
INT_L.EE4BEG0.EE4END0 03_09 05_08
INT_L.EE4BEG0.LH12 05_08 07_09
INT_L.EE4BEG0.LOGIC_OUTS_L0 02_09 04_10
INT_L.EE4BEG0.LOGIC_OUTS_L12 03_08 04_10
INT_L.EE4BEG0.LOGIC_OUTS_L18 06_08 07_09
INT_L.EE4BEG0.LOGIC_OUTS_L22 04_10 06_08
INT_L.EE4BEG0.LOGIC_OUTS_L4 02_09 07_09
INT_L.EE4BEG0.LOGIC_OUTS_L8 03_08 07_09
INT_L.EE4BEG0.LV_L0 04_10 05_08
INT_L.EE4BEG0.NE2END0 02_09 04_09
INT_L.EE4BEG0.NE6END0 04_09 05_08
INT_L.EE4BEG0.NN2END0 03_08 04_09
@ -354,12 +358,14 @@ INT_L.EE4BEG0.SW2END0 02_09 05_11
INT_L.EE4BEG0.SW6END0 05_08 05_11
INT_L.EE4BEG1.EE2END1 03_24 03_25
INT_L.EE4BEG1.EE4END1 03_25 05_24
INT_L.EE4BEG1.LH6 05_24 07_25
INT_L.EE4BEG1.LOGIC_OUTS_L1 02_25 07_25
INT_L.EE4BEG1.LOGIC_OUTS_L13 03_24 07_25
INT_L.EE4BEG1.LOGIC_OUTS_L19 04_26 06_24
INT_L.EE4BEG1.LOGIC_OUTS_L23 06_24 07_25
INT_L.EE4BEG1.LOGIC_OUTS_L5 02_25 04_26
INT_L.EE4BEG1.LOGIC_OUTS_L9 03_24 04_26
INT_L.EE4BEG1.LV_L9 04_26 05_24
INT_L.EE4BEG1.NE2END1 02_25 04_25
INT_L.EE4BEG1.NE6END1 04_25 05_24
INT_L.EE4BEG1.NN2END1 03_24 04_25
@ -378,6 +384,8 @@ INT_L.EE4BEG2.LOGIC_OUTS_L16 06_40 07_41
INT_L.EE4BEG2.LOGIC_OUTS_L2 02_41 04_42
INT_L.EE4BEG2.LOGIC_OUTS_L20 04_42 06_40
INT_L.EE4BEG2.LOGIC_OUTS_L6 02_41 07_41
INT_L.EE4BEG2.LVB_L0 04_42 05_40
INT_L.EE4BEG2.LVB_L12 05_40 07_41
INT_L.EE4BEG2.NE2END2 02_41 04_41
INT_L.EE4BEG2.NE6END2 04_41 05_40
INT_L.EE4BEG2.NN2END2 03_40 04_41
@ -390,12 +398,14 @@ INT_L.EE4BEG2.SW2END2 02_41 05_43
INT_L.EE4BEG2.SW6END2 05_40 05_43
INT_L.EE4BEG3.EE2END3 03_56 03_57
INT_L.EE4BEG3.EE4END3 03_57 05_56
INT_L.EE4BEG3.LH0 04_58 05_56
INT_L.EE4BEG3.LOGIC_OUTS_L11 03_56 04_58
INT_L.EE4BEG3.LOGIC_OUTS_L15 03_56 07_57
INT_L.EE4BEG3.LOGIC_OUTS_L17 04_58 06_56
INT_L.EE4BEG3.LOGIC_OUTS_L21 06_56 07_57
INT_L.EE4BEG3.LOGIC_OUTS_L3 02_57 07_57
INT_L.EE4BEG3.LOGIC_OUTS_L7 02_57 04_58
INT_L.EE4BEG3.LV_L18 05_56 07_57
INT_L.EE4BEG3.NE2END3 02_57 04_57
INT_L.EE4BEG3.NE6END3 04_57 05_56
INT_L.EE4BEG3.NN2END3 03_56 04_57
@ -597,6 +607,7 @@ INT_L.FAN_ALT1.EL1END3 !22_48 17_48 23_48 24_48 25_48
INT_L.FAN_ALT1.ER1END2 !23_48 16_48 22_48 24_48 25_48
INT_L.FAN_ALT1.FAN_BOUNCE3 !22_48 20_48 23_48 24_48 25_48
INT_L.FAN_ALT1.FAN_BOUNCE_S3_4 !23_48 20_48 22_48 24_48 25_48
INT_L.FAN_ALT1.GFAN1 !00_18 !00_19 !01_13 !22_48 !23_48 !24_48 00_14 00_17 21_48 25_48
INT_L.FAN_ALT1.LOGIC_OUTS_L11 !22_48 21_48 23_48 24_48 25_48
INT_L.FAN_ALT1.LOGIC_OUTS_L17 !22_48 !23_48 !25_48 21_48 24_48
INT_L.FAN_ALT1.LOGIC_OUTS_L7 !23_48 21_48 22_48 24_48 25_48
@ -692,6 +703,7 @@ INT_L.FAN_ALT5.EL1END2 !22_40 16_40 23_40 24_40 25_40
INT_L.FAN_ALT5.ER1END2 !23_40 17_40 22_40 24_40 25_40
INT_L.FAN_ALT5.FAN_BOUNCE1 !22_40 20_40 23_40 24_40 25_40
INT_L.FAN_ALT5.FAN_BOUNCE_S3_0 !23_40 20_40 22_40 24_40 25_40
INT_L.FAN_ALT5.GFAN1 !00_18 !00_19 !01_13 !22_40 !23_40 !24_40 00_14 00_17 21_40 25_40
INT_L.FAN_ALT5.LOGIC_OUTS_L10 !22_40 21_40 23_40 24_40 25_40
INT_L.FAN_ALT5.LOGIC_OUTS_L16 !22_40 !23_40 !25_40 21_40 24_40
INT_L.FAN_ALT5.LOGIC_OUTS_L6 !23_40 21_40 22_40 24_40 25_40
@ -769,6 +781,7 @@ INT_L.GFAN0.GCLK_L_B6_WEST !00_10 !00_11 !01_09 01_10 01_18
INT_L.GFAN0.GCLK_L_B7_WEST !00_10 !01_09 !01_10 00_11 01_18
INT_L.GFAN0.GCLK_L_B8_WEST !01_09 00_10 00_11 01_10 01_16
INT_L.GFAN0.GCLK_L_B9_WEST !00_10 00_11 01_09 01_10 01_16
INT_L.GFAN0.GND_WIRE !00_10 !01_09 !01_10 00_11 01_14
INT_L.GFAN0.NR1END1 !00_10 00_11 01_09 01_10 01_14
INT_L.GFAN0.WW4END1 !00_10 !00_11 !01_09 01_10 01_14
INT_L.GFAN1.BYP_BOUNCE1 !00_19 00_14 00_17 00_18 01_13
@ -784,6 +797,7 @@ INT_L.GFAN1.GCLK_L_B6_WEST !00_18 !00_19 !01_13 00_14 00_15
INT_L.GFAN1.GCLK_L_B7_WEST !00_14 !00_18 !00_19 00_15 01_13
INT_L.GFAN1.GCLK_L_B8_WEST !00_19 00_14 00_18 01_13 01_17
INT_L.GFAN1.GCLK_L_B9_WEST !00_18 00_14 00_19 01_13 01_17
INT_L.GFAN1.GND_WIRE !00_14 !00_18 !00_19 00_17 01_13
INT_L.GFAN1.NR1END1 !00_18 00_14 00_17 00_19 01_13
INT_L.GFAN1.WW4END1 !00_18 !00_19 !01_13 00_14 00_17
INT_L.IMUX_L0.BYP_BOUNCE_N3_2 !22_01 !23_01 !24_01 21_01 25_01
@ -1938,6 +1952,90 @@ INT_L.IMUX_L9.SW2END0 !22_10 !23_10 !25_10 17_10 24_10
INT_L.IMUX_L9.WL1END0 !22_10 18_11 23_10 24_10 25_10
INT_L.IMUX_L9.WR1END0 !23_10 17_10 22_10 24_10 25_10
INT_L.IMUX_L9.WW2END0 !22_10 !23_10 !24_10 18_11 25_10
INT_L.LH0.EE4END3 00_58 01_61
INT_L.LH0.ER1END3 00_57 01_54
INT_L.LH0.LH12 01_54 01_56
INT_L.LH0.LV_L0 01_56 01_58
INT_L.LH0.LV_L18 01_56 01_61
INT_L.LH0.LV_L9 00_59 01_56
INT_L.LH0.NE2END3 00_58 00_59
INT_L.LH0.NE6END3 00_58 01_58
INT_L.LH0.NW2END3 00_58 01_54
INT_L.LH0.SR1END3 00_57 00_59
INT_L.LH0.SS6END3 00_57 01_58
INT_L.LH0.SW6END3 00_57 01_61
INT_L.LH12.EE4END3 01_60 01_62
INT_L.LH12.ER1END3 00_63 01_60
INT_L.LH12.LH0 00_61 00_63
INT_L.LH12.LV_L0 00_55 00_62
INT_L.LH12.LV_L18 00_62 01_62
INT_L.LH12.LV_L9 00_62 01_57
INT_L.LH12.NE2END3 01_57 01_60
INT_L.LH12.NE6END3 00_55 01_60
INT_L.LH12.NW2END3 00_62 00_63
INT_L.LH12.SR1END3 00_61 01_57
INT_L.LH12.SS6END3 00_55 00_61
INT_L.LH12.SW6END3 00_61 01_62
INT_L.LVB_L0.LH0 00_43 00_51
INT_L.LVB_L0.LH12 00_50 00_51
INT_L.LVB_L0.LH6 00_51 00_53
INT_L.LVB_L0.LVB_L12 00_51 00_54
INT_L.LVB_L0.LV_L0 00_47 01_52
INT_L.LVB_L0.LV_L18 01_42 01_52
INT_L.LVB_L0.NE2END2 00_53 01_52
INT_L.LVB_L0.NN6END3 00_50 01_50
INT_L.LVB_L0.NR1END3 00_47 01_50
INT_L.LVB_L0.NW2END2 00_43 01_52
INT_L.LVB_L0.NW6END3 00_43 01_50
INT_L.LVB_L0.SE2END3 00_51 01_42
INT_L.LVB_L0.SE6END3 00_54 01_50
INT_L.LVB_L0.SW2END2 00_50 01_52
INT_L.LVB_L0.SW2END3 00_47 00_51
INT_L.LVB_L0.SW6END2 00_54 01_52
INT_L.LVB_L0.WR1END3 01_42 01_50
INT_L.LVB_L0.WW4END3 00_53 01_50
INT_L.LVB_L12.LH0 00_46 00_49
INT_L.LVB_L12.LH12 00_46 01_53
INT_L.LVB_L12.LH6 00_46 01_49
INT_L.LVB_L12.LVB_L0 00_45 01_45
INT_L.LVB_L12.LV_L0 00_45 01_44
INT_L.LVB_L12.LV_L18 00_45 01_48
INT_L.LVB_L12.NE2END2 00_45 01_49
INT_L.LVB_L12.NN6END3 01_46 01_53
INT_L.LVB_L12.NR1END3 01_44 01_46
INT_L.LVB_L12.NW2END2 00_45 00_49
INT_L.LVB_L12.NW6END3 00_49 01_46
INT_L.LVB_L12.SE2END3 00_46 01_48
INT_L.LVB_L12.SE6END3 00_46 01_45
INT_L.LVB_L12.SW2END2 00_45 01_53
INT_L.LVB_L12.SW2END3 00_46 01_44
INT_L.LVB_L12.SW6END2 01_45 01_46
INT_L.LVB_L12.WR1END3 01_46 01_48
INT_L.LVB_L12.WW4END3 01_46 01_49
INT_L.LV_L0.ER1END0 01_04 01_05
INT_L.LV_L0.LH0 00_02 01_06
INT_L.LV_L0.LH12 00_05 01_06
INT_L.LV_L0.LH6 01_04 01_06
INT_L.LV_L0.LV_L18 00_09 01_06
INT_L.LV_L0.NN6END0 00_07 00_09
INT_L.LV_L0.NR1END0 00_02 01_05
INT_L.LV_L0.NW6END0 00_07 01_04
INT_L.LV_L0.SR1BEG_S0 00_05 01_05
INT_L.LV_L0.SW6END0 00_09 01_05
INT_L.LV_L0.WR1END0 00_02 00_07
INT_L.LV_L0.WW4END0 00_05 00_07
INT_L.LV_L18.ER1END0 00_03 00_06
INT_L.LV_L18.LH0 00_01 01_02
INT_L.LV_L18.LH12 01_02
INT_L.LV_L18.LH6 00_06 01_02
INT_L.LV_L18.LV_L0 01_00 01_01
INT_L.LV_L18.NN6END0 00_03 01_00
INT_L.LV_L18.NR1END0 00_01 00_03
INT_L.LV_L18.NW6END0 00_06 01_01
INT_L.LV_L18.SR1BEG_S0 00_03 01_08
INT_L.LV_L18.SW6END0 01_00 01_02
INT_L.LV_L18.WR1END0 00_01 01_01
INT_L.LV_L18.WW4END0 01_01 01_08
INT_L.NE2BEG0.EE2END0 09_04 14_04
INT_L.NE2BEG0.EE4END0 09_04 13_04
INT_L.NE2BEG0.EL1END0 09_05 12_04
@ -2020,12 +2118,14 @@ INT_L.NE2BEG3.SE2END3 09_53 14_52
INT_L.NE2BEG3.SE6END3 09_53 13_52
INT_L.NE6BEG0.EE2END0 03_04 05_07
INT_L.NE6BEG0.EE4END0 05_04 05_07
INT_L.NE6BEG0.LH12 05_04 07_05
INT_L.NE6BEG0.LOGIC_OUTS_L0 02_05 07_05
INT_L.NE6BEG0.LOGIC_OUTS_L12 03_04 07_05
INT_L.NE6BEG0.LOGIC_OUTS_L18 04_06 06_04
INT_L.NE6BEG0.LOGIC_OUTS_L22 06_04 07_05
INT_L.NE6BEG0.LOGIC_OUTS_L4 02_05 04_06
INT_L.NE6BEG0.LOGIC_OUTS_L8 03_04 04_06
INT_L.NE6BEG0.LV_L0 04_06 05_04
INT_L.NE6BEG0.NE2END0 02_05 03_05
INT_L.NE6BEG0.NE6END0 03_05 05_04
INT_L.NE6BEG0.NN2END0 03_04 03_05
@ -2038,12 +2138,14 @@ INT_L.NE6BEG0.WW2END_N0_3 03_04 04_05
INT_L.NE6BEG0.WW4END0 04_05 05_04
INT_L.NE6BEG1.EE2END1 03_20 05_23
INT_L.NE6BEG1.EE4END1 05_20 05_23
INT_L.NE6BEG1.LH6 05_20 07_21
INT_L.NE6BEG1.LOGIC_OUTS_L1 02_21 04_22
INT_L.NE6BEG1.LOGIC_OUTS_L13 03_20 04_22
INT_L.NE6BEG1.LOGIC_OUTS_L19 06_20 07_21
INT_L.NE6BEG1.LOGIC_OUTS_L23 04_22 06_20
INT_L.NE6BEG1.LOGIC_OUTS_L5 02_21 07_21
INT_L.NE6BEG1.LOGIC_OUTS_L9 03_20 07_21
INT_L.NE6BEG1.LV_L9 04_22 05_20
INT_L.NE6BEG1.NE2END1 02_21 03_21
INT_L.NE6BEG1.NE6END1 03_21 05_20
INT_L.NE6BEG1.NN2END1 03_20 03_21
@ -2062,6 +2164,8 @@ INT_L.NE6BEG2.LOGIC_OUTS_L16 04_38 06_36
INT_L.NE6BEG2.LOGIC_OUTS_L2 02_37 07_37
INT_L.NE6BEG2.LOGIC_OUTS_L20 06_36 07_37
INT_L.NE6BEG2.LOGIC_OUTS_L6 02_37 04_38
INT_L.NE6BEG2.LVB_L0 04_38 05_36
INT_L.NE6BEG2.LVB_L12 05_36 07_37
INT_L.NE6BEG2.NE2END2 02_37 03_37
INT_L.NE6BEG2.NE6END2 03_37 05_36
INT_L.NE6BEG2.NN2END2 03_36 03_37
@ -2074,12 +2178,14 @@ INT_L.NE6BEG2.WW2END1 03_36 04_37
INT_L.NE6BEG2.WW4END2 04_37 05_36
INT_L.NE6BEG3.EE2END3 03_52 05_55
INT_L.NE6BEG3.EE4END3 05_52 05_55
INT_L.NE6BEG3.LH0 04_54 05_52
INT_L.NE6BEG3.LOGIC_OUTS_L11 03_52 07_53
INT_L.NE6BEG3.LOGIC_OUTS_L15 03_52 04_54
INT_L.NE6BEG3.LOGIC_OUTS_L17 06_52 07_53
INT_L.NE6BEG3.LOGIC_OUTS_L21 04_54 06_52
INT_L.NE6BEG3.LOGIC_OUTS_L3 02_53 04_54
INT_L.NE6BEG3.LOGIC_OUTS_L7 02_53 07_53
INT_L.NE6BEG3.LV_L18 05_52 07_53
INT_L.NE6BEG3.NE2END3 02_53 03_53
INT_L.NE6BEG3.NE6END3 03_53 05_52
INT_L.NE6BEG3.NN2END3 03_52 03_53
@ -2252,12 +2358,14 @@ INT_L.NN2BEG3.WW2END2 10_50 14_50
INT_L.NN2BEG3.WW4END3 10_50 13_50
INT_L.NN6BEG0.EE2END0 02_07 05_06
INT_L.NN6BEG0.EE4END0 04_07 05_06
INT_L.NN6BEG0.LH12 04_07 05_05
INT_L.NN6BEG0.LOGIC_OUTS_L0 03_06 05_05
INT_L.NN6BEG0.LOGIC_OUTS_L12 02_07 05_05
INT_L.NN6BEG0.LOGIC_OUTS_L18 06_06 07_07
INT_L.NN6BEG0.LOGIC_OUTS_L22 05_05 07_07
INT_L.NN6BEG0.LOGIC_OUTS_L4 03_06 06_06
INT_L.NN6BEG0.LOGIC_OUTS_L8 02_07 06_06
INT_L.NN6BEG0.LV_L0 04_07 06_06
INT_L.NN6BEG0.NE2END0 02_06 03_06
INT_L.NN6BEG0.NE6END0 02_06 04_07
INT_L.NN6BEG0.NN2END0 02_06 02_07
@ -2270,12 +2378,14 @@ INT_L.NN6BEG0.WW2END_N0_3 02_07 04_04
INT_L.NN6BEG0.WW4END0 04_04 04_07
INT_L.NN6BEG1.EE2END1 02_23 05_22
INT_L.NN6BEG1.EE4END1 04_23 05_22
INT_L.NN6BEG1.LH6 04_23 05_21
INT_L.NN6BEG1.LOGIC_OUTS_L1 03_22 06_22
INT_L.NN6BEG1.LOGIC_OUTS_L13 02_23 06_22
INT_L.NN6BEG1.LOGIC_OUTS_L19 05_21 07_23
INT_L.NN6BEG1.LOGIC_OUTS_L23 06_22 07_23
INT_L.NN6BEG1.LOGIC_OUTS_L5 03_22 05_21
INT_L.NN6BEG1.LOGIC_OUTS_L9 02_23 05_21
INT_L.NN6BEG1.LV_L9 04_23 06_22
INT_L.NN6BEG1.NE2END1 02_22 03_22
INT_L.NN6BEG1.NE6END1 02_22 04_23
INT_L.NN6BEG1.NN2END1 02_22 02_23
@ -2294,6 +2404,8 @@ INT_L.NN6BEG2.LOGIC_OUTS_L16 06_38 07_39
INT_L.NN6BEG2.LOGIC_OUTS_L2 03_38 05_37
INT_L.NN6BEG2.LOGIC_OUTS_L20 05_37 07_39
INT_L.NN6BEG2.LOGIC_OUTS_L6 03_38 06_38
INT_L.NN6BEG2.LVB_L0 04_39 06_38
INT_L.NN6BEG2.LVB_L12 04_39 05_37
INT_L.NN6BEG2.NE2END2 02_38 03_38
INT_L.NN6BEG2.NE6END2 02_38 04_39
INT_L.NN6BEG2.NN2END2 02_38 02_39
@ -2306,12 +2418,14 @@ INT_L.NN6BEG2.WW2END1 02_39 04_36
INT_L.NN6BEG2.WW4END2 04_36 04_39
INT_L.NN6BEG3.EE2END3 02_55 05_54
INT_L.NN6BEG3.EE4END3 04_55 05_54
INT_L.NN6BEG3.LH0 04_55 06_54
INT_L.NN6BEG3.LOGIC_OUTS_L11 02_55 05_53
INT_L.NN6BEG3.LOGIC_OUTS_L15 02_55 06_54
INT_L.NN6BEG3.LOGIC_OUTS_L17 05_53 07_55
INT_L.NN6BEG3.LOGIC_OUTS_L21 06_54 07_55
INT_L.NN6BEG3.LOGIC_OUTS_L3 03_54 06_54
INT_L.NN6BEG3.LOGIC_OUTS_L7 03_54 05_53
INT_L.NN6BEG3.LV_L18 04_55 05_53
INT_L.NN6BEG3.NE2END3 02_54 03_54
INT_L.NN6BEG3.NE6END3 02_54 04_55
INT_L.NN6BEG3.NN2END3 02_54 02_55
@ -2482,12 +2596,14 @@ INT_L.NW2BEG3.WL1END2 10_48 12_48
INT_L.NW2BEG3.WR1END3 09_48 12_48
INT_L.NW2BEG3.WW2END2 06_49 14_48
INT_L.NW2BEG3.WW4END3 06_49 13_48
INT_L.NW6BEG0.LH12 04_03 05_01
INT_L.NW6BEG0.LOGIC_OUTS_L0 03_02 06_02
INT_L.NW6BEG0.LOGIC_OUTS_L12 02_03 06_02
INT_L.NW6BEG0.LOGIC_OUTS_L18 05_01 07_03
INT_L.NW6BEG0.LOGIC_OUTS_L22 06_02 07_03
INT_L.NW6BEG0.LOGIC_OUTS_L4 03_02 05_01
INT_L.NW6BEG0.LOGIC_OUTS_L8 02_03 05_01
INT_L.NW6BEG0.LV_L0 04_03 06_02
INT_L.NW6BEG0.NE2END0 03_02 05_02
INT_L.NW6BEG0.NE6END0 04_03 05_02
INT_L.NW6BEG0.NN2END0 02_03 05_02
@ -2500,12 +2616,14 @@ INT_L.NW6BEG0.SW2END_N0_3 03_02 04_00
INT_L.NW6BEG0.SW6END_N0_3 04_00 04_03
INT_L.NW6BEG0.WW2END_N0_3 02_02 02_03
INT_L.NW6BEG0.WW4END0 02_02 04_03
INT_L.NW6BEG1.LH6 04_19 05_17
INT_L.NW6BEG1.LOGIC_OUTS_L1 03_18 05_17
INT_L.NW6BEG1.LOGIC_OUTS_L13 02_19 05_17
INT_L.NW6BEG1.LOGIC_OUTS_L19 06_18 07_19
INT_L.NW6BEG1.LOGIC_OUTS_L23 05_17 07_19
INT_L.NW6BEG1.LOGIC_OUTS_L5 03_18 06_18
INT_L.NW6BEG1.LOGIC_OUTS_L9 02_19 06_18
INT_L.NW6BEG1.LV_L9 04_19 06_18
INT_L.NW6BEG1.NE2END1 03_18 05_18
INT_L.NW6BEG1.NE6END1 04_19 05_18
INT_L.NW6BEG1.NN2END1 02_19 05_18
@ -2524,6 +2642,8 @@ INT_L.NW6BEG2.LOGIC_OUTS_L16 05_33 07_35
INT_L.NW6BEG2.LOGIC_OUTS_L2 03_34 06_34
INT_L.NW6BEG2.LOGIC_OUTS_L20 06_34 07_35
INT_L.NW6BEG2.LOGIC_OUTS_L6 03_34 05_33
INT_L.NW6BEG2.LVB_L0 04_35 06_34
INT_L.NW6BEG2.LVB_L12 04_35 05_33
INT_L.NW6BEG2.NE2END2 03_34 05_34
INT_L.NW6BEG2.NE6END2 04_35 05_34
INT_L.NW6BEG2.NN2END2 02_35 05_34
@ -2536,12 +2656,14 @@ INT_L.NW6BEG2.SW2END1 03_34 04_32
INT_L.NW6BEG2.SW6END1 04_32 04_35
INT_L.NW6BEG2.WW2END1 02_34 02_35
INT_L.NW6BEG2.WW4END2 02_34 04_35
INT_L.NW6BEG3.LH0 04_51 06_50
INT_L.NW6BEG3.LOGIC_OUTS_L11 02_51 06_50
INT_L.NW6BEG3.LOGIC_OUTS_L15 02_51 05_49
INT_L.NW6BEG3.LOGIC_OUTS_L17 06_50 07_51
INT_L.NW6BEG3.LOGIC_OUTS_L21 05_49 07_51
INT_L.NW6BEG3.LOGIC_OUTS_L3 03_50 05_49
INT_L.NW6BEG3.LOGIC_OUTS_L7 03_50 06_50
INT_L.NW6BEG3.LV_L18 04_51 05_49
INT_L.NW6BEG3.NE2END3 03_50 05_50
INT_L.NW6BEG3.NE6END3 04_51 05_50
INT_L.NW6BEG3.NN2END3 02_51 05_50
@ -2636,12 +2758,14 @@ INT_L.SE2BEG3.SW2END3 09_57 14_56
INT_L.SE2BEG3.SW6END3 09_57 13_56
INT_L.SE6BEG0.EE2END0 02_10 02_11
INT_L.SE6BEG0.EE4END0 02_10 04_11
INT_L.SE6BEG0.LH12 04_11 05_09
INT_L.SE6BEG0.LOGIC_OUTS_L0 03_10 06_10
INT_L.SE6BEG0.LOGIC_OUTS_L12 02_11 06_10
INT_L.SE6BEG0.LOGIC_OUTS_L18 05_09 07_11
INT_L.SE6BEG0.LOGIC_OUTS_L22 06_10 07_11
INT_L.SE6BEG0.LOGIC_OUTS_L4 03_10 05_09
INT_L.SE6BEG0.LOGIC_OUTS_L8 02_11 05_09
INT_L.SE6BEG0.LV_L0 04_11 06_10
INT_L.SE6BEG0.NE2END0 03_10 04_08
INT_L.SE6BEG0.NE6END0 04_08 04_11
INT_L.SE6BEG0.NN2END0 02_11 04_08
@ -2654,12 +2778,14 @@ INT_L.SE6BEG0.SW2END0 03_10 05_10
INT_L.SE6BEG0.SW6END0 04_11 05_10
INT_L.SE6BEG1.EE2END1 02_26 02_27
INT_L.SE6BEG1.EE4END1 02_26 04_27
INT_L.SE6BEG1.LH6 04_27 05_25
INT_L.SE6BEG1.LOGIC_OUTS_L1 03_26 05_25
INT_L.SE6BEG1.LOGIC_OUTS_L13 02_27 05_25
INT_L.SE6BEG1.LOGIC_OUTS_L19 06_26 07_27
INT_L.SE6BEG1.LOGIC_OUTS_L23 05_25 07_27
INT_L.SE6BEG1.LOGIC_OUTS_L5 03_26 06_26
INT_L.SE6BEG1.LOGIC_OUTS_L9 02_27 06_26
INT_L.SE6BEG1.LV_L9 04_27 06_26
INT_L.SE6BEG1.NE2END1 03_26 04_24
INT_L.SE6BEG1.NE6END1 04_24 04_27
INT_L.SE6BEG1.NN2END1 02_27 04_24
@ -2678,6 +2804,8 @@ INT_L.SE6BEG2.LOGIC_OUTS_L16 05_41 07_43
INT_L.SE6BEG2.LOGIC_OUTS_L2 03_42 06_42
INT_L.SE6BEG2.LOGIC_OUTS_L20 06_42 07_43
INT_L.SE6BEG2.LOGIC_OUTS_L6 03_42 05_41
INT_L.SE6BEG2.LVB_L0 04_43 06_42
INT_L.SE6BEG2.LVB_L12 04_43 05_41
INT_L.SE6BEG2.NE2END2 03_42 04_40
INT_L.SE6BEG2.NE6END2 04_40 04_43
INT_L.SE6BEG2.NN2END2 02_43 04_40
@ -2690,12 +2818,14 @@ INT_L.SE6BEG2.SW2END2 03_42 05_42
INT_L.SE6BEG2.SW6END2 04_43 05_42
INT_L.SE6BEG3.EE2END3 02_58 02_59
INT_L.SE6BEG3.EE4END3 02_58 04_59
INT_L.SE6BEG3.LH0 04_59 06_58
INT_L.SE6BEG3.LOGIC_OUTS_L11 02_59 06_58
INT_L.SE6BEG3.LOGIC_OUTS_L15 02_59 05_57
INT_L.SE6BEG3.LOGIC_OUTS_L17 06_58 07_59
INT_L.SE6BEG3.LOGIC_OUTS_L21 05_57 07_59
INT_L.SE6BEG3.LOGIC_OUTS_L3 03_58 05_57
INT_L.SE6BEG3.LOGIC_OUTS_L7 03_58 06_58
INT_L.SE6BEG3.LV_L18 04_59 05_57
INT_L.SE6BEG3.NE2END3 03_58 04_56
INT_L.SE6BEG3.NE6END3 04_56 04_59
INT_L.SE6BEG3.NN2END3 02_59 04_56
@ -2948,12 +3078,14 @@ INT_L.SS2BEG3.WW2END3 09_59 14_58
INT_L.SS2BEG3.WW4END_S0_0 09_59 13_58
INT_L.SS6BEG0.EE2END0 02_15 04_12
INT_L.SS6BEG0.EE4END0 04_12 04_15
INT_L.SS6BEG0.LH12 04_15 05_13
INT_L.SS6BEG0.LOGIC_OUTS_L0 03_14 05_13
INT_L.SS6BEG0.LOGIC_OUTS_L12 02_15 05_13
INT_L.SS6BEG0.LOGIC_OUTS_L18 06_14 07_15
INT_L.SS6BEG0.LOGIC_OUTS_L22 05_13 07_15
INT_L.SS6BEG0.LOGIC_OUTS_L4 03_14 06_14
INT_L.SS6BEG0.LOGIC_OUTS_L8 02_15 06_14
INT_L.SS6BEG0.LV_L0 04_15 06_14
INT_L.SS6BEG0.NW2END1 03_14 05_14
INT_L.SS6BEG0.NW6END1 05_14 07_15
INT_L.SS6BEG0.SE2END0 03_14 04_12
@ -2966,12 +3098,14 @@ INT_L.SS6BEG0.WW2END0 02_15 05_14
INT_L.SS6BEG0.WW4END1 04_15 05_14
INT_L.SS6BEG1.EE2END1 02_31 04_28
INT_L.SS6BEG1.EE4END1 04_28 04_31
INT_L.SS6BEG1.LH6 04_31 05_29
INT_L.SS6BEG1.LOGIC_OUTS_L1 03_30 06_30
INT_L.SS6BEG1.LOGIC_OUTS_L13 02_31 06_30
INT_L.SS6BEG1.LOGIC_OUTS_L19 05_29 07_31
INT_L.SS6BEG1.LOGIC_OUTS_L23 06_30 07_31
INT_L.SS6BEG1.LOGIC_OUTS_L5 03_30 05_29
INT_L.SS6BEG1.LOGIC_OUTS_L9 02_31 05_29
INT_L.SS6BEG1.LV_L9 04_31 06_30
INT_L.SS6BEG1.NW2END2 03_30 05_30
INT_L.SS6BEG1.NW6END2 05_30 07_31
INT_L.SS6BEG1.SE2END1 03_30 04_28
@ -2990,6 +3124,8 @@ INT_L.SS6BEG2.LOGIC_OUTS_L16 06_46 07_47
INT_L.SS6BEG2.LOGIC_OUTS_L2 03_46 05_45
INT_L.SS6BEG2.LOGIC_OUTS_L20 05_45 07_47
INT_L.SS6BEG2.LOGIC_OUTS_L6 03_46 06_46
INT_L.SS6BEG2.LVB_L0 04_47 06_46
INT_L.SS6BEG2.LVB_L12 04_47 05_45
INT_L.SS6BEG2.NW2END3 03_46 05_46
INT_L.SS6BEG2.NW6END3 05_46 07_47
INT_L.SS6BEG2.SE2END2 03_46 04_44
@ -3002,12 +3138,14 @@ INT_L.SS6BEG2.WW2END2 02_47 05_46
INT_L.SS6BEG2.WW4END3 04_47 05_46
INT_L.SS6BEG3.EE2END3 02_63 04_60
INT_L.SS6BEG3.EE4END3 04_60 04_63
INT_L.SS6BEG3.LH0 04_63 06_62
INT_L.SS6BEG3.LOGIC_OUTS_L11 02_63 05_61
INT_L.SS6BEG3.LOGIC_OUTS_L15 02_63 06_62
INT_L.SS6BEG3.LOGIC_OUTS_L17 05_61 07_63
INT_L.SS6BEG3.LOGIC_OUTS_L21 06_62 07_63
INT_L.SS6BEG3.LOGIC_OUTS_L3 03_62 06_62
INT_L.SS6BEG3.LOGIC_OUTS_L7 03_62 05_61
INT_L.SS6BEG3.LV_L18 04_63 05_61
INT_L.SS6BEG3.NW2END_S0_0 03_62 05_62
INT_L.SS6BEG3.NW6END_S0_0 05_62 07_63
INT_L.SS6BEG3.SE2END3 03_62 04_60
@ -3100,12 +3238,14 @@ INT_L.SW2BEG3.WW2END3 09_60 14_60
INT_L.SW2BEG3.WW4END_S0_0 09_60 13_60
INT_L.SW6BEG0.EE2END0 03_12 04_13
INT_L.SW6BEG0.EE4END0 04_13 05_12
INT_L.SW6BEG0.LH12 05_12 07_13
INT_L.SW6BEG0.LOGIC_OUTS_L0 02_13 07_13
INT_L.SW6BEG0.LOGIC_OUTS_L12 03_12 07_13
INT_L.SW6BEG0.LOGIC_OUTS_L18 04_14 06_12
INT_L.SW6BEG0.LOGIC_OUTS_L22 06_12 07_13
INT_L.SW6BEG0.LOGIC_OUTS_L4 02_13 04_14
INT_L.SW6BEG0.LOGIC_OUTS_L8 03_12 04_14
INT_L.SW6BEG0.LV_L0 04_14 05_12
INT_L.SW6BEG0.NW2END1 02_13 05_15
INT_L.SW6BEG0.NW6END1 05_15 06_12
INT_L.SW6BEG0.SE2END0 02_13 04_13
@ -3118,12 +3258,14 @@ INT_L.SW6BEG0.WW2END0 03_12 05_15
INT_L.SW6BEG0.WW4END1 05_12 05_15
INT_L.SW6BEG1.EE2END1 03_28 04_29
INT_L.SW6BEG1.EE4END1 04_29 05_28
INT_L.SW6BEG1.LH6 05_28 07_29
INT_L.SW6BEG1.LOGIC_OUTS_L1 02_29 04_30
INT_L.SW6BEG1.LOGIC_OUTS_L13 03_28 04_30
INT_L.SW6BEG1.LOGIC_OUTS_L19 06_28 07_29
INT_L.SW6BEG1.LOGIC_OUTS_L23 04_30 06_28
INT_L.SW6BEG1.LOGIC_OUTS_L5 02_29 07_29
INT_L.SW6BEG1.LOGIC_OUTS_L9 03_28 07_29
INT_L.SW6BEG1.LV_L9 04_30 05_28
INT_L.SW6BEG1.NW2END2 02_29 05_31
INT_L.SW6BEG1.NW6END2 05_31 06_28
INT_L.SW6BEG1.SE2END1 02_29 04_29
@ -3142,6 +3284,8 @@ INT_L.SW6BEG2.LOGIC_OUTS_L16 04_46 06_44
INT_L.SW6BEG2.LOGIC_OUTS_L2 02_45 07_45
INT_L.SW6BEG2.LOGIC_OUTS_L20 06_44 07_45
INT_L.SW6BEG2.LOGIC_OUTS_L6 02_45 04_46
INT_L.SW6BEG2.LVB_L0 04_46 05_44
INT_L.SW6BEG2.LVB_L12 05_44 07_45
INT_L.SW6BEG2.NW2END3 02_45 05_47
INT_L.SW6BEG2.NW6END3 05_47 06_44
INT_L.SW6BEG2.SE2END2 02_45 04_45
@ -3154,12 +3298,14 @@ INT_L.SW6BEG2.WW2END2 03_44 05_47
INT_L.SW6BEG2.WW4END3 05_44 05_47
INT_L.SW6BEG3.EE2END3 03_60 04_61
INT_L.SW6BEG3.EE4END3 04_61 05_60
INT_L.SW6BEG3.LH0 04_62 05_60
INT_L.SW6BEG3.LOGIC_OUTS_L11 03_60 07_61
INT_L.SW6BEG3.LOGIC_OUTS_L15 03_60 04_62
INT_L.SW6BEG3.LOGIC_OUTS_L17 06_60 07_61
INT_L.SW6BEG3.LOGIC_OUTS_L21 04_62 06_60
INT_L.SW6BEG3.LOGIC_OUTS_L3 02_61 04_62
INT_L.SW6BEG3.LOGIC_OUTS_L7 02_61 07_61
INT_L.SW6BEG3.LV_L18 05_60 07_61
INT_L.SW6BEG3.NW2END_S0_0 02_61 05_63
INT_L.SW6BEG3.NW6END_S0_0 05_63 06_60
INT_L.SW6BEG3.SE2END3 02_61 04_61
@ -3410,12 +3556,14 @@ INT_L.WW2BEG3.WL1END3 09_63 12_62
INT_L.WW2BEG3.WR1END_S1_0 09_62 12_62
INT_L.WW2BEG3.WW2END3 11_62 14_62
INT_L.WW2BEG3.WW4END_S0_0 11_62 13_62
INT_L.WW4BEG0.LH12 05_00 07_01
INT_L.WW4BEG0.LOGIC_OUTS_L0 02_01 04_02
INT_L.WW4BEG0.LOGIC_OUTS_L12 03_00 04_02
INT_L.WW4BEG0.LOGIC_OUTS_L18 06_00 07_01
INT_L.WW4BEG0.LOGIC_OUTS_L22 04_02 06_00
INT_L.WW4BEG0.LOGIC_OUTS_L4 02_01 07_01
INT_L.WW4BEG0.LOGIC_OUTS_L8 03_00 07_01
INT_L.WW4BEG0.LV_L0 04_02 05_00
INT_L.WW4BEG0.NE2END0 02_01 05_03
INT_L.WW4BEG0.NE6END0 05_00 05_03
INT_L.WW4BEG0.NN2END0 03_00 05_03
@ -3428,12 +3576,14 @@ INT_L.WW4BEG0.SW2END_N0_3 02_01 04_01
INT_L.WW4BEG0.SW6END_N0_3 04_01 05_00
INT_L.WW4BEG0.WW2END_N0_3 03_00 03_01
INT_L.WW4BEG0.WW4END0 03_01 05_00
INT_L.WW4BEG1.LH6 05_16 07_17
INT_L.WW4BEG1.LOGIC_OUTS_L1 02_17 07_17
INT_L.WW4BEG1.LOGIC_OUTS_L13 03_16 07_17
INT_L.WW4BEG1.LOGIC_OUTS_L19 04_18 06_16
INT_L.WW4BEG1.LOGIC_OUTS_L23 06_16 07_17
INT_L.WW4BEG1.LOGIC_OUTS_L5 02_17 04_18
INT_L.WW4BEG1.LOGIC_OUTS_L9 03_16 04_18
INT_L.WW4BEG1.LV_L9 04_18 05_16
INT_L.WW4BEG1.NE2END1 02_17 05_19
INT_L.WW4BEG1.NE6END1 05_16 05_19
INT_L.WW4BEG1.NN2END1 03_16 05_19
@ -3452,6 +3602,8 @@ INT_L.WW4BEG2.LOGIC_OUTS_L16 06_32 07_33
INT_L.WW4BEG2.LOGIC_OUTS_L2 02_33 04_34
INT_L.WW4BEG2.LOGIC_OUTS_L20 04_34 06_32
INT_L.WW4BEG2.LOGIC_OUTS_L6 02_33 07_33
INT_L.WW4BEG2.LVB_L0 04_34 05_32
INT_L.WW4BEG2.LVB_L12 05_32 07_33
INT_L.WW4BEG2.NE2END2 02_33 05_35
INT_L.WW4BEG2.NE6END2 05_32 05_35
INT_L.WW4BEG2.NN2END2 03_32 05_35
@ -3464,12 +3616,14 @@ INT_L.WW4BEG2.SW2END1 02_33 04_33
INT_L.WW4BEG2.SW6END1 04_33 05_32
INT_L.WW4BEG2.WW2END1 03_32 03_33
INT_L.WW4BEG2.WW4END2 03_33 05_32
INT_L.WW4BEG3.LH0 04_50 05_48
INT_L.WW4BEG3.LOGIC_OUTS_L11 03_48 04_50
INT_L.WW4BEG3.LOGIC_OUTS_L15 03_48 07_49
INT_L.WW4BEG3.LOGIC_OUTS_L17 04_50 06_48
INT_L.WW4BEG3.LOGIC_OUTS_L21 06_48 07_49
INT_L.WW4BEG3.LOGIC_OUTS_L3 02_49 07_49
INT_L.WW4BEG3.LOGIC_OUTS_L7 02_49 04_50
INT_L.WW4BEG3.LV_L18 05_48 07_49
INT_L.WW4BEG3.NE2END3 02_49 05_51
INT_L.WW4BEG3.NE6END3 05_48 05_51
INT_L.WW4BEG3.NN2END3 03_48 05_51

154
kintex7/segbits_int_r.db
View File

@ -19,6 +19,7 @@ INT_R.BYP_ALT0.SL1END0 !23_07 19_06 22_07 24_07 25_07
INT_R.BYP_ALT0.SR1END_N3_3 !22_07 18_06 23_07 24_07 25_07
INT_R.BYP_ALT0.SS2END0 !22_07 !23_07 !25_07 16_07 24_07
INT_R.BYP_ALT0.SW2END0 !22_07 !23_07 !24_07 16_07 25_07
INT_R.BYP_ALT0.VCC_WIRE !30_04 !30_58 !31_00 !31_01 !31_24 !31_25 !31_27 !31_35 !31_36 !31_38 !31_60 !31_61 31_02 31_26 31_37 31_62
INT_R.BYP_ALT0.WL1END0 !23_07 17_07 22_07 24_07 25_07
INT_R.BYP_ALT0.WR1END0 !22_07 16_07 23_07 24_07 25_07
INT_R.BYP_ALT0.WW2END_N0_3 !22_07 !23_07 !25_07 17_07 24_07
@ -43,6 +44,7 @@ INT_R.BYP_ALT1.SL1END0 !23_15 19_14 22_15 24_15 25_15
INT_R.BYP_ALT1.SR1BEG_S0 !22_15 18_14 23_15 24_15 25_15
INT_R.BYP_ALT1.SS2END0 !22_15 !23_15 !25_15 19_14 24_15
INT_R.BYP_ALT1.SW2END0 !22_15 !23_15 !24_15 19_14 25_15
INT_R.BYP_ALT1.VCC_WIRE !30_00 !30_01 !30_03 !30_24 !30_26 !30_27 !30_35 !30_36 !30_38 !30_59 !30_61 !30_62 30_02 30_25 30_37 30_60
INT_R.BYP_ALT1.WL1END0 !23_15 16_15 22_15 24_15 25_15
INT_R.BYP_ALT1.WR1END1 !22_15 17_15 23_15 24_15 25_15
INT_R.BYP_ALT1.WW2END0 !22_15 !23_15 !25_15 18_14 24_15
@ -336,12 +338,14 @@ INT_R.EE2BEG3.SS2END3 09_55 14_54
INT_R.EE2BEG3.SS6END3 09_55 13_54
INT_R.EE4BEG0.EE2END0 03_08 03_09
INT_R.EE4BEG0.EE4END0 03_09 05_08
INT_R.EE4BEG0.LH12 05_08 07_09
INT_R.EE4BEG0.LOGIC_OUTS0 02_09 04_10
INT_R.EE4BEG0.LOGIC_OUTS12 03_08 04_10
INT_R.EE4BEG0.LOGIC_OUTS18 06_08 07_09
INT_R.EE4BEG0.LOGIC_OUTS22 04_10 06_08
INT_R.EE4BEG0.LOGIC_OUTS4 02_09 07_09
INT_R.EE4BEG0.LOGIC_OUTS8 03_08 07_09
INT_R.EE4BEG0.LV0 04_10 05_08
INT_R.EE4BEG0.NE2END0 02_09 04_09
INT_R.EE4BEG0.NE6END0 04_09 05_08
INT_R.EE4BEG0.NN2END0 03_08 04_09
@ -354,12 +358,14 @@ INT_R.EE4BEG0.SW2END0 02_09 05_11
INT_R.EE4BEG0.SW6END0 05_08 05_11
INT_R.EE4BEG1.EE2END1 03_24 03_25
INT_R.EE4BEG1.EE4END1 03_25 05_24
INT_R.EE4BEG1.LH6 05_24 07_25
INT_R.EE4BEG1.LOGIC_OUTS1 02_25 07_25
INT_R.EE4BEG1.LOGIC_OUTS13 03_24 07_25
INT_R.EE4BEG1.LOGIC_OUTS19 04_26 06_24
INT_R.EE4BEG1.LOGIC_OUTS23 06_24 07_25
INT_R.EE4BEG1.LOGIC_OUTS5 02_25 04_26
INT_R.EE4BEG1.LOGIC_OUTS9 03_24 04_26
INT_R.EE4BEG1.LV9 04_26 05_24
INT_R.EE4BEG1.NE2END1 02_25 04_25
INT_R.EE4BEG1.NE6END1 04_25 05_24
INT_R.EE4BEG1.NN2END1 03_24 04_25
@ -378,6 +384,8 @@ INT_R.EE4BEG2.LOGIC_OUTS16 06_40 07_41
INT_R.EE4BEG2.LOGIC_OUTS2 02_41 04_42
INT_R.EE4BEG2.LOGIC_OUTS20 04_42 06_40
INT_R.EE4BEG2.LOGIC_OUTS6 02_41 07_41
INT_R.EE4BEG2.LVB0 04_42 05_40
INT_R.EE4BEG2.LVB12 05_40 07_41
INT_R.EE4BEG2.NE2END2 02_41 04_41
INT_R.EE4BEG2.NE6END2 04_41 05_40
INT_R.EE4BEG2.NN2END2 03_40 04_41
@ -390,12 +398,14 @@ INT_R.EE4BEG2.SW2END2 02_41 05_43
INT_R.EE4BEG2.SW6END2 05_40 05_43
INT_R.EE4BEG3.EE2END3 03_56 03_57
INT_R.EE4BEG3.EE4END3 03_57 05_56
INT_R.EE4BEG3.LH0 04_58 05_56
INT_R.EE4BEG3.LOGIC_OUTS11 03_56 04_58
INT_R.EE4BEG3.LOGIC_OUTS15 03_56 07_57
INT_R.EE4BEG3.LOGIC_OUTS17 04_58 06_56
INT_R.EE4BEG3.LOGIC_OUTS21 06_56 07_57
INT_R.EE4BEG3.LOGIC_OUTS3 02_57 07_57
INT_R.EE4BEG3.LOGIC_OUTS7 02_57 04_58
INT_R.EE4BEG3.LV18 05_56 07_57
INT_R.EE4BEG3.NE2END3 02_57 04_57
INT_R.EE4BEG3.NE6END3 04_57 05_56
INT_R.EE4BEG3.NN2END3 03_56 04_57
@ -597,6 +607,7 @@ INT_R.FAN_ALT1.EL1END3 !22_48 17_48 23_48 24_48 25_48
INT_R.FAN_ALT1.ER1END2 !23_48 16_48 22_48 24_48 25_48
INT_R.FAN_ALT1.FAN_BOUNCE3 !22_48 20_48 23_48 24_48 25_48
INT_R.FAN_ALT1.FAN_BOUNCE_S3_4 !23_48 20_48 22_48 24_48 25_48
INT_R.FAN_ALT1.GFAN1 !00_18 !00_19 !01_13 !22_48 !23_48 !24_48 00_14 00_17 21_48 25_48
INT_R.FAN_ALT1.LOGIC_OUTS11 !22_48 21_48 23_48 24_48 25_48
INT_R.FAN_ALT1.LOGIC_OUTS17 !22_48 !23_48 !25_48 21_48 24_48
INT_R.FAN_ALT1.LOGIC_OUTS7 !23_48 21_48 22_48 24_48 25_48
@ -692,6 +703,7 @@ INT_R.FAN_ALT5.EL1END2 !22_40 16_40 23_40 24_40 25_40
INT_R.FAN_ALT5.ER1END2 !23_40 17_40 22_40 24_40 25_40
INT_R.FAN_ALT5.FAN_BOUNCE1 !22_40 20_40 23_40 24_40 25_40
INT_R.FAN_ALT5.FAN_BOUNCE_S3_0 !23_40 20_40 22_40 24_40 25_40
INT_R.FAN_ALT5.GFAN1 !22_40 !23_40 !24_40 21_40 25_40
INT_R.FAN_ALT5.LOGIC_OUTS10 !22_40 21_40 23_40 24_40 25_40
INT_R.FAN_ALT5.LOGIC_OUTS16 !22_40 !23_40 !25_40 21_40 24_40
INT_R.FAN_ALT5.LOGIC_OUTS6 !23_40 21_40 22_40 24_40 25_40
@ -769,6 +781,7 @@ INT_R.GFAN0.GCLK_B6 !00_10 !00_11 !01_09 01_10 01_18
INT_R.GFAN0.GCLK_B7 !00_10 !01_09 !01_10 00_11 01_18
INT_R.GFAN0.GCLK_B8 !01_09 00_10 00_11 01_10 01_16
INT_R.GFAN0.GCLK_B9 !00_10 00_11 01_09 01_10 01_16
INT_R.GFAN0.GND_WIRE !00_10 !01_09 !01_10 00_11 01_14
INT_R.GFAN0.NR1END1 !00_10 00_11 01_09 01_10 01_14
INT_R.GFAN0.WW4END1 !00_10 !00_11 !01_09 01_10 01_14
INT_R.GFAN1.BYP_BOUNCE1 !00_19 00_14 00_17 00_18 01_13
@ -784,6 +797,7 @@ INT_R.GFAN1.GCLK_B6 !00_18 !00_19 !01_13 00_14 00_15
INT_R.GFAN1.GCLK_B7 !00_14 !00_18 !00_19 00_15 01_13
INT_R.GFAN1.GCLK_B8 !00_19 00_14 00_18 01_13 01_17
INT_R.GFAN1.GCLK_B9 !00_18 00_14 00_19 01_13 01_17
INT_R.GFAN1.GND_WIRE !00_14 !00_18 !00_19 00_17 01_13
INT_R.GFAN1.NR1END1 !00_18 00_14 00_17 00_19 01_13
INT_R.GFAN1.WW4END1 !00_18 !00_19 !01_13 00_14 00_17
INT_R.IMUX0.BYP_BOUNCE_N3_2 !22_01 !23_01 !24_01 21_01 25_01
@ -1938,6 +1952,90 @@ INT_R.IMUX9.SW2END0 !22_10 !23_10 !25_10 17_10 24_10
INT_R.IMUX9.WL1END0 !22_10 18_11 23_10 24_10 25_10
INT_R.IMUX9.WR1END0 !23_10 17_10 22_10 24_10 25_10
INT_R.IMUX9.WW2END0 !22_10 !23_10 !24_10 18_11 25_10
INT_R.LH0.EE4END3 00_58 01_61
INT_R.LH0.ER1END3 00_57 01_54
INT_R.LH0.LH12 01_54 01_56
INT_R.LH0.LV0 01_56 01_58
INT_R.LH0.LV18 01_56 01_61
INT_R.LH0.LV9 00_59 01_56
INT_R.LH0.NE2END3 00_58 00_59
INT_R.LH0.NE6END3 00_58 01_58
INT_R.LH0.NW2END3 00_58 01_54
INT_R.LH0.SR1END3 00_57 00_59
INT_R.LH0.SS6END3 00_57 01_58
INT_R.LH0.SW6END3 00_57 01_61
INT_R.LH12.EE4END3 01_60 01_62
INT_R.LH12.ER1END3 00_63 01_60
INT_R.LH12.LH0 00_61 00_63
INT_R.LH12.LV0 00_55 00_62
INT_R.LH12.LV18 00_62 01_62
INT_R.LH12.LV9 00_62 01_57
INT_R.LH12.NE2END3 01_57 01_60
INT_R.LH12.NE6END3 00_55 01_60
INT_R.LH12.NW2END3 00_62 00_63
INT_R.LH12.SR1END3 00_61 01_57
INT_R.LH12.SS6END3 00_55 00_61
INT_R.LH12.SW6END3 00_61 01_62
INT_R.LV0.ER1END0 01_04 01_05
INT_R.LV0.LH0 00_02 01_06
INT_R.LV0.LH12 00_05 01_06
INT_R.LV0.LH6 01_04 01_06
INT_R.LV0.LV18 00_09 01_06
INT_R.LV0.NN6END0 00_07 00_09
INT_R.LV0.NR1END0 00_02 01_05
INT_R.LV0.NW6END0 00_07 01_04
INT_R.LV0.SR1BEG_S0 00_05 01_05
INT_R.LV0.SW6END0 00_09 01_05
INT_R.LV0.WR1END0 00_02 00_07
INT_R.LV0.WW4END0 00_05 00_07
INT_R.LV18.ER1END0 00_03 00_06
INT_R.LV18.LH0 00_01 01_02
INT_R.LV18.LH12 01_02 01_08
INT_R.LV18.LH6 00_06 01_02
INT_R.LV18.LV0 01_00 01_01
INT_R.LV18.NN6END0 00_03 01_00
INT_R.LV18.NR1END0 00_01 00_03
INT_R.LV18.NW6END0 00_06 01_01
INT_R.LV18.SR1BEG_S0 00_03 01_08
INT_R.LV18.SW6END0 01_00 01_02
INT_R.LV18.WR1END0 00_01 01_01
INT_R.LV18.WW4END0 01_01 01_08
INT_R.LVB0.LH0 00_43 00_51
INT_R.LVB0.LH12 00_50 00_51
INT_R.LVB0.LH6 00_51 00_53
INT_R.LVB0.LV0 00_47 01_52
INT_R.LVB0.LV18 01_42 01_52
INT_R.LVB0.LVB12 00_51 00_54
INT_R.LVB0.NE2END2 00_53 01_52
INT_R.LVB0.NN6END3 00_50 01_50
INT_R.LVB0.NR1END3 00_47 01_50
INT_R.LVB0.NW2END2 00_43 01_52
INT_R.LVB0.NW6END3 00_43 01_50
INT_R.LVB0.SE2END3 00_51 01_42
INT_R.LVB0.SE6END3 00_54 01_50
INT_R.LVB0.SW2END2 00_50 01_52
INT_R.LVB0.SW2END3 00_47 00_51
INT_R.LVB0.SW6END2 00_54 01_52
INT_R.LVB0.WR1END3 01_42 01_50
INT_R.LVB0.WW4END3 00_53 01_50
INT_R.LVB12.LH0 00_46 00_49
INT_R.LVB12.LH12 00_46 01_53
INT_R.LVB12.LH6 00_46 01_49
INT_R.LVB12.LV0 00_45 01_44
INT_R.LVB12.LV18 00_45 01_48
INT_R.LVB12.LVB0 00_45 01_45
INT_R.LVB12.NE2END2 00_45 01_49
INT_R.LVB12.NN6END3 01_46 01_53
INT_R.LVB12.NR1END3 01_44 01_46
INT_R.LVB12.NW2END2 00_45 00_49
INT_R.LVB12.NW6END3 00_49 01_46
INT_R.LVB12.SE2END3 00_46 01_48
INT_R.LVB12.SE6END3 00_46 01_45
INT_R.LVB12.SW2END2 00_45 01_53
INT_R.LVB12.SW2END3 00_46 01_44
INT_R.LVB12.SW6END2 01_45 01_46
INT_R.LVB12.WR1END3 01_46 01_48
INT_R.LVB12.WW4END3 01_46 01_49
INT_R.NE2BEG0.EE2END0 09_04 14_04
INT_R.NE2BEG0.EE4END0 09_04 13_04
INT_R.NE2BEG0.EL1END0 09_05 12_04
@ -2020,12 +2118,14 @@ INT_R.NE2BEG3.SE2END3 09_53 14_52
INT_R.NE2BEG3.SE6END3 09_53 13_52
INT_R.NE6BEG0.EE2END0 03_04 05_07
INT_R.NE6BEG0.EE4END0 05_04 05_07
INT_R.NE6BEG0.LH12 05_04 07_05
INT_R.NE6BEG0.LOGIC_OUTS0 02_05 07_05
INT_R.NE6BEG0.LOGIC_OUTS12 03_04 07_05
INT_R.NE6BEG0.LOGIC_OUTS18 04_06 06_04
INT_R.NE6BEG0.LOGIC_OUTS22 06_04 07_05
INT_R.NE6BEG0.LOGIC_OUTS4 02_05 04_06
INT_R.NE6BEG0.LOGIC_OUTS8 03_04 04_06
INT_R.NE6BEG0.LV0 04_06 05_04
INT_R.NE6BEG0.NE2END0 02_05 03_05
INT_R.NE6BEG0.NE6END0 03_05 05_04
INT_R.NE6BEG0.NN2END0 03_04 03_05
@ -2038,12 +2138,14 @@ INT_R.NE6BEG0.WW2END_N0_3 03_04 04_05
INT_R.NE6BEG0.WW4END0 04_05 05_04
INT_R.NE6BEG1.EE2END1 03_20 05_23
INT_R.NE6BEG1.EE4END1 05_20 05_23
INT_R.NE6BEG1.LH6 05_20 07_21
INT_R.NE6BEG1.LOGIC_OUTS1 02_21 04_22
INT_R.NE6BEG1.LOGIC_OUTS13 03_20 04_22
INT_R.NE6BEG1.LOGIC_OUTS19 06_20 07_21
INT_R.NE6BEG1.LOGIC_OUTS23 04_22 06_20
INT_R.NE6BEG1.LOGIC_OUTS5 02_21 07_21
INT_R.NE6BEG1.LOGIC_OUTS9 03_20 07_21
INT_R.NE6BEG1.LV9 04_22 05_20
INT_R.NE6BEG1.NE2END1 02_21 03_21
INT_R.NE6BEG1.NE6END1 03_21 05_20
INT_R.NE6BEG1.NN2END1 03_20 03_21
@ -2062,6 +2164,8 @@ INT_R.NE6BEG2.LOGIC_OUTS16 04_38 06_36
INT_R.NE6BEG2.LOGIC_OUTS2 02_37 07_37
INT_R.NE6BEG2.LOGIC_OUTS20 06_36 07_37
INT_R.NE6BEG2.LOGIC_OUTS6 02_37 04_38
INT_R.NE6BEG2.LVB0 04_38 05_36
INT_R.NE6BEG2.LVB12 05_36 07_37
INT_R.NE6BEG2.NE2END2 02_37 03_37
INT_R.NE6BEG2.NE6END2 03_37 05_36
INT_R.NE6BEG2.NN2END2 03_36 03_37
@ -2074,12 +2178,14 @@ INT_R.NE6BEG2.WW2END1 03_36 04_37
INT_R.NE6BEG2.WW4END2 04_37 05_36
INT_R.NE6BEG3.EE2END3 03_52 05_55
INT_R.NE6BEG3.EE4END3 05_52 05_55
INT_R.NE6BEG3.LH0 04_54 05_52
INT_R.NE6BEG3.LOGIC_OUTS11 03_52 07_53
INT_R.NE6BEG3.LOGIC_OUTS15 03_52 04_54
INT_R.NE6BEG3.LOGIC_OUTS17 06_52 07_53
INT_R.NE6BEG3.LOGIC_OUTS21 04_54 06_52
INT_R.NE6BEG3.LOGIC_OUTS3 02_53 04_54
INT_R.NE6BEG3.LOGIC_OUTS7 02_53 07_53
INT_R.NE6BEG3.LV18 05_52 07_53
INT_R.NE6BEG3.NE2END3 02_53 03_53
INT_R.NE6BEG3.NE6END3 03_53 05_52
INT_R.NE6BEG3.NN2END3 03_52 03_53
@ -2252,12 +2358,14 @@ INT_R.NN2BEG3.WW2END2 10_50 14_50
INT_R.NN2BEG3.WW4END3 10_50 13_50
INT_R.NN6BEG0.EE2END0 02_07 05_06
INT_R.NN6BEG0.EE4END0 04_07 05_06
INT_R.NN6BEG0.LH12 04_07 05_05
INT_R.NN6BEG0.LOGIC_OUTS0 03_06 05_05
INT_R.NN6BEG0.LOGIC_OUTS12 02_07 05_05
INT_R.NN6BEG0.LOGIC_OUTS18 06_06 07_07
INT_R.NN6BEG0.LOGIC_OUTS22 05_05 07_07
INT_R.NN6BEG0.LOGIC_OUTS4 03_06 06_06
INT_R.NN6BEG0.LOGIC_OUTS8 02_07 06_06
INT_R.NN6BEG0.LV0 04_07 06_06
INT_R.NN6BEG0.NE2END0 02_06 03_06
INT_R.NN6BEG0.NE6END0 02_06 04_07
INT_R.NN6BEG0.NN2END0 02_06 02_07
@ -2270,12 +2378,14 @@ INT_R.NN6BEG0.WW2END_N0_3 02_07 04_04
INT_R.NN6BEG0.WW4END0 04_04 04_07
INT_R.NN6BEG1.EE2END1 02_23 05_22
INT_R.NN6BEG1.EE4END1 04_23 05_22
INT_R.NN6BEG1.LH6 04_23 05_21
INT_R.NN6BEG1.LOGIC_OUTS1 03_22 06_22
INT_R.NN6BEG1.LOGIC_OUTS13 02_23 06_22
INT_R.NN6BEG1.LOGIC_OUTS19 05_21 07_23
INT_R.NN6BEG1.LOGIC_OUTS23 06_22 07_23
INT_R.NN6BEG1.LOGIC_OUTS5 03_22 05_21
INT_R.NN6BEG1.LOGIC_OUTS9 02_23 05_21
INT_R.NN6BEG1.LV9 04_23 06_22
INT_R.NN6BEG1.NE2END1 02_22 03_22
INT_R.NN6BEG1.NE6END1 02_22 04_23
INT_R.NN6BEG1.NN2END1 02_22 02_23
@ -2294,6 +2404,8 @@ INT_R.NN6BEG2.LOGIC_OUTS16 06_38 07_39
INT_R.NN6BEG2.LOGIC_OUTS2 03_38 05_37
INT_R.NN6BEG2.LOGIC_OUTS20 05_37 07_39
INT_R.NN6BEG2.LOGIC_OUTS6 03_38 06_38
INT_R.NN6BEG2.LVB0 04_39 06_38
INT_R.NN6BEG2.LVB12 04_39 05_37
INT_R.NN6BEG2.NE2END2 02_38 03_38
INT_R.NN6BEG2.NE6END2 02_38 04_39
INT_R.NN6BEG2.NN2END2 02_38 02_39
@ -2306,12 +2418,14 @@ INT_R.NN6BEG2.WW2END1 02_39 04_36
INT_R.NN6BEG2.WW4END2 04_36 04_39
INT_R.NN6BEG3.EE2END3 02_55 05_54
INT_R.NN6BEG3.EE4END3 04_55 05_54
INT_R.NN6BEG3.LH0 04_55 06_54
INT_R.NN6BEG3.LOGIC_OUTS11 02_55 05_53
INT_R.NN6BEG3.LOGIC_OUTS15 02_55 06_54
INT_R.NN6BEG3.LOGIC_OUTS17 05_53 07_55
INT_R.NN6BEG3.LOGIC_OUTS21 06_54 07_55
INT_R.NN6BEG3.LOGIC_OUTS3 03_54 06_54
INT_R.NN6BEG3.LOGIC_OUTS7 03_54 05_53
INT_R.NN6BEG3.LV18 04_55 05_53
INT_R.NN6BEG3.NE2END3 02_54 03_54
INT_R.NN6BEG3.NE6END3 02_54 04_55
INT_R.NN6BEG3.NN2END3 02_54 02_55
@ -2482,12 +2596,14 @@ INT_R.NW2BEG3.WL1END2 10_48 12_48
INT_R.NW2BEG3.WR1END3 09_48 12_48
INT_R.NW2BEG3.WW2END2 06_49 14_48
INT_R.NW2BEG3.WW4END3 06_49 13_48
INT_R.NW6BEG0.LH12 04_03 05_01
INT_R.NW6BEG0.LOGIC_OUTS0 03_02 06_02
INT_R.NW6BEG0.LOGIC_OUTS12 02_03 06_02
INT_R.NW6BEG0.LOGIC_OUTS18 05_01 07_03
INT_R.NW6BEG0.LOGIC_OUTS22 06_02 07_03
INT_R.NW6BEG0.LOGIC_OUTS4 03_02 05_01
INT_R.NW6BEG0.LOGIC_OUTS8 02_03 05_01
INT_R.NW6BEG0.LV0 04_03 06_02
INT_R.NW6BEG0.NE2END0 03_02 05_02
INT_R.NW6BEG0.NE6END0 04_03 05_02
INT_R.NW6BEG0.NN2END0 02_03 05_02
@ -2500,12 +2616,14 @@ INT_R.NW6BEG0.SW2END_N0_3 03_02 04_00
INT_R.NW6BEG0.SW6END_N0_3 04_00 04_03
INT_R.NW6BEG0.WW2END_N0_3 02_02 02_03
INT_R.NW6BEG0.WW4END0 02_02 04_03
INT_R.NW6BEG1.LH6 04_19 05_17
INT_R.NW6BEG1.LOGIC_OUTS1 03_18 05_17
INT_R.NW6BEG1.LOGIC_OUTS13 02_19 05_17
INT_R.NW6BEG1.LOGIC_OUTS19 06_18 07_19
INT_R.NW6BEG1.LOGIC_OUTS23 05_17 07_19
INT_R.NW6BEG1.LOGIC_OUTS5 03_18 06_18
INT_R.NW6BEG1.LOGIC_OUTS9 02_19 06_18
INT_R.NW6BEG1.LV9 04_19 06_18
INT_R.NW6BEG1.NE2END1 03_18 05_18
INT_R.NW6BEG1.NE6END1 04_19 05_18
INT_R.NW6BEG1.NN2END1 02_19 05_18
@ -2524,6 +2642,8 @@ INT_R.NW6BEG2.LOGIC_OUTS16 05_33 07_35
INT_R.NW6BEG2.LOGIC_OUTS2 03_34 06_34
INT_R.NW6BEG2.LOGIC_OUTS20 06_34 07_35
INT_R.NW6BEG2.LOGIC_OUTS6 03_34 05_33
INT_R.NW6BEG2.LVB0 04_35 06_34
INT_R.NW6BEG2.LVB12 04_35 05_33
INT_R.NW6BEG2.NE2END2 03_34 05_34
INT_R.NW6BEG2.NE6END2 04_35 05_34
INT_R.NW6BEG2.NN2END2 02_35 05_34
@ -2536,12 +2656,14 @@ INT_R.NW6BEG2.SW2END1 03_34 04_32
INT_R.NW6BEG2.SW6END1 04_32 04_35
INT_R.NW6BEG2.WW2END1 02_34 02_35
INT_R.NW6BEG2.WW4END2 02_34 04_35
INT_R.NW6BEG3.LH0 04_51 06_50
INT_R.NW6BEG3.LOGIC_OUTS11 02_51 06_50
INT_R.NW6BEG3.LOGIC_OUTS15 02_51 05_49
INT_R.NW6BEG3.LOGIC_OUTS17 06_50 07_51
INT_R.NW6BEG3.LOGIC_OUTS21 05_49 07_51
INT_R.NW6BEG3.LOGIC_OUTS3 03_50 05_49
INT_R.NW6BEG3.LOGIC_OUTS7 03_50 06_50
INT_R.NW6BEG3.LV18 04_51 05_49
INT_R.NW6BEG3.NE2END3 03_50 05_50
INT_R.NW6BEG3.NE6END3 04_51 05_50
INT_R.NW6BEG3.NN2END3 02_51 05_50
@ -2636,12 +2758,14 @@ INT_R.SE2BEG3.SW2END3 09_57 14_56
INT_R.SE2BEG3.SW6END3 09_57 13_56
INT_R.SE6BEG0.EE2END0 02_10 02_11
INT_R.SE6BEG0.EE4END0 02_10 04_11
INT_R.SE6BEG0.LH12 04_11 05_09
INT_R.SE6BEG0.LOGIC_OUTS0 03_10 06_10
INT_R.SE6BEG0.LOGIC_OUTS12 02_11 06_10
INT_R.SE6BEG0.LOGIC_OUTS18 05_09 07_11
INT_R.SE6BEG0.LOGIC_OUTS22 06_10 07_11
INT_R.SE6BEG0.LOGIC_OUTS4 03_10 05_09
INT_R.SE6BEG0.LOGIC_OUTS8 02_11 05_09
INT_R.SE6BEG0.LV0 04_11 06_10
INT_R.SE6BEG0.NE2END0 03_10 04_08
INT_R.SE6BEG0.NE6END0 04_08 04_11
INT_R.SE6BEG0.NN2END0 02_11 04_08
@ -2654,12 +2778,14 @@ INT_R.SE6BEG0.SW2END0 03_10 05_10
INT_R.SE6BEG0.SW6END0 04_11 05_10
INT_R.SE6BEG1.EE2END1 02_26 02_27
INT_R.SE6BEG1.EE4END1 02_26 04_27
INT_R.SE6BEG1.LH6 04_27 05_25
INT_R.SE6BEG1.LOGIC_OUTS1 03_26 05_25
INT_R.SE6BEG1.LOGIC_OUTS13 02_27 05_25
INT_R.SE6BEG1.LOGIC_OUTS19 06_26 07_27
INT_R.SE6BEG1.LOGIC_OUTS23 05_25 07_27
INT_R.SE6BEG1.LOGIC_OUTS5 03_26 06_26
INT_R.SE6BEG1.LOGIC_OUTS9 02_27 06_26
INT_R.SE6BEG1.LV9 04_27 06_26
INT_R.SE6BEG1.NE2END1 03_26 04_24
INT_R.SE6BEG1.NE6END1 04_24 04_27
INT_R.SE6BEG1.NN2END1 02_27 04_24
@ -2678,6 +2804,8 @@ INT_R.SE6BEG2.LOGIC_OUTS16 05_41 07_43
INT_R.SE6BEG2.LOGIC_OUTS2 03_42 06_42
INT_R.SE6BEG2.LOGIC_OUTS20 06_42 07_43
INT_R.SE6BEG2.LOGIC_OUTS6 03_42 05_41
INT_R.SE6BEG2.LVB0 04_43 06_42
INT_R.SE6BEG2.LVB12 04_43 05_41
INT_R.SE6BEG2.NE2END2 03_42 04_40
INT_R.SE6BEG2.NE6END2 04_40 04_43
INT_R.SE6BEG2.NN2END2 02_43 04_40
@ -2690,12 +2818,14 @@ INT_R.SE6BEG2.SW2END2 03_42 05_42
INT_R.SE6BEG2.SW6END2 04_43 05_42
INT_R.SE6BEG3.EE2END3 02_58 02_59
INT_R.SE6BEG3.EE4END3 02_58 04_59
INT_R.SE6BEG3.LH0 04_59 06_58
INT_R.SE6BEG3.LOGIC_OUTS11 02_59 06_58
INT_R.SE6BEG3.LOGIC_OUTS15 02_59 05_57
INT_R.SE6BEG3.LOGIC_OUTS17 06_58 07_59
INT_R.SE6BEG3.LOGIC_OUTS21 05_57 07_59
INT_R.SE6BEG3.LOGIC_OUTS3 03_58 05_57
INT_R.SE6BEG3.LOGIC_OUTS7 03_58 06_58
INT_R.SE6BEG3.LV18 04_59 05_57
INT_R.SE6BEG3.NE2END3 03_58 04_56
INT_R.SE6BEG3.NE6END3 04_56 04_59
INT_R.SE6BEG3.NN2END3 02_59 04_56
@ -2948,12 +3078,14 @@ INT_R.SS2BEG3.WW2END3 09_59 14_58
INT_R.SS2BEG3.WW4END_S0_0 09_59 13_58
INT_R.SS6BEG0.EE2END0 02_15 04_12
INT_R.SS6BEG0.EE4END0 04_12 04_15
INT_R.SS6BEG0.LH12 04_15 05_13
INT_R.SS6BEG0.LOGIC_OUTS0 03_14 05_13
INT_R.SS6BEG0.LOGIC_OUTS12 02_15 05_13
INT_R.SS6BEG0.LOGIC_OUTS18 06_14 07_15
INT_R.SS6BEG0.LOGIC_OUTS22 05_13 07_15
INT_R.SS6BEG0.LOGIC_OUTS4 03_14 06_14
INT_R.SS6BEG0.LOGIC_OUTS8 02_15 06_14
INT_R.SS6BEG0.LV0 04_15 06_14
INT_R.SS6BEG0.NW2END1 03_14 05_14
INT_R.SS6BEG0.NW6END1 05_14 07_15
INT_R.SS6BEG0.SE2END0 03_14 04_12
@ -2966,12 +3098,14 @@ INT_R.SS6BEG0.WW2END0 02_15 05_14
INT_R.SS6BEG0.WW4END1 04_15 05_14
INT_R.SS6BEG1.EE2END1 02_31 04_28
INT_R.SS6BEG1.EE4END1 04_28 04_31
INT_R.SS6BEG1.LH6 04_31 05_29
INT_R.SS6BEG1.LOGIC_OUTS1 03_30 06_30
INT_R.SS6BEG1.LOGIC_OUTS13 02_31 06_30
INT_R.SS6BEG1.LOGIC_OUTS19 05_29 07_31
INT_R.SS6BEG1.LOGIC_OUTS23 06_30 07_31
INT_R.SS6BEG1.LOGIC_OUTS5 03_30 05_29
INT_R.SS6BEG1.LOGIC_OUTS9 02_31 05_29
INT_R.SS6BEG1.LV9 04_31 06_30
INT_R.SS6BEG1.NW2END2 03_30 05_30
INT_R.SS6BEG1.NW6END2 05_30 07_31
INT_R.SS6BEG1.SE2END1 03_30 04_28
@ -2990,6 +3124,8 @@ INT_R.SS6BEG2.LOGIC_OUTS16 06_46 07_47
INT_R.SS6BEG2.LOGIC_OUTS2 03_46 05_45
INT_R.SS6BEG2.LOGIC_OUTS20 05_45 07_47
INT_R.SS6BEG2.LOGIC_OUTS6 03_46 06_46
INT_R.SS6BEG2.LVB0 04_47 06_46
INT_R.SS6BEG2.LVB12 04_47 05_45
INT_R.SS6BEG2.NW2END3 03_46 05_46
INT_R.SS6BEG2.NW6END3 05_46 07_47
INT_R.SS6BEG2.SE2END2 03_46 04_44
@ -3002,12 +3138,14 @@ INT_R.SS6BEG2.WW2END2 02_47 05_46
INT_R.SS6BEG2.WW4END3 04_47 05_46
INT_R.SS6BEG3.EE2END3 02_63 04_60
INT_R.SS6BEG3.EE4END3 04_60 04_63
INT_R.SS6BEG3.LH0 04_63 06_62
INT_R.SS6BEG3.LOGIC_OUTS11 02_63 05_61
INT_R.SS6BEG3.LOGIC_OUTS15 02_63 06_62
INT_R.SS6BEG3.LOGIC_OUTS17 05_61 07_63
INT_R.SS6BEG3.LOGIC_OUTS21 06_62 07_63
INT_R.SS6BEG3.LOGIC_OUTS3 03_62 06_62
INT_R.SS6BEG3.LOGIC_OUTS7 03_62 05_61
INT_R.SS6BEG3.LV18 04_63 05_61
INT_R.SS6BEG3.NW2END_S0_0 03_62 05_62
INT_R.SS6BEG3.NW6END_S0_0 05_62 07_63
INT_R.SS6BEG3.SE2END3 03_62 04_60
@ -3100,12 +3238,14 @@ INT_R.SW2BEG3.WW2END3 09_60 14_60
INT_R.SW2BEG3.WW4END_S0_0 09_60 13_60
INT_R.SW6BEG0.EE2END0 03_12 04_13
INT_R.SW6BEG0.EE4END0 04_13 05_12
INT_R.SW6BEG0.LH12 05_12 07_13
INT_R.SW6BEG0.LOGIC_OUTS0 02_13 07_13
INT_R.SW6BEG0.LOGIC_OUTS12 03_12 07_13
INT_R.SW6BEG0.LOGIC_OUTS18 04_14 06_12
INT_R.SW6BEG0.LOGIC_OUTS22 06_12 07_13
INT_R.SW6BEG0.LOGIC_OUTS4 02_13 04_14
INT_R.SW6BEG0.LOGIC_OUTS8 03_12 04_14
INT_R.SW6BEG0.LV0 04_14 05_12
INT_R.SW6BEG0.NW2END1 02_13 05_15
INT_R.SW6BEG0.NW6END1 05_15 06_12
INT_R.SW6BEG0.SE2END0 02_13 04_13
@ -3118,12 +3258,14 @@ INT_R.SW6BEG0.WW2END0 03_12 05_15
INT_R.SW6BEG0.WW4END1 05_12 05_15
INT_R.SW6BEG1.EE2END1 03_28 04_29
INT_R.SW6BEG1.EE4END1 04_29 05_28
INT_R.SW6BEG1.LH6 05_28 07_29
INT_R.SW6BEG1.LOGIC_OUTS1 02_29 04_30
INT_R.SW6BEG1.LOGIC_OUTS13 03_28 04_30
INT_R.SW6BEG1.LOGIC_OUTS19 06_28 07_29
INT_R.SW6BEG1.LOGIC_OUTS23 04_30 06_28
INT_R.SW6BEG1.LOGIC_OUTS5 02_29 07_29
INT_R.SW6BEG1.LOGIC_OUTS9 03_28 07_29
INT_R.SW6BEG1.LV9 04_30 05_28
INT_R.SW6BEG1.NW2END2 02_29 05_31
INT_R.SW6BEG1.NW6END2 05_31 06_28
INT_R.SW6BEG1.SE2END1 02_29 04_29
@ -3142,6 +3284,8 @@ INT_R.SW6BEG2.LOGIC_OUTS16 04_46 06_44
INT_R.SW6BEG2.LOGIC_OUTS2 02_45 07_45
INT_R.SW6BEG2.LOGIC_OUTS20 06_44 07_45
INT_R.SW6BEG2.LOGIC_OUTS6 02_45 04_46
INT_R.SW6BEG2.LVB0 04_46 05_44
INT_R.SW6BEG2.LVB12 05_44 07_45
INT_R.SW6BEG2.NW2END3 02_45 05_47
INT_R.SW6BEG2.NW6END3 05_47 06_44
INT_R.SW6BEG2.SE2END2 02_45 04_45
@ -3154,12 +3298,14 @@ INT_R.SW6BEG2.WW2END2 03_44 05_47
INT_R.SW6BEG2.WW4END3 05_44 05_47
INT_R.SW6BEG3.EE2END3 03_60 04_61
INT_R.SW6BEG3.EE4END3 04_61 05_60
INT_R.SW6BEG3.LH0 04_62 05_60
INT_R.SW6BEG3.LOGIC_OUTS11 03_60 07_61
INT_R.SW6BEG3.LOGIC_OUTS15 03_60 04_62
INT_R.SW6BEG3.LOGIC_OUTS17 06_60 07_61
INT_R.SW6BEG3.LOGIC_OUTS21 04_62 06_60
INT_R.SW6BEG3.LOGIC_OUTS3 02_61 04_62
INT_R.SW6BEG3.LOGIC_OUTS7 02_61 07_61
INT_R.SW6BEG3.LV18 05_60 07_61
INT_R.SW6BEG3.NW2END_S0_0 02_61 05_63
INT_R.SW6BEG3.NW6END_S0_0 05_63 06_60
INT_R.SW6BEG3.SE2END3 02_61 04_61
@ -3410,12 +3556,14 @@ INT_R.WW2BEG3.WL1END3 09_63 12_62
INT_R.WW2BEG3.WR1END_S1_0 09_62 12_62
INT_R.WW2BEG3.WW2END3 11_62 14_62
INT_R.WW2BEG3.WW4END_S0_0 11_62 13_62
INT_R.WW4BEG0.LH12 05_00 07_01
INT_R.WW4BEG0.LOGIC_OUTS0 02_01 04_02
INT_R.WW4BEG0.LOGIC_OUTS12 03_00 04_02
INT_R.WW4BEG0.LOGIC_OUTS18 06_00 07_01
INT_R.WW4BEG0.LOGIC_OUTS22 04_02 06_00
INT_R.WW4BEG0.LOGIC_OUTS4 02_01 07_01
INT_R.WW4BEG0.LOGIC_OUTS8 03_00 07_01
INT_R.WW4BEG0.LV0 04_02 05_00
INT_R.WW4BEG0.NE2END0 02_01 05_03
INT_R.WW4BEG0.NE6END0 05_00 05_03
INT_R.WW4BEG0.NN2END0 03_00 05_03
@ -3428,12 +3576,14 @@ INT_R.WW4BEG0.SW2END_N0_3 02_01 04_01
INT_R.WW4BEG0.SW6END_N0_3 04_01 05_00
INT_R.WW4BEG0.WW2END_N0_3 03_00 03_01
INT_R.WW4BEG0.WW4END0 03_01 05_00
INT_R.WW4BEG1.LH6 05_16 07_17
INT_R.WW4BEG1.LOGIC_OUTS1 02_17 07_17
INT_R.WW4BEG1.LOGIC_OUTS13 03_16 07_17
INT_R.WW4BEG1.LOGIC_OUTS19 04_18 06_16
INT_R.WW4BEG1.LOGIC_OUTS23 06_16 07_17
INT_R.WW4BEG1.LOGIC_OUTS5 02_17 04_18
INT_R.WW4BEG1.LOGIC_OUTS9 03_16 04_18
INT_R.WW4BEG1.LV9 04_18 05_16
INT_R.WW4BEG1.NE2END1 02_17 05_19
INT_R.WW4BEG1.NE6END1 05_16 05_19
INT_R.WW4BEG1.NN2END1 03_16 05_19
@ -3452,6 +3602,8 @@ INT_R.WW4BEG2.LOGIC_OUTS16 06_32 07_33
INT_R.WW4BEG2.LOGIC_OUTS2 02_33 04_34
INT_R.WW4BEG2.LOGIC_OUTS20 04_34 06_32
INT_R.WW4BEG2.LOGIC_OUTS6 02_33 07_33
INT_R.WW4BEG2.LVB0 04_34 05_32
INT_R.WW4BEG2.LVB12 05_32 07_33
INT_R.WW4BEG2.NE2END2 02_33 05_35
INT_R.WW4BEG2.NE6END2 05_32 05_35
INT_R.WW4BEG2.NN2END2 03_32 05_35
@ -3464,12 +3616,14 @@ INT_R.WW4BEG2.SW2END1 02_33 04_33
INT_R.WW4BEG2.SW6END1 04_33 05_32
INT_R.WW4BEG2.WW2END1 03_32 03_33
INT_R.WW4BEG2.WW4END2 03_33 05_32
INT_R.WW4BEG3.LH0 04_50 05_48
INT_R.WW4BEG3.LOGIC_OUTS11 03_48 04_50
INT_R.WW4BEG3.LOGIC_OUTS15 03_48 07_49
INT_R.WW4BEG3.LOGIC_OUTS17 04_50 06_48
INT_R.WW4BEG3.LOGIC_OUTS21 06_48 07_49
INT_R.WW4BEG3.LOGIC_OUTS3 02_49 07_49
INT_R.WW4BEG3.LOGIC_OUTS7 02_49 04_50
INT_R.WW4BEG3.LV18 05_48 07_49
INT_R.WW4BEG3.NE2END3 02_49 05_51
INT_R.WW4BEG3.NE6END3 05_48 05_51
INT_R.WW4BEG3.NN2END3 03_48 05_51

7
kintex7/settings.sh
View File

@ -1,11 +1,16 @@
export XRAY_DATABASE="kintex7"
export XRAY_PART="xc7k70tfbg676-2"
export XRAY_ROI_FRAMES="0x00000000:0xffffffff"
export XRAY_ROI="SLICE_X0Y50:SLICE_X19Y99 DSP48_X0Y20:DSP48_X0Y39 RAMB18_X0Y20:RAMB18_X0Y39 RAMB36_X0Y10:RAMB36_X0Y19"
export XRAY_ROI_FRAMES="0x00400100:0x004006ff"
# Part of CMT X0Y1
export XRAY_ROI_GRID_X1="9"
export XRAY_ROI_GRID_X2="38"
# Include VBRK / VTERM
export XRAY_ROI_GRID_Y1="104"
export XRAY_ROI_GRID_Y2="156"
# Choose the first N High Range I/Os
export XRAY_PIN_00="K25"
export XRAY_PIN_01="K26"

39
kintex7/site_type_BSCAN.json Normal file
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@ -0,0 +1,39 @@
{
"type": "BSCAN",
"site_pips": {},
"site_pins": {
"TMS": {
"direction": "OUT"
},
"CAPTURE": {
"direction": "OUT"
},
"TDO": {
"direction": "IN"
},
"SHIFT": {
"direction": "OUT"
},
"SEL": {
"direction": "OUT"
},
"UPDATE": {
"direction": "OUT"
},
"TCK": {
"direction": "OUT"
},
"TDI": {
"direction": "OUT"
},
"RESET": {
"direction": "OUT"
},
"RUNTEST": {
"direction": "OUT"
},
"DRCK": {
"direction": "OUT"
}
}
}

82
kintex7/site_type_BUFGCTRL.json Normal file
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@ -0,0 +1,82 @@
{
"type": "BUFGCTRL",
"site_pips": {
"CE1INV:CE1_B": {
"from_pin": "CE1_B",
"to_pin": "OUT"
},
"IGNORE1INV:IGNORE1_B": {
"from_pin": "IGNORE1_B",
"to_pin": "OUT"
},
"S0INV:S0_B": {
"from_pin": "S0_B",
"to_pin": "OUT"
},
"CE1INV:CE1": {
"from_pin": "CE1",
"to_pin": "OUT"
},
"CE0INV:CE0": {
"from_pin": "CE0",
"to_pin": "OUT"
},
"IGNORE1INV:IGNORE1": {
"from_pin": "IGNORE1",
"to_pin": "OUT"
},
"S1INV:S1_B": {
"from_pin": "S1_B",
"to_pin": "OUT"
},
"CE0INV:CE0_B": {
"from_pin": "CE0_B",
"to_pin": "OUT"
},
"IGNORE0INV:IGNORE0": {
"from_pin": "IGNORE0",
"to_pin": "OUT"
},
"S1INV:S1": {
"from_pin": "S1",
"to_pin": "OUT"
},
"S0INV:S0": {
"from_pin": "S0",
"to_pin": "OUT"
},
"IGNORE0INV:IGNORE0_B": {
"from_pin": "IGNORE0_B",
"to_pin": "OUT"
}
},
"site_pins": {
"IGNORE1": {
"direction": "IN"
},
"S1": {
"direction": "IN"
},
"I1": {
"direction": "IN"
},
"CE0": {
"direction": "IN"
},
"I0": {
"direction": "IN"
},
"CE1": {
"direction": "IN"
},
"S0": {
"direction": "IN"
},
"O": {
"direction": "OUT"
},
"IGNORE0": {
"direction": "IN"
}
}
}

24
kintex7/site_type_BUFHCE.json Normal file
View File

@ -0,0 +1,24 @@
{
"type": "BUFHCE",
"site_pips": {
"CEINV:CE": {
"from_pin": "CE",
"to_pin": "OUT"
},
"CEINV:CE_B": {
"from_pin": "CE_B",
"to_pin": "OUT"
}
},
"site_pins": {
"CE": {
"direction": "IN"
},
"I": {
"direction": "IN"
},
"O": {
"direction": "OUT"
}
}
}

12
kintex7/site_type_BUFIO.json Normal file
View File

@ -0,0 +1,12 @@
{
"type": "BUFIO",
"site_pips": {},
"site_pins": {
"I": {
"direction": "IN"
},
"O": {
"direction": "OUT"
}
}
}

24
kintex7/site_type_BUFMRCE.json Normal file
View File

@ -0,0 +1,24 @@
{
"type": "BUFMRCE",
"site_pips": {
"CEINV:CE": {
"from_pin": "CE",
"to_pin": "OUT"
},
"CEINV:CE_B": {
"from_pin": "CE_B",
"to_pin": "OUT"
}
},
"site_pins": {
"CE": {
"direction": "IN"
},
"I": {
"direction": "IN"
},
"O": {
"direction": "OUT"
}
}
}

18
kintex7/site_type_BUFR.json Normal file
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@ -0,0 +1,18 @@
{
"type": "BUFR",
"site_pips": {},
"site_pins": {
"CE": {
"direction": "IN"
},
"I": {
"direction": "IN"
},
"CLR": {
"direction": "IN"
},
"O": {
"direction": "OUT"
}
}
}

12
kintex7/site_type_CAPTURE.json Normal file
View File

@ -0,0 +1,12 @@
{
"type": "CAPTURE",
"site_pips": {},
"site_pins": {
"CLK": {
"direction": "IN"
},
"CAP": {
"direction": "IN"
}
}
}

12
kintex7/site_type_DCIRESET.json Normal file
View File

@ -0,0 +1,12 @@
{
"type": "DCIRESET",
"site_pips": {},
"site_pins": {
"RST": {
"direction": "IN"
},
"LOCKED": {
"direction": "OUT"
}
}
}

21
kintex7/site_type_DNA_PORT.json Normal file
View File

@ -0,0 +1,21 @@
{
"type": "DNA_PORT",
"site_pips": {},
"site_pins": {
"DOUT": {
"direction": "OUT"
},
"CLK": {
"direction": "IN"
},
"DIN": {
"direction": "IN"
},
"READ": {
"direction": "IN"
},
"SHIFT": {
"direction": "IN"
}
}
}

1402
kintex7/site_type_DSP48E1.json Normal file
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File diff suppressed because it is too large Load Diff

102
kintex7/site_type_EFUSE_USR.json Normal file
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@ -0,0 +1,102 @@
{
"type": "EFUSE_USR",
"site_pips": {},
"site_pins": {
"EFUSEUSR2": {
"direction": "OUT"
},
"EFUSEUSR25": {
"direction": "OUT"
},
"EFUSEUSR30": {
"direction": "OUT"
},
"EFUSEUSR28": {
"direction": "OUT"
},
"EFUSEUSR4": {
"direction": "OUT"
},
"EFUSEUSR7": {
"direction": "OUT"
},
"EFUSEUSR0": {
"direction": "OUT"
},
"EFUSEUSR1": {
"direction": "OUT"
},
"EFUSEUSR6": {
"direction": "OUT"
},
"EFUSEUSR18": {
"direction": "OUT"
},
"EFUSEUSR29": {
"direction": "OUT"
},
"EFUSEUSR21": {
"direction": "OUT"
},
"EFUSEUSR22": {
"direction": "OUT"
},
"EFUSEUSR16": {
"direction": "OUT"
},
"EFUSEUSR9": {
"direction": "OUT"
},
"EFUSEUSR13": {
"direction": "OUT"
},
"EFUSEUSR11": {
"direction": "OUT"
},
"EFUSEUSR17": {
"direction": "OUT"
},
"EFUSEUSR27": {
"direction": "OUT"
},
"EFUSEUSR15": {
"direction": "OUT"
},
"EFUSEUSR8": {
"direction": "OUT"
},
"EFUSEUSR20": {
"direction": "OUT"
},
"EFUSEUSR3": {
"direction": "OUT"
},
"EFUSEUSR23": {
"direction": "OUT"
},
"EFUSEUSR12": {
"direction": "OUT"
},
"EFUSEUSR5": {
"direction": "OUT"
},
"EFUSEUSR24": {
"direction": "OUT"
},
"EFUSEUSR10": {
"direction": "OUT"
},
"EFUSEUSR14": {
"direction": "OUT"
},
"EFUSEUSR26": {
"direction": "OUT"
},
"EFUSEUSR19": {
"direction": "OUT"
},
"EFUSEUSR31": {
"direction": "OUT"
}
}
}

537
kintex7/site_type_FIFO18E1.json Normal file
View File

@ -0,0 +1,537 @@
{
"type": "FIFO18E1",
"site_pips": {
"RSTREGINV:RSTREG": {
"from_pin": "RSTREG",
"to_pin": "OUT"
},
"WRCLKINV:WRCLK": {
"from_pin": "WRCLK",
"to_pin": "OUT"
},
"RDENINV:RDEN_B": {
"from_pin": "RDEN_B",
"to_pin": "OUT"
},
"WRCLKINV:WRCLK_B": {
"from_pin": "WRCLK_B",
"to_pin": "OUT"
},
"RSTREGINV:RSTREG_B": {
"from_pin": "RSTREG_B",
"to_pin": "OUT"
},
"RDCLKINV:RDCLK": {
"from_pin": "RDCLK",
"to_pin": "OUT"
},
"RDCLKINV:RDCLK_B": {
"from_pin": "RDCLK_B",
"to_pin": "OUT"
},
"WRENINV:WREN_B": {
"from_pin": "WREN_B",
"to_pin": "OUT"
},
"RSTINV:RST": {
"from_pin": "RST",
"to_pin": "OUT"
},
"RDENINV:RDEN": {
"from_pin": "RDEN",
"to_pin": "OUT"
},
"RDRCLKINV:RDRCLK_B": {
"from_pin": "RDRCLK_B",
"to_pin": "OUT"
},
"WRENINV:WREN": {
"from_pin": "WREN",
"to_pin": "OUT"
},
"RDRCLKINV:RDRCLK": {
"from_pin": "RDRCLK",
"to_pin": "OUT"
},
"RSTINV:RST_B": {
"from_pin": "RST_B",
"to_pin": "OUT"
}
},
"site_pins": {
"ALMOSTEMPTY": {
"direction": "OUT"
},
"DIADI6": {
"direction": "IN"
},
"WEBWE5": {
"direction": "IN"
},
"ADDRARDADDR8": {
"direction": "IN"
},
"WRCOUNT0": {
"direction": "OUT"
},
"WEA0": {
"direction": "IN"
},
"DO21": {
"direction": "OUT"
},
"ADDRARDADDR5": {
"direction": "IN"
},
"WEA1": {
"direction": "IN"
},
"DOP1": {
"direction": "OUT"
},
"DIADI0": {
"direction": "IN"
},
"RST": {
"direction": "IN"
},
"RSTREG": {
"direction": "IN"
},
"DIBDI8": {
"direction": "IN"
},
"RSTREGB": {
"direction": "IN"
},
"ADDRARDADDR13": {
"direction": "IN"
},
"WREN": {
"direction": "IN"
},
"ADDRBWRADDR9": {
"direction": "IN"
},
"RDCOUNT9": {
"direction": "OUT"
},
"DIADI1": {
"direction": "IN"
},
"DIADI15": {
"direction": "IN"
},
"REGCE": {
"direction": "IN"
},
"DIBDI5": {
"direction": "IN"
},
"DIBDI12": {
"direction": "IN"
},
"DO30": {
"direction": "OUT"
},
"ADDRBWRADDR0": {
"direction": "IN"
},
"ADDRBTIEHIGH1": {
"direction": "IN"
},
"DO18": {
"direction": "OUT"
},
"ADDRATIEHIGH1": {
"direction": "IN"
},
"RDCOUNT7": {
"direction": "OUT"
},
"RDERR": {
"direction": "OUT"
},
"DO12": {
"direction": "OUT"
},
"DIBDI13": {
"direction": "IN"
},
"DO28": {
"direction": "OUT"
},
"RDCOUNT1": {
"direction": "OUT"
},
"WRERR": {
"direction": "OUT"
},
"DO24": {
"direction": "OUT"
},
"WRCOUNT1": {
"direction": "OUT"
},
"WRCOUNT10": {
"direction": "OUT"
},
"RDCOUNT10": {
"direction": "OUT"
},
"DIBDI7": {
"direction": "IN"
},
"DO27": {
"direction": "OUT"
},
"WRCOUNT7": {
"direction": "OUT"
},
"DIADI5": {
"direction": "IN"
},
"DIADI10": {
"direction": "IN"
},
"DO8": {
"direction": "OUT"
},
"DIADI7": {
"direction": "IN"
},
"DO3": {
"direction": "OUT"
},
"DIPBDIP1": {
"direction": "IN"
},
"WEBWE4": {
"direction": "IN"
},
"RDCOUNT11": {
"direction": "OUT"
},
"WEBWE0": {
"direction": "IN"
},
"ADDRARDADDR1": {
"direction": "IN"
},
"DIBDI4": {
"direction": "IN"
},
"EMPTY": {
"direction": "OUT"
},
"DO4": {
"direction": "OUT"
},
"DO31": {
"direction": "OUT"
},
"DO19": {
"direction": "OUT"
},
"RDCLK": {
"direction": "IN"
},
"RDCOUNT8": {
"direction": "OUT"
},
"ADDRBWRADDR6": {
"direction": "IN"
},
"ADDRBWRADDR10": {
"direction": "IN"
},
"DIBDI2": {
"direction": "IN"
},
"ADDRBWRADDR2": {
"direction": "IN"
},
"DO13": {
"direction": "OUT"
},
"WRCOUNT4": {
"direction": "OUT"
},
"ADDRARDADDR10": {
"direction": "IN"
},
"RSTRAMB": {
"direction": "IN"
},
"DO1": {
"direction": "OUT"
},
"DIADI14": {
"direction": "IN"
},
"ADDRARDADDR11": {
"direction": "IN"
},
"DIBDI1": {
"direction": "IN"
},
"DIBDI6": {
"direction": "IN"
},
"WEBWE2": {
"direction": "IN"
},
"FULL": {
"direction": "OUT"
},
"RDEN": {
"direction": "IN"
},
"ADDRBTIEHIGH0": {
"direction": "IN"
},
"DO16": {
"direction": "OUT"
},
"RDCOUNT0": {
"direction": "OUT"
},
"DOP0": {
"direction": "OUT"
},
"RDCOUNT5": {
"direction": "OUT"
},
"DIBDI9": {
"direction": "IN"
},
"ADDRBWRADDR8": {
"direction": "IN"
},
"DOP3": {
"direction": "OUT"
},
"DIBDI3": {
"direction": "IN"
},
"WEA2": {
"direction": "IN"
},
"RDRCLK": {
"direction": "IN"
},
"DIPADIP1": {
"direction": "IN"
},
"WRCOUNT11": {
"direction": "OUT"
},
"DIPBDIP0": {
"direction": "IN"
},
"WRCOUNT9": {
"direction": "OUT"
},
"DO0": {
"direction": "OUT"
},
"DO17": {
"direction": "OUT"
},
"WRCOUNT2": {
"direction": "OUT"
},
"DOP2": {
"direction": "OUT"
},
"WRCOUNT6": {
"direction": "OUT"
},
"DIBDI11": {
"direction": "IN"
},
"DO22": {
"direction": "OUT"
},
"ADDRBWRADDR11": {
"direction": "IN"
},
"ADDRARDADDR9": {
"direction": "IN"
},
"DO15": {
"direction": "OUT"
},
"REGCEB": {
"direction": "IN"
},
"ALMOSTFULL": {
"direction": "OUT"
},
"WEBWE1": {
"direction": "IN"
},
"WEBWE3": {
"direction": "IN"
},
"DO26": {
"direction": "OUT"
},
"RDCOUNT2": {
"direction": "OUT"
},
"DO14": {
"direction": "OUT"
},
"WRCLK": {
"direction": "IN"
},
"WRCOUNT5": {
"direction": "OUT"
},
"WEBWE7": {
"direction": "IN"
},
"ADDRARDADDR7": {
"direction": "IN"
},
"ADDRARDADDR3": {
"direction": "IN"
},
"DIADI11": {
"direction": "IN"
},
"ADDRBWRADDR4": {
"direction": "IN"
},
"DIADI12": {
"direction": "IN"
},
"DO7": {
"direction": "OUT"
},
"RDCOUNT6": {
"direction": "OUT"
},
"ADDRARDADDR12": {
"direction": "IN"
},
"ADDRBWRADDR13": {
"direction": "IN"
},
"RDCOUNT4": {
"direction": "OUT"
},
"DIADI13": {
"direction": "IN"
},
"DO10": {
"direction": "OUT"
},
"DIADI4": {
"direction": "IN"
},
"DO23": {
"direction": "OUT"
},
"DIADI8": {
"direction": "IN"
},
"DO29": {
"direction": "OUT"
},
"ADDRARDADDR2": {
"direction": "IN"
},
"ADDRBWRADDR7": {
"direction": "IN"
},
"DIADI2": {
"direction": "IN"
},
"DO25": {
"direction": "OUT"
},
"ADDRARDADDR4": {
"direction": "IN"
},
"WRCOUNT3": {
"direction": "OUT"
},
"DO9": {
"direction": "OUT"
},
"DO6": {
"direction": "OUT"
},
"WEA3": {
"direction": "IN"
},
"ADDRATIEHIGH0": {
"direction": "IN"
},
"DO20": {
"direction": "OUT"
},
"DO2": {
"direction": "OUT"
},
"ADDRBWRADDR5": {
"direction": "IN"
},
"ADDRBWRADDR3": {
"direction": "IN"
},
"DIADI9": {
"direction": "IN"
},
"DIPADIP0": {
"direction": "IN"
},
"WEBWE6": {
"direction": "IN"
},
"DIBDI0": {
"direction": "IN"
},
"ADDRBWRADDR12": {
"direction": "IN"
},
"REGCLKB": {
"direction": "IN"
},
"DIBDI15": {
"direction": "IN"
},
"DO11": {
"direction": "OUT"
},
"WRCOUNT8": {
"direction": "OUT"
},
"DO5": {
"direction": "OUT"
},
"ADDRARDADDR6": {
"direction": "IN"
},
"DIBDI14": {
"direction": "IN"
},
"ADDRBWRADDR1": {
"direction": "IN"
},
"DIADI3": {
"direction": "IN"
},
"RDCOUNT3": {
"direction": "OUT"
},
"ADDRARDADDR0": {
"direction": "IN"
},
"DIBDI10": {
"direction": "IN"
}
}
}

171
kintex7/site_type_FRAME_ECC.json Normal file
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@ -0,0 +1,171 @@
{
"type": "FRAME_ECC",
"site_pips": {},
"site_pins": {
"FAR19": {
"direction": "OUT"
},
"SYNDROME5": {
"direction": "OUT"
},
"CRCERROR": {
"direction": "OUT"
},
"SYNDROME6": {
"direction": "OUT"
},
"FAR2": {
"direction": "OUT"
},
"FAR11": {
"direction": "OUT"
},
"FAR0": {
"direction": "OUT"
},
"FAR17": {
"direction": "OUT"
},
"SYNWORD6": {
"direction": "OUT"
},
"SYNWORD0": {
"direction": "OUT"
},
"SYNDROME3": {
"direction": "OUT"
},
"FAR23": {
"direction": "OUT"
},
"SYNBIT0": {
"direction": "OUT"
},
"SYNDROME1": {
"direction": "OUT"
},
"FAR13": {
"direction": "OUT"
},
"FAR7": {
"direction": "OUT"
},
"SYNWORD5": {
"direction": "OUT"
},
"FAR20": {
"direction": "OUT"
},
"SYNWORD4": {
"direction": "OUT"
},
"SYNBIT4": {
"direction": "OUT"
},
"SYNDROME11": {
"direction": "OUT"
},
"FAR15": {
"direction": "OUT"
},
"FAR1": {
"direction": "OUT"
},
"FAR24": {
"direction": "OUT"
},
"SYNBIT2": {
"direction": "OUT"
},
"FAR12": {
"direction": "OUT"
},
"SYNDROME12": {
"direction": "OUT"
},
"SYNDROME0": {
"direction": "OUT"
},
"FAR5": {
"direction": "OUT"
},
"FAR10": {
"direction": "OUT"
},
"SYNDROME8": {
"direction": "OUT"
},
"SYNDROMEVALID": {
"direction": "OUT"
},
"FAR8": {
"direction": "OUT"
},
"FAR6": {
"direction": "OUT"
},
"ECCERROR": {
"direction": "OUT"
},
"SYNWORD1": {
"direction": "OUT"
},
"FAR14": {
"direction": "OUT"
},
"SYNBIT3": {
"direction": "OUT"
},
"SYNDROME9": {
"direction": "OUT"
},
"FAR3": {
"direction": "OUT"
},
"SYNWORD2": {
"direction": "OUT"
},
"SYNWORD3": {
"direction": "OUT"
},
"SYNDROME2": {
"direction": "OUT"
},
"SYNDROME4": {
"direction": "OUT"
},
"FAR16": {
"direction": "OUT"
},
"SYNBIT1": {
"direction": "OUT"
},
"FAR9": {
"direction": "OUT"
},
"FAR22": {
"direction": "OUT"
},
"FAR25": {
"direction": "OUT"
},
"SYNDROME10": {
"direction": "OUT"
},
"FAR21": {
"direction": "OUT"
},
"FAR4": {
"direction": "OUT"
},
"FAR18": {
"direction": "OUT"
},
"SYNDROME7": {
"direction": "OUT"
},
"ECCERRORSINGLE": {
"direction": "OUT"
}
}
}

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kintex7/site_type_GTXE2_CHANNEL.json Normal file
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447
kintex7/site_type_GTXE2_COMMON.json Normal file
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{
"type": "GTXE2_COMMON",
"site_pips": {
"DRPCLKINV:DRPCLK": {
"from_pin": "DRPCLK",
"to_pin": "OUT"
},
"QPLLCLKSPARE0INV:QPLLCLKSPARE0": {
"from_pin": "QPLLCLKSPARE0",
"to_pin": "OUT"
},
"DRPCLKINV:DRPCLK_B": {
"from_pin": "DRPCLK_B",
"to_pin": "OUT"
},
"PMASCANCLK1INV:PMASCANCLK1": {
"from_pin": "PMASCANCLK1",
"to_pin": "OUT"
},
"QPLLCLKSPARE1INV:QPLLCLKSPARE1_B": {
"from_pin": "QPLLCLKSPARE1_B",
"to_pin": "OUT"
},
"PMASCANCLK0INV:PMASCANCLK0_B": {
"from_pin": "PMASCANCLK0_B",
"to_pin": "OUT"
},
"GTGREFCLKINV:GTGREFCLK": {
"from_pin": "GTGREFCLK",
"to_pin": "OUT"
},
"QPLLLOCKDETCLKINV:QPLLLOCKDETCLK_B": {
"from_pin": "QPLLLOCKDETCLK_B",
"to_pin": "OUT"
},
"QPLLLOCKDETCLKINV:QPLLLOCKDETCLK": {
"from_pin": "QPLLLOCKDETCLK",
"to_pin": "OUT"
},
"GTGREFCLKINV:GTGREFCLK_B": {
"from_pin": "GTGREFCLK_B",
"to_pin": "OUT"
},
"QPLLCLKSPARE0INV:QPLLCLKSPARE0_B": {
"from_pin": "QPLLCLKSPARE0_B",
"to_pin": "OUT"
},
"PMASCANCLK1INV:PMASCANCLK1_B": {
"from_pin": "PMASCANCLK1_B",
"to_pin": "OUT"
},
"PMASCANCLK0INV:PMASCANCLK0": {
"from_pin": "PMASCANCLK0",
"to_pin": "OUT"
},
"QPLLCLKSPARE1INV:QPLLCLKSPARE1": {
"from_pin": "QPLLCLKSPARE1",
"to_pin": "OUT"
}
},
"site_pins": {
"QPLLLOCKEN": {
"direction": "IN"
},
"QPLLRSVD23": {
"direction": "IN"
},
"PMASCANOUT3": {
"direction": "OUT"
},
"BGPDB": {
"direction": "IN"
},
"QPLLRSVD111": {
"direction": "IN"
},
"QPLLREFCLKSEL2": {
"direction": "IN"
},
"BGMONITORENB": {
"direction": "IN"
},
"QPLLREFCLKSEL1": {
"direction": "IN"
},
"QPLLDMONITOR5": {
"direction": "OUT"
},
"DRPDO8": {
"direction": "OUT"
},
"QPLLCLKSPARE0": {
"direction": "IN"
},
"DRPDO5": {
"direction": "OUT"
},
"BGRCALOVRD0": {
"direction": "IN"
},
"QPLLDMONITOR2": {
"direction": "OUT"
},
"QPLLRSVD12": {
"direction": "IN"
},
"QPLLRSVD22": {
"direction": "IN"
},
"DRPDI4": {
"direction": "IN"
},
"BGRCALOVRD2": {
"direction": "IN"
},
"QPLLOUTREFCLK": {
"direction": "OUT"
},
"QDPMASCANMODEB": {
"direction": "IN"
},
"PMASCANIN0": {
"direction": "IN"
},
"DRPDO2": {
"direction": "OUT"
},
"PMASCANOUT0": {
"direction": "OUT"
},
"QPLLLOCK": {
"direction": "OUT"
},
"QPLLRSVD20": {
"direction": "IN"
},
"QPLLRSVD21": {
"direction": "IN"
},
"DRPADDR4": {
"direction": "IN"
},
"QPLLRESET": {
"direction": "IN"
},
"QPLLDMONITOR6": {
"direction": "OUT"
},
"DRPADDR7": {
"direction": "IN"
},
"DRPDO0": {
"direction": "OUT"
},
"QPLLRSVD14": {
"direction": "IN"
},
"QPLLLOCKDETCLK": {
"direction": "IN"
},
"PMARSVD5": {
"direction": "IN"
},
"QPLLRSVD15": {
"direction": "IN"
},
"PMASCANIN1": {
"direction": "IN"
},
"DRPDO12": {
"direction": "OUT"
},
"DRPDO13": {
"direction": "OUT"
},
"QPLLRSVD19": {
"direction": "IN"
},
"PMASCANIN4": {
"direction": "IN"
},
"DRPDI11": {
"direction": "IN"
},
"DRPDI7": {
"direction": "IN"
},
"QPLLREFCLKSEL0": {
"direction": "IN"
},
"PMARSVD1": {
"direction": "IN"
},
"DRPDO11": {
"direction": "OUT"
},
"QPLLRSVD10": {
"direction": "IN"
},
"DRPADDR2": {
"direction": "IN"
},
"DRPDI0": {
"direction": "IN"
},
"DRPDO3": {
"direction": "OUT"
},
"BGBYPASSB": {
"direction": "IN"
},
"GTSOUTHREFCLK1": {
"direction": "IN"
},
"PMARSVD7": {
"direction": "IN"
},
"GTREFCLK0": {
"direction": "IN"
},
"QPLLOUTRESET": {
"direction": "IN"
},
"PMASCANOUT4": {
"direction": "OUT"
},
"GTNORTHREFCLK1": {
"direction": "IN"
},
"QPLLOUTCLK": {
"direction": "OUT"
},
"QPLLRSVD18": {
"direction": "IN"
},
"DRPADDR0": {
"direction": "IN"
},
"QPLLDMONITOR4": {
"direction": "OUT"
},
"QPLLDMONITOR0": {
"direction": "OUT"
},
"QPLLRSVD115": {
"direction": "IN"
},
"PMARSVD0": {
"direction": "IN"
},
"PMASCANOUT2": {
"direction": "OUT"
},
"DRPADDR3": {
"direction": "IN"
},
"DRPDO14": {
"direction": "OUT"
},
"BGRCALOVRD3": {
"direction": "IN"
},
"DRPDI13": {
"direction": "IN"
},
"DRPDI9": {
"direction": "IN"
},
"DRPDO9": {
"direction": "OUT"
},
"DRPDO10": {
"direction": "OUT"
},
"GTSOUTHREFCLK0": {
"direction": "IN"
},
"QPLLREFCLKLOST": {
"direction": "OUT"
},
"QPLLRSVD112": {
"direction": "IN"
},
"QPLLDMONITOR7": {
"direction": "OUT"
},
"PMARSVD6": {
"direction": "IN"
},
"DRPADDR1": {
"direction": "IN"
},
"DRPADDR5": {
"direction": "IN"
},
"PMARSVD3": {
"direction": "IN"
},
"QPLLRSVD24": {
"direction": "IN"
},
"QPLLRSVD13": {
"direction": "IN"
},
"DRPDO1": {
"direction": "OUT"
},
"PMARSVD2": {
"direction": "IN"
},
"DRPDI1": {
"direction": "IN"
},
"DRPDO7": {
"direction": "OUT"
},
"QPLLRSVD113": {
"direction": "IN"
},
"BGRCALOVRD4": {
"direction": "IN"
},
"DRPDI5": {
"direction": "IN"
},
"DRPEN": {
"direction": "IN"
},
"QPLLFBCLKLOST": {
"direction": "OUT"
},
"QPLLDMONITOR3": {
"direction": "OUT"
},
"PMASCANCLK0": {
"direction": "IN"
},
"DRPDI10": {
"direction": "IN"
},
"PMASCANENB": {
"direction": "IN"
},
"DRPDI14": {
"direction": "IN"
},
"PMASCANOUT1": {
"direction": "OUT"
},
"DRPDO15": {
"direction": "OUT"
},
"QPLLRSVD17": {
"direction": "IN"
},
"QPLLRSVD110": {
"direction": "IN"
},
"DRPADDR6": {
"direction": "IN"
},
"DRPDI3": {
"direction": "IN"
},
"GTGREFCLK": {
"direction": "IN"
},
"QPLLRSVD11": {
"direction": "IN"
},
"RCALENB": {
"direction": "IN"
},
"QPLLRSVD114": {
"direction": "IN"
},
"PMARSVD4": {
"direction": "IN"
},
"QPLLPD": {
"direction": "IN"
},
"DRPDI15": {
"direction": "IN"
},
"DRPDI8": {
"direction": "IN"
},
"DRPCLK": {
"direction": "IN"
},
"GTNORTHREFCLK0": {
"direction": "IN"
},
"QPLLRSVD16": {
"direction": "IN"
},
"QPLLCLKSPARE1": {
"direction": "IN"
},
"DRPRDY": {
"direction": "OUT"
},
"DRPDO6": {
"direction": "OUT"
},
"REFCLKOUTMONITOR": {
"direction": "OUT"
},
"DRPDI12": {
"direction": "IN"
},
"QDPMASCANRSTEN": {
"direction": "IN"
},
"DRPDI6": {
"direction": "IN"
},
"QPLLDMONITOR1": {
"direction": "OUT"
},
"DRPWE": {
"direction": "IN"
},
"PMASCANCLK1": {
"direction": "IN"
},
"GTREFCLK1": {
"direction": "IN"
},
"DRPDI2": {
"direction": "IN"
},
"PMASCANIN3": {
"direction": "IN"
},
"PMASCANIN2": {
"direction": "IN"
},
"BGRCALOVRD1": {
"direction": "IN"
},
"DRPDO4": {
"direction": "OUT"
}
}
}

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kintex7/site_type_IBUFDS_GTE2.json Normal file
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{
"type": "IBUFDS_GTE2",
"site_pips": {
"CLKTESTSIGINV:CLKTESTSIG_B": {
"from_pin": "CLKTESTSIG_B",
"to_pin": "OUT"
},
"CLKTESTSIGINV:CLKTESTSIG": {
"from_pin": "CLKTESTSIG",
"to_pin": "OUT"
}
},
"site_pins": {
"I": {
"direction": "IN"
},
"CEB": {
"direction": "IN"
},
"ODIV2": {
"direction": "OUT"
},
"IB": {
"direction": "IN"
},
"O": {
"direction": "OUT"
},
"CLKTESTSIG": {
"direction": "IN"
}
}
}

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kintex7/site_type_ICAP.json Normal file
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{
"type": "ICAP",
"site_pips": {},
"site_pins": {
"O13": {
"direction": "OUT"
},
"I8": {
"direction": "IN"
},
"I4": {
"direction": "IN"
},
"O14": {
"direction": "OUT"
},
"O4": {
"direction": "OUT"
},
"O22": {
"direction": "OUT"
},
"O7": {
"direction": "OUT"
},
"O9": {
"direction": "OUT"
},
"I25": {
"direction": "IN"
},
"O6": {
"direction": "OUT"
},
"I14": {
"direction": "IN"
},
"O12": {
"direction": "OUT"
},
"I31": {
"direction": "IN"
},
"I2": {
"direction": "IN"
},
"I13": {
"direction": "IN"
},
"I21": {
"direction": "IN"
},
"O1": {
"direction": "OUT"
},
"O20": {
"direction": "OUT"
},
"I5": {
"direction": "IN"
},
"O25": {
"direction": "OUT"
},
"I1": {
"direction": "IN"
},
"I29": {
"direction": "IN"
},
"I19": {
"direction": "IN"
},
"I23": {
"direction": "IN"
},
"O28": {
"direction": "OUT"
},
"O0": {
"direction": "OUT"
},
"O5": {
"direction": "OUT"
},
"O23": {
"direction": "OUT"
},
"CLK": {
"direction": "IN"
},
"I10": {
"direction": "IN"
},
"I9": {
"direction": "IN"
},
"O10": {
"direction": "OUT"
},
"I24": {
"direction": "IN"
},
"I17": {
"direction": "IN"
},
"O2": {
"direction": "OUT"
},
"O19": {
"direction": "OUT"
},
"O27": {
"direction": "OUT"
},
"I6": {
"direction": "IN"
},
"O30": {
"direction": "OUT"
},
"I27": {
"direction": "IN"
},
"I18": {
"direction": "IN"
},
"O8": {
"direction": "OUT"
},
"I16": {
"direction": "IN"
},
"RDWRB": {
"direction": "IN"
},
"O15": {
"direction": "OUT"
},
"I20": {
"direction": "IN"
},
"I12": {
"direction": "IN"
},
"I28": {
"direction": "IN"
},
"I3": {
"direction": "IN"
},
"I30": {
"direction": "IN"
},
"O29": {
"direction": "OUT"
},
"O31": {
"direction": "OUT"
},
"I22": {
"direction": "IN"
},
"O18": {
"direction": "OUT"
},
"CSIB": {
"direction": "IN"
},
"O21": {
"direction": "OUT"
},
"O26": {
"direction": "OUT"
},
"O17": {
"direction": "OUT"
},
"O3": {
"direction": "OUT"
},
"O24": {
"direction": "OUT"
},
"I11": {
"direction": "IN"
},
"O11": {
"direction": "OUT"
},
"I0": {
"direction": "IN"
},
"I15": {
"direction": "IN"
},
"I26": {
"direction": "IN"
},
"I7": {
"direction": "IN"
},
"O16": {
"direction": "OUT"
}
}
}

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kintex7/site_type_IDELAYCTRL.json Normal file
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{
"type": "IDELAYCTRL",
"site_pips": {},
"site_pins": {
"UPPULSEOUT": {
"direction": "OUT"
},
"RST": {
"direction": "IN"
},
"RDY": {
"direction": "OUT"
},
"OUTN65": {
"direction": "OUT"
},
"OUTN1": {
"direction": "OUT"
},
"DNPULSEOUT": {
"direction": "OUT"
},
"REFCLK": {
"direction": "IN"
}
}
}

100
kintex7/site_type_IDELAYE2.json Normal file
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@ -0,0 +1,100 @@
{
"type": "IDELAYE2",
"site_pips": {
"IDATAININV:IDATAIN": {
"from_pin": "IDATAIN",
"to_pin": "OUT"
},
"CINV:C_B": {
"from_pin": "C_B",
"to_pin": "OUT"
},
"DATAININV:DATAIN": {
"from_pin": "DATAIN",
"to_pin": "OUT"
},
"DATAININV:DATAIN_B": {
"from_pin": "DATAIN_B",
"to_pin": "OUT"
},
"CINV:C": {
"from_pin": "C",
"to_pin": "OUT"
},
"IDATAININV:IDATAIN_B": {
"from_pin": "IDATAIN_B",
"to_pin": "OUT"
}
},
"site_pins": {
"CNTVALUEOUT1": {
"direction": "OUT"
},
"IFDLY0": {
"direction": "IN"
},
"DATAIN": {
"direction": "IN"
},
"CNTVALUEIN1": {
"direction": "IN"
},
"CE": {
"direction": "IN"
},
"IDATAIN": {
"direction": "IN"
},
"DATAOUT": {
"direction": "OUT"
},
"CNTVALUEIN0": {
"direction": "IN"
},
"C": {
"direction": "IN"
},
"CNTVALUEOUT2": {
"direction": "OUT"
},
"CNTVALUEIN4": {
"direction": "IN"
},
"CNTVALUEOUT0": {
"direction": "OUT"
},
"CNTVALUEIN2": {
"direction": "IN"
},
"LDPIPEEN": {
"direction": "IN"
},
"IFDLY1": {
"direction": "IN"
},
"CINVCTRL": {
"direction": "IN"
},
"CNTVALUEOUT3": {
"direction": "OUT"
},
"INC": {
"direction": "IN"
},
"REGRST": {
"direction": "IN"
},
"CNTVALUEIN3": {
"direction": "IN"
},
"CNTVALUEOUT4": {
"direction": "OUT"
},
"IFDLY2": {
"direction": "IN"
},
"LD": {
"direction": "IN"
}
}
}

100
kintex7/site_type_IDELAYE2_FINEDELAY.json Normal file
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@ -0,0 +1,100 @@
{
"type": "IDELAYE2_FINEDELAY",
"site_pips": {
"IDATAININV:IDATAIN": {
"from_pin": "IDATAIN",
"to_pin": "OUT"
},
"CINV:C_B": {
"from_pin": "C_B",
"to_pin": "OUT"
},
"DATAININV:DATAIN": {
"from_pin": "DATAIN",
"to_pin": "OUT"
},
"DATAININV:DATAIN_B": {
"from_pin": "DATAIN_B",
"to_pin": "OUT"
},
"CINV:C": {
"from_pin": "C",
"to_pin": "OUT"
},
"IDATAININV:IDATAIN_B": {
"from_pin": "IDATAIN_B",
"to_pin": "OUT"
}
},
"site_pins": {
"CNTVALUEOUT1": {
"direction": "OUT"
},
"IFDLY0": {
"direction": "IN"
},
"DATAIN": {
"direction": "IN"
},
"CNTVALUEIN1": {
"direction": "IN"
},
"CE": {
"direction": "IN"
},
"IDATAIN": {
"direction": "IN"
},
"DATAOUT": {
"direction": "OUT"
},
"CNTVALUEIN0": {
"direction": "IN"
},
"C": {
"direction": "IN"
},
"CNTVALUEOUT2": {
"direction": "OUT"
},
"CNTVALUEIN4": {
"direction": "IN"
},
"CNTVALUEOUT0": {
"direction": "OUT"
},
"CNTVALUEIN2": {
"direction": "IN"
},
"LDPIPEEN": {
"direction": "IN"
},
"IFDLY1": {
"direction": "IN"
},
"CINVCTRL": {
"direction": "IN"
},
"CNTVALUEOUT3": {
"direction": "OUT"
},
"INC": {
"direction": "IN"
},
"REGRST": {
"direction": "IN"
},
"CNTVALUEIN3": {
"direction": "IN"
},
"CNTVALUEOUT4": {
"direction": "OUT"
},
"IFDLY2": {
"direction": "IN"
},
"LD": {
"direction": "IN"
}
}
}

184
kintex7/site_type_ILOGICE2.json Normal file
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{
"type": "ILOGICE2",
"site_pips": {
"CLKINV:CLK": {
"from_pin": "CLK",
"to_pin": "OUT"
},
"REVUSED:0": {
"from_pin": "0",
"to_pin": "OUT"
},
"CLKBINV:CLKB_B": {
"from_pin": "CLKB_B",
"to_pin": "OUT"
},
"D2OFFBYP_SEL:T": {
"from_pin": "T",
"to_pin": "OUT"
},
"IDELMUX:0": {
"from_pin": "0",
"to_pin": "OUT"
},
"D2OBYP_SEL:T": {
"from_pin": "T",
"to_pin": "OUT"
},
"DINV:D": {
"from_pin": "D",
"to_pin": "OUT"
},
"CLKBINV:CLKB": {
"from_pin": "CLKB",
"to_pin": "OUT"
},
"SRUSED:0": {
"from_pin": "0",
"to_pin": "OUT"
},
"IMUX:1": {
"from_pin": "1",
"to_pin": "OUT"
},
"CE1USED:0": {
"from_pin": "0",
"to_pin": "OUT"
},
"DINV:D_B": {
"from_pin": "D_B",
"to_pin": "OUT"
},
"IFFDELMUX:0": {
"from_pin": "0",
"to_pin": "OUT"
},
"D2OBYP_SEL:GND": {
"from_pin": "GND",
"to_pin": "OUT"
},
"IFFMUX:1": {
"from_pin": "1",
"to_pin": "OUT"
},
"IMUX:0": {
"from_pin": "0",
"to_pin": "OUT"
},
"IFFDELMUX:1": {
"from_pin": "1",
"to_pin": "OUT"
},
"IDELMUX:1": {
"from_pin": "1",
"to_pin": "OUT"
},
"IFFMUX:0": {
"from_pin": "0",
"to_pin": "OUT"
},
"CLKINV:CLK_B": {
"from_pin": "CLK_B",
"to_pin": "OUT"
},
"D2OFFBYP_SEL:GND": {
"from_pin": "GND",
"to_pin": "OUT"
}
},
"site_pins": {
"REV": {
"direction": "IN"
},
"BITSLIP": {
"direction": "IN"
},
"OFB": {
"direction": "IN"
},
"TFB": {
"direction": "IN"
},
"OCLK": {
"direction": "IN"
},
"Q4": {
"direction": "OUT"
},
"DYNCLKSEL": {
"direction": "IN"
},
"SHIFTOUT1": {
"direction": "OUT"
},
"CLKDIV": {
"direction": "IN"
},
"CLKB": {
"direction": "IN"
},
"Q5": {
"direction": "OUT"
},
"Q8": {
"direction": "OUT"
},
"SHIFTIN2": {
"direction": "IN"
},
"SHIFTIN1": {
"direction": "IN"
},
"CE1": {
"direction": "IN"
},
"Q1": {
"direction": "OUT"
},
"SHIFTOUT2": {
"direction": "OUT"
},
"D": {
"direction": "IN"
},
"DYNCLKDIVSEL": {
"direction": "IN"
},
"DYNCLKDIVPSEL": {
"direction": "IN"
},
"Q3": {
"direction": "OUT"
},
"OCLKB": {
"direction": "IN"
},
"Q6": {
"direction": "OUT"
},
"Q2": {
"direction": "OUT"
},
"CLK": {
"direction": "IN"
},
"Q7": {
"direction": "OUT"
},
"SR": {
"direction": "IN"
},
"CLKDIVP": {
"direction": "IN"
},
"DDLY": {
"direction": "IN"
},
"O": {
"direction": "OUT"
},
"CE2": {
"direction": "IN"
}
}
}

208
kintex7/site_type_ILOGICE3.json Normal file
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{
"type": "ILOGICE3",
"site_pips": {
"CLKBINV:CLKB_B": {
"from_pin": "CLKB_B",
"to_pin": "OUT"
},
"CLKINV:CLK": {
"from_pin": "CLK",
"to_pin": "OUT"
},
"D2OBYP_SEL:GND": {
"from_pin": "GND",
"to_pin": "OUT"
},
"IMUX:0": {
"from_pin": "0",
"to_pin": "OUT"
},
"IDELMUXE3:0": {
"from_pin": "0",
"to_pin": "OUT"
},
"DINV:D": {
"from_pin": "D",
"to_pin": "OUT"
},
"DINV:D_B": {
"from_pin": "D_B",
"to_pin": "OUT"
},
"D2OFFBYP_SEL:T": {
"from_pin": "T",
"to_pin": "OUT"
},
"IFFDELMUXE3:1": {
"from_pin": "1",
"to_pin": "OUT"
},
"CE1USED:0": {
"from_pin": "0",
"to_pin": "OUT"
},
"ZHOLD_FABRIC_INV:D": {
"from_pin": "D",
"to_pin": "OUT"
},
"REVUSED:0": {
"from_pin": "0",
"to_pin": "OUT"
},
"IDELMUXE3:2": {
"from_pin": "2",
"to_pin": "OUT"
},
"ZHOLD_IFF_INV:D": {
"from_pin": "D",
"to_pin": "OUT"
},
"D2OBYP_SEL:T": {
"from_pin": "T",
"to_pin": "OUT"
},
"CLKBINV:CLKB": {
"from_pin": "CLKB",
"to_pin": "OUT"
},
"SRUSED:0": {
"from_pin": "0",
"to_pin": "OUT"
},
"CLKINV:CLK_B": {
"from_pin": "CLK_B",
"to_pin": "OUT"
},
"IMUX:1": {
"from_pin": "1",
"to_pin": "OUT"
},
"IDELMUXE3:1": {
"from_pin": "1",
"to_pin": "OUT"
},
"IFFDELMUXE3:0": {
"from_pin": "0",
"to_pin": "OUT"
},
"IFFMUX:1": {
"from_pin": "1",
"to_pin": "OUT"
},
"ZHOLD_FABRIC_INV:D_B": {
"from_pin": "D_B",
"to_pin": "OUT"
},
"IFFMUX:0": {
"from_pin": "0",
"to_pin": "OUT"
},
"D2OFFBYP_SEL:GND": {
"from_pin": "GND",
"to_pin": "OUT"
},
"ZHOLD_IFF_INV:D_B": {
"from_pin": "D_B",
"to_pin": "OUT"
},
"IFFDELMUXE3:2": {
"from_pin": "2",
"to_pin": "OUT"
}
},
"site_pins": {
"REV": {
"direction": "IN"
},
"BITSLIP": {
"direction": "IN"
},
"OFB": {
"direction": "IN"
},
"TFB": {
"direction": "IN"
},
"OCLK": {
"direction": "IN"
},
"Q4": {
"direction": "OUT"
},
"DYNCLKSEL": {
"direction": "IN"
},
"SHIFTOUT1": {
"direction": "OUT"
},
"CLKDIV": {
"direction": "IN"
},
"CLKB": {
"direction": "IN"
},
"Q5": {
"direction": "OUT"
},
"Q8": {
"direction": "OUT"
},
"SHIFTIN2": {
"direction": "IN"
},
"SHIFTIN1": {
"direction": "IN"
},
"CE1": {
"direction": "IN"
},
"Q1": {
"direction": "OUT"
},
"SHIFTOUT2": {
"direction": "OUT"
},
"D": {
"direction": "IN"
},
"DYNCLKDIVSEL": {
"direction": "IN"
},
"DYNCLKDIVPSEL": {
"direction": "IN"
},
"Q3": {
"direction": "OUT"
},
"OCLKB": {
"direction": "IN"
},
"Q6": {
"direction": "OUT"
},
"Q2": {
"direction": "OUT"
},
"CLK": {
"direction": "IN"
},
"Q7": {
"direction": "OUT"
},
"SR": {
"direction": "IN"
},
"CLKDIVP": {
"direction": "IN"
},
"DDLY": {
"direction": "IN"
},
"O": {
"direction": "OUT"
},
"CE2": {
"direction": "IN"
}
}
}

453
kintex7/site_type_IN_FIFO.json Normal file
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{
"type": "IN_FIFO",
"site_pips": {},
"site_pins": {
"Q53": {
"direction": "OUT"
},
"ALMOSTEMPTY": {
"direction": "OUT"
},
"Q80": {
"direction": "OUT"
},
"D53": {
"direction": "IN"
},
"D23": {
"direction": "IN"
},
"D73": {
"direction": "IN"
},
"D56": {
"direction": "IN"
},
"Q64": {
"direction": "OUT"
},
"Q57": {
"direction": "OUT"
},
"Q12": {
"direction": "OUT"
},
"D66": {
"direction": "IN"
},
"Q44": {
"direction": "OUT"
},
"Q41": {
"direction": "OUT"
},
"FULL": {
"direction": "OUT"
},
"SCANOUT3": {
"direction": "OUT"
},
"Q22": {
"direction": "OUT"
},
"D67": {
"direction": "IN"
},
"Q21": {
"direction": "OUT"
},
"WREN": {
"direction": "IN"
},
"D31": {
"direction": "IN"
},
"Q15": {
"direction": "OUT"
},
"D60": {
"direction": "IN"
},
"WRCLK": {
"direction": "IN"
},
"Q65": {
"direction": "OUT"
},
"Q93": {
"direction": "OUT"
},
"Q03": {
"direction": "OUT"
},
"D41": {
"direction": "IN"
},
"SCANOUT1": {
"direction": "OUT"
},
"Q76": {
"direction": "OUT"
},
"Q60": {
"direction": "OUT"
},
"D54": {
"direction": "IN"
},
"TESTMODEB": {
"direction": "IN"
},
"Q32": {
"direction": "OUT"
},
"Q77": {
"direction": "OUT"
},
"Q90": {
"direction": "OUT"
},
"Q24": {
"direction": "OUT"
},
"SCANENB": {
"direction": "IN"
},
"Q82": {
"direction": "OUT"
},
"Q37": {
"direction": "OUT"
},
"Q47": {
"direction": "OUT"
},
"Q04": {
"direction": "OUT"
},
"Q06": {
"direction": "OUT"
},
"Q46": {
"direction": "OUT"
},
"D57": {
"direction": "IN"
},
"D30": {
"direction": "IN"
},
"D11": {
"direction": "IN"
},
"Q23": {
"direction": "OUT"
},
"Q40": {
"direction": "OUT"
},
"Q34": {
"direction": "OUT"
},
"Q95": {
"direction": "OUT"
},
"TESTWRITEDISB": {
"direction": "IN"
},
"Q33": {
"direction": "OUT"
},
"EMPTY": {
"direction": "OUT"
},
"Q26": {
"direction": "OUT"
},
"Q84": {
"direction": "OUT"
},
"Q16": {
"direction": "OUT"
},
"SCANIN0": {
"direction": "IN"
},
"D65": {
"direction": "IN"
},
"D93": {
"direction": "IN"
},
"Q30": {
"direction": "OUT"
},
"D42": {
"direction": "IN"
},
"Q71": {
"direction": "OUT"
},
"Q50": {
"direction": "OUT"
},
"RDCLK": {
"direction": "IN"
},
"D92": {
"direction": "IN"
},
"Q20": {
"direction": "OUT"
},
"D72": {
"direction": "IN"
},
"Q10": {
"direction": "OUT"
},
"D91": {
"direction": "IN"
},
"SCANIN1": {
"direction": "IN"
},
"Q97": {
"direction": "OUT"
},
"D80": {
"direction": "IN"
},
"Q05": {
"direction": "OUT"
},
"Q94": {
"direction": "OUT"
},
"RDEN": {
"direction": "IN"
},
"D81": {
"direction": "IN"
},
"D50": {
"direction": "IN"
},
"D55": {
"direction": "IN"
},
"Q92": {
"direction": "OUT"
},
"Q35": {
"direction": "OUT"
},
"Q54": {
"direction": "OUT"
},
"D33": {
"direction": "IN"
},
"D64": {
"direction": "IN"
},
"Q63": {
"direction": "OUT"
},
"D12": {
"direction": "IN"
},
"Q31": {
"direction": "OUT"
},
"Q14": {
"direction": "OUT"
},
"Q56": {
"direction": "OUT"
},
"Q75": {
"direction": "OUT"
},
"Q36": {
"direction": "OUT"
},
"Q86": {
"direction": "OUT"
},
"SCANIN2": {
"direction": "IN"
},
"SCANOUT0": {
"direction": "OUT"
},
"Q45": {
"direction": "OUT"
},
"Q07": {
"direction": "OUT"
},
"D21": {
"direction": "IN"
},
"D32": {
"direction": "IN"
},
"Q00": {
"direction": "OUT"
},
"Q85": {
"direction": "OUT"
},
"D71": {
"direction": "IN"
},
"SCANIN3": {
"direction": "IN"
},
"D10": {
"direction": "IN"
},
"Q67": {
"direction": "OUT"
},
"D01": {
"direction": "IN"
},
"D40": {
"direction": "IN"
},
"D22": {
"direction": "IN"
},
"D00": {
"direction": "IN"
},
"Q13": {
"direction": "OUT"
},
"Q96": {
"direction": "OUT"
},
"D52": {
"direction": "IN"
},
"Q43": {
"direction": "OUT"
},
"Q27": {
"direction": "OUT"
},
"Q01": {
"direction": "OUT"
},
"D82": {
"direction": "IN"
},
"D83": {
"direction": "IN"
},
"Q87": {
"direction": "OUT"
},
"D03": {
"direction": "IN"
},
"Q91": {
"direction": "OUT"
},
"ALMOSTFULL": {
"direction": "OUT"
},
"D62": {
"direction": "IN"
},
"D13": {
"direction": "IN"
},
"Q55": {
"direction": "OUT"
},
"RESET": {
"direction": "IN"
},
"Q51": {
"direction": "OUT"
},
"Q25": {
"direction": "OUT"
},
"Q52": {
"direction": "OUT"
},
"D02": {
"direction": "IN"
},
"Q62": {
"direction": "OUT"
},
"D63": {
"direction": "IN"
},
"Q61": {
"direction": "OUT"
},
"Q70": {
"direction": "OUT"
},
"Q02": {
"direction": "OUT"
},
"Q74": {
"direction": "OUT"
},
"Q66": {
"direction": "OUT"
},
"D70": {
"direction": "IN"
},
"Q83": {
"direction": "OUT"
},
"D61": {
"direction": "IN"
},
"D43": {
"direction": "IN"
},
"Q73": {
"direction": "OUT"
},
"SCANOUT2": {
"direction": "OUT"
},
"D51": {
"direction": "IN"
},
"Q42": {
"direction": "OUT"
},
"Q17": {
"direction": "OUT"
},
"Q11": {
"direction": "OUT"
},
"TESTREADDISB": {
"direction": "IN"
},
"Q72": {
"direction": "OUT"
},
"D20": {
"direction": "IN"
},
"D90": {
"direction": "IN"
},
"Q81": {
"direction": "OUT"
}
}
}

94
kintex7/site_type_IOB18.json Normal file
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{
"type": "IOB18",
"site_pips": {
"DCITERMDISABLE_SEL:I": {
"from_pin": "I",
"to_pin": "OUT"
},
"IBUFDISABLE_SEL:GND": {
"from_pin": "GND",
"to_pin": "OUT"
},
"IUSED:0": {
"from_pin": "0",
"to_pin": "OUT"
},
"OUSED:0": {
"from_pin": "0",
"to_pin": "OUT"
},
"TUSED:0": {
"from_pin": "0",
"to_pin": "OUT"
},
"DIFFI_INUSED:0": {
"from_pin": "0",
"to_pin": "OUT"
},
"IBUFDISABLE_SEL:I": {
"from_pin": "I",
"to_pin": "OUT"
},
"PADOUTUSED:0": {
"from_pin": "0",
"to_pin": "OUT"
},
"DCITERMDISABLE_SEL:GND": {
"from_pin": "GND",
"to_pin": "OUT"
}
},
"site_pins": {
"KEEPER_INT_EN": {
"direction": "IN"
},
"I": {
"direction": "OUT"
},
"T": {
"direction": "IN"
},
"DIFFI_IN": {
"direction": "IN"
},
"T_IN": {
"direction": "IN"
},
"PD_INT_EN": {
"direction": "IN"
},
"O_OUT": {
"direction": "OUT"
},
"DCITERMDISABLE": {
"direction": "IN"
},
"DIFFO_IN": {
"direction": "IN"
},
"DIFFO_OUT": {
"direction": "OUT"
},
"PADOUT": {
"direction": "OUT"
},
"O_IN": {
"direction": "IN"
},
"T_OUT": {
"direction": "OUT"
},
"DIFF_TERM_INT_EN": {
"direction": "IN"
},
"IBUFDISABLE": {
"direction": "IN"
},
"PU_INT_EN": {
"direction": "IN"
},
"O": {
"direction": "IN"
}
}
}

106
kintex7/site_type_IOB18M.json Normal file
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{
"type": "IOB18M",
"site_pips": {
"IBUFDISABLE_SEL:GND": {
"from_pin": "GND",
"to_pin": "OUT"
},
"DIFFO_OUTUSED:0": {
"from_pin": "0",
"to_pin": "OUT"
},
"OUSED:0": {
"from_pin": "0",
"to_pin": "OUT"
},
"T_OUTUSED:0": {
"from_pin": "0",
"to_pin": "OUT"
},
"DIFFI_INUSED:0": {
"from_pin": "0",
"to_pin": "OUT"
},
"DCITERMDISABLE_SEL:GND": {
"from_pin": "GND",
"to_pin": "OUT"
},
"DCITERMDISABLE_SEL:I": {
"from_pin": "I",
"to_pin": "OUT"
},
"O_OUTUSED:0": {
"from_pin": "0",
"to_pin": "OUT"
},
"IUSED:0": {
"from_pin": "0",
"to_pin": "OUT"
},
"TUSED:0": {
"from_pin": "0",
"to_pin": "OUT"
},
"PADOUTUSED:0": {
"from_pin": "0",
"to_pin": "OUT"
},
"IBUFDISABLE_SEL:I": {
"from_pin": "I",
"to_pin": "OUT"
}
},
"site_pins": {
"KEEPER_INT_EN": {
"direction": "IN"
},
"I": {
"direction": "OUT"
},
"T": {
"direction": "IN"
},
"DIFFI_IN": {
"direction": "IN"
},
"T_IN": {
"direction": "IN"
},
"PD_INT_EN": {
"direction": "IN"
},
"O_OUT": {
"direction": "OUT"
},
"DCITERMDISABLE": {
"direction": "IN"
},
"DIFFO_IN": {
"direction": "IN"
},
"DIFFO_OUT": {
"direction": "OUT"
},
"PADOUT": {
"direction": "OUT"
},
"O_IN": {
"direction": "IN"
},
"T_OUT": {
"direction": "OUT"
},
"DIFF_TERM_INT_EN": {
"direction": "IN"
},
"IBUFDISABLE": {
"direction": "IN"
},
"PU_INT_EN": {
"direction": "IN"
},
"O": {
"direction": "IN"
}
}
}

114
kintex7/site_type_IOB18S.json Normal file
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{
"type": "IOB18S",
"site_pips": {
"OUTMUX:1": {
"from_pin": "1",
"to_pin": "OUT"
},
"TINMUX:0": {
"from_pin": "0",
"to_pin": "OUT"
},
"IBUFDISABLE_SEL:GND": {
"from_pin": "GND",
"to_pin": "OUT"
},
"DIFFI_INUSED:0": {
"from_pin": "0",
"to_pin": "OUT"
},
"IBUFDISABLE_SEL:I": {
"from_pin": "I",
"to_pin": "OUT"
},
"OINMUX:0": {
"from_pin": "0",
"to_pin": "OUT"
},
"OINMUX:1": {
"from_pin": "1",
"to_pin": "OUT"
},
"DIFFO_INUSED:0": {
"from_pin": "0",
"to_pin": "OUT"
},
"OUTMUX:0": {
"from_pin": "0",
"to_pin": "OUT"
},
"DCITERMDISABLE_SEL:I": {
"from_pin": "I",
"to_pin": "OUT"
},
"IUSED:0": {
"from_pin": "0",
"to_pin": "OUT"
},
"TINMUX:1": {
"from_pin": "1",
"to_pin": "OUT"
},
"PADOUTUSED:0": {
"from_pin": "0",
"to_pin": "OUT"
},
"DCITERMDISABLE_SEL:GND": {
"from_pin": "GND",
"to_pin": "OUT"
}
},
"site_pins": {
"KEEPER_INT_EN": {
"direction": "IN"
},
"I": {
"direction": "OUT"
},
"T": {
"direction": "IN"
},
"DIFFI_IN": {
"direction": "IN"
},
"T_IN": {
"direction": "IN"
},
"PD_INT_EN": {
"direction": "IN"
},
"O_OUT": {
"direction": "OUT"
},
"DCITERMDISABLE": {
"direction": "IN"
},
"DIFFO_IN": {
"direction": "IN"
},
"DIFFO_OUT": {
"direction": "OUT"
},
"PADOUT": {
"direction": "OUT"
},
"O_IN": {
"direction": "IN"
},
"T_OUT": {
"direction": "OUT"
},
"DIFF_TERM_INT_EN": {
"direction": "IN"
},
"IBUFDISABLE": {
"direction": "IN"
},
"PU_INT_EN": {
"direction": "IN"
},
"O": {
"direction": "IN"
}
}
}

94
kintex7/site_type_IOB33.json Normal file
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{
"type": "IOB33",
"site_pips": {
"INTERMDISABLE_SEL:I": {
"from_pin": "I",
"to_pin": "OUT"
},
"IBUFDISABLE_SEL:GND": {
"from_pin": "GND",
"to_pin": "OUT"
},
"IUSED:0": {
"from_pin": "0",
"to_pin": "OUT"
},
"OUSED:0": {
"from_pin": "0",
"to_pin": "OUT"
},
"TUSED:0": {
"from_pin": "0",
"to_pin": "OUT"
},
"INTERMDISABLE_SEL:GND": {
"from_pin": "GND",
"to_pin": "OUT"
},
"DIFFI_INUSED:0": {
"from_pin": "0",
"to_pin": "OUT"
},
"PADOUTUSED:0": {
"from_pin": "0",
"to_pin": "OUT"
},
"IBUFDISABLE_SEL:I": {
"from_pin": "I",
"to_pin": "OUT"
}
},
"site_pins": {
"KEEPER_INT_EN": {
"direction": "IN"
},
"I": {
"direction": "OUT"
},
"INTERMDISABLE": {
"direction": "IN"
},
"T": {
"direction": "IN"
},
"DIFFI_IN": {
"direction": "IN"
},
"T_IN": {
"direction": "IN"
},
"PD_INT_EN": {
"direction": "IN"
},
"O_OUT": {
"direction": "OUT"
},
"DIFFO_IN": {
"direction": "IN"
},
"DIFFO_OUT": {
"direction": "OUT"
},
"PADOUT": {
"direction": "OUT"
},
"O_IN": {
"direction": "IN"
},
"T_OUT": {
"direction": "OUT"
},
"DIFF_TERM_INT_EN": {
"direction": "IN"
},
"IBUFDISABLE": {
"direction": "IN"
},
"PU_INT_EN": {
"direction": "IN"
},
"O": {
"direction": "IN"
}
}
}

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{
"type": "IOB33M",
"site_pips": {
"IBUFDISABLE_SEL:GND": {
"from_pin": "GND",
"to_pin": "OUT"
},
"DIFFO_OUTUSED:0": {
"from_pin": "0",
"to_pin": "OUT"
},
"OUSED:0": {
"from_pin": "0",
"to_pin": "OUT"
},
"T_OUTUSED:0": {
"from_pin": "0",
"to_pin": "OUT"
},
"INTERMDISABLE_SEL:GND": {
"from_pin": "GND",
"to_pin": "OUT"
},
"DIFFI_INUSED:0": {
"from_pin": "0",
"to_pin": "OUT"
},
"INTERMDISABLE_SEL:I": {
"from_pin": "I",
"to_pin": "OUT"
},
"O_OUTUSED:0": {
"from_pin": "0",
"to_pin": "OUT"
},
"IUSED:0": {
"from_pin": "0",
"to_pin": "OUT"
},
"TUSED:0": {
"from_pin": "0",
"to_pin": "OUT"
},
"PADOUTUSED:0": {
"from_pin": "0",
"to_pin": "OUT"
},
"IBUFDISABLE_SEL:I": {
"from_pin": "I",
"to_pin": "OUT"
}
},
"site_pins": {
"KEEPER_INT_EN": {
"direction": "IN"
},
"I": {
"direction": "OUT"
},
"INTERMDISABLE": {
"direction": "IN"
},
"T": {
"direction": "IN"
},
"DIFFI_IN": {
"direction": "IN"
},
"T_IN": {
"direction": "IN"
},
"PD_INT_EN": {
"direction": "IN"
},
"O_OUT": {
"direction": "OUT"
},
"DIFFO_IN": {
"direction": "IN"
},
"DIFFO_OUT": {
"direction": "OUT"
},
"PADOUT": {
"direction": "OUT"
},
"O_IN": {
"direction": "IN"
},
"T_OUT": {
"direction": "OUT"
},
"DIFF_TERM_INT_EN": {
"direction": "IN"
},
"IBUFDISABLE": {
"direction": "IN"
},
"PU_INT_EN": {
"direction": "IN"
},
"O": {
"direction": "IN"
}
}
}

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kintex7/site_type_IOB33S.json Normal file
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{
"type": "IOB33S",
"site_pips": {
"OUTMUX:1": {
"from_pin": "1",
"to_pin": "OUT"
},
"TINMUX:0": {
"from_pin": "0",
"to_pin": "OUT"
},
"IBUFDISABLE_SEL:GND": {
"from_pin": "GND",
"to_pin": "OUT"
},
"INTERMDISABLE_SEL:GND": {
"from_pin": "GND",
"to_pin": "OUT"
},
"DIFFI_INUSED:0": {
"from_pin": "0",
"to_pin": "OUT"
},
"OINMUX:0": {
"from_pin": "0",
"to_pin": "OUT"
},
"DIFFO_INUSED:0": {
"from_pin": "0",
"to_pin": "OUT"
},
"OUTMUX:0": {
"from_pin": "0",
"to_pin": "OUT"
},
"INTERMDISABLE_SEL:I": {
"from_pin": "I",
"to_pin": "OUT"
},
"OINMUX:1": {
"from_pin": "1",
"to_pin": "OUT"
},
"IUSED:0": {
"from_pin": "0",
"to_pin": "OUT"
},
"TINMUX:1": {
"from_pin": "1",
"to_pin": "OUT"
},
"PADOUTUSED:0": {
"from_pin": "0",
"to_pin": "OUT"
},
"IBUFDISABLE_SEL:I": {
"from_pin": "I",
"to_pin": "OUT"
}
},
"site_pins": {
"KEEPER_INT_EN": {
"direction": "IN"
},
"I": {
"direction": "OUT"
},
"INTERMDISABLE": {
"direction": "IN"
},
"T": {
"direction": "IN"
},
"DIFFI_IN": {
"direction": "IN"
},
"T_IN": {
"direction": "IN"
},
"PD_INT_EN": {
"direction": "IN"
},
"O_OUT": {
"direction": "OUT"
},
"DIFFO_IN": {
"direction": "IN"
},
"DIFFO_OUT": {
"direction": "OUT"
},
"PADOUT": {
"direction": "OUT"
},
"O_IN": {
"direction": "IN"
},
"T_OUT": {
"direction": "OUT"
},
"DIFF_TERM_INT_EN": {
"direction": "IN"
},
"IBUFDISABLE": {
"direction": "IN"
},
"PU_INT_EN": {
"direction": "IN"
},
"O": {
"direction": "IN"
}
}
}

9
kintex7/site_type_IPAD.json Normal file
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{
"type": "IPAD",
"site_pips": {},
"site_pins": {
"O": {
"direction": "OUT"
}
}
}

545
kintex7/site_type_MMCME2_ADV.json Normal file
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{
"type": "MMCME2_ADV",
"site_pips": {
"RSTINV:RST": {
"from_pin": "RST",
"to_pin": "OUT"
},
"CLKINSELINV:CLKINSEL_B": {
"from_pin": "CLKINSEL_B",
"to_pin": "OUT"
},
"PSENINV:PSEN_B": {
"from_pin": "PSEN_B",
"to_pin": "OUT"
},
"CLKINSELINV:CLKINSEL": {
"from_pin": "CLKINSEL",
"to_pin": "OUT"
},
"PWRDWNINV:PWRDWN_B": {
"from_pin": "PWRDWN_B",
"to_pin": "OUT"
},
"RSTINV:RST_B": {
"from_pin": "RST_B",
"to_pin": "OUT"
},
"PSINCDECINV:PSINCDEC": {
"from_pin": "PSINCDEC",
"to_pin": "OUT"
},
"PWRDWNINV:PWRDWN": {
"from_pin": "PWRDWN",
"to_pin": "OUT"
},
"PSENINV:PSEN": {
"from_pin": "PSEN",
"to_pin": "OUT"
},
"PSINCDECINV:PSINCDEC_B": {
"from_pin": "PSINCDEC_B",
"to_pin": "OUT"
}
},
"site_pins": {
"CLKOUT2B": {
"direction": "OUT"
},
"TESTOUT1": {
"direction": "OUT"
},
"TESTOUT51": {
"direction": "OUT"
},
"TESTOUT56": {
"direction": "OUT"
},
"TESTIN11": {
"direction": "IN"
},
"CLKOUT6": {
"direction": "OUT"
},
"TESTOUT31": {
"direction": "OUT"
},
"TESTOUT26": {
"direction": "OUT"
},
"DCLK": {
"direction": "IN"
},
"TESTOUT7": {
"direction": "OUT"
},
"TESTIN31": {
"direction": "IN"
},
"TESTIN14": {
"direction": "IN"
},
"TESTOUT53": {
"direction": "OUT"
},
"RST": {
"direction": "IN"
},
"TESTIN18": {
"direction": "IN"
},
"TESTIN6": {
"direction": "IN"
},
"TESTOUT42": {
"direction": "OUT"
},
"TESTOUT28": {
"direction": "OUT"
},
"TESTIN9": {
"direction": "IN"
},
"TESTOUT43": {
"direction": "OUT"
},
"TESTOUT59": {
"direction": "OUT"
},
"CLKOUT5": {
"direction": "OUT"
},
"CLKOUT2": {
"direction": "OUT"
},
"TESTIN29": {
"direction": "IN"
},
"CLKFBOUT": {
"direction": "OUT"
},
"TESTIN30": {
"direction": "IN"
},
"PSCLK": {
"direction": "IN"
},
"CLKFBSTOPPED": {
"direction": "OUT"
},
"TESTIN23": {
"direction": "IN"
},
"TESTOUT11": {
"direction": "OUT"
},
"TESTIN21": {
"direction": "IN"
},
"TESTOUT41": {
"direction": "OUT"
},
"DADDR5": {
"direction": "IN"
},
"TESTIN22": {
"direction": "IN"
},
"TESTOUT32": {
"direction": "OUT"
},
"TESTIN19": {
"direction": "IN"
},
"TESTOUT5": {
"direction": "OUT"
},
"TESTIN1": {
"direction": "IN"
},
"CLKFBIN": {
"direction": "IN"
},
"TESTOUT29": {
"direction": "OUT"
},
"TESTOUT15": {
"direction": "OUT"
},
"DO12": {
"direction": "OUT"
},
"TESTOUT44": {
"direction": "OUT"
},
"TESTOUT35": {
"direction": "OUT"
},
"DI2": {
"direction": "IN"
},
"CLKINSEL": {
"direction": "IN"
},
"DI13": {
"direction": "IN"
},
"TESTOUT27": {
"direction": "OUT"
},
"TESTOUT4": {
"direction": "OUT"
},
"DRDY": {
"direction": "OUT"
},
"TESTIN20": {
"direction": "IN"
},
"TESTOUT22": {
"direction": "OUT"
},
"DO5": {
"direction": "OUT"
},
"TESTOUT49": {
"direction": "OUT"
},
"TESTIN17": {
"direction": "IN"
},
"TESTOUT19": {
"direction": "OUT"
},
"DO8": {
"direction": "OUT"
},
"DADDR3": {
"direction": "IN"
},
"DO3": {
"direction": "OUT"
},
"TESTIN8": {
"direction": "IN"
},
"DI8": {
"direction": "IN"
},
"TESTOUT61": {
"direction": "OUT"
},
"TESTOUT12": {
"direction": "OUT"
},
"TESTOUT57": {
"direction": "OUT"
},
"TESTOUT18": {
"direction": "OUT"
},
"TESTOUT9": {
"direction": "OUT"
},
"DO4": {
"direction": "OUT"
},
"TESTOUT3": {
"direction": "OUT"
},
"TESTOUT6": {
"direction": "OUT"
},
"TESTOUT17": {
"direction": "OUT"
},
"TESTOUT40": {
"direction": "OUT"
},
"TESTOUT2": {
"direction": "OUT"
},
"DI0": {
"direction": "IN"
},
"DI11": {
"direction": "IN"
},
"CLKFBOUTB": {
"direction": "OUT"
},
"DWE": {
"direction": "IN"
},
"TESTOUT16": {
"direction": "OUT"
},
"TESTIN13": {
"direction": "IN"
},
"DI6": {
"direction": "IN"
},
"TMUXOUT": {
"direction": "OUT"
},
"DADDR2": {
"direction": "IN"
},
"TESTOUT13": {
"direction": "OUT"
},
"DADDR1": {
"direction": "IN"
},
"DO1": {
"direction": "OUT"
},
"TESTOUT23": {
"direction": "OUT"
},
"TESTIN2": {
"direction": "IN"
},
"TESTOUT8": {
"direction": "OUT"
},
"CLKOUT0": {
"direction": "OUT"
},
"DO11": {
"direction": "OUT"
},
"TESTOUT47": {
"direction": "OUT"
},
"TESTOUT21": {
"direction": "OUT"
},
"DO7": {
"direction": "OUT"
},
"DI10": {
"direction": "IN"
},
"TESTOUT38": {
"direction": "OUT"
},
"TESTIN28": {
"direction": "IN"
},
"TESTOUT63": {
"direction": "OUT"
},
"TESTOUT33": {
"direction": "OUT"
},
"TESTOUT52": {
"direction": "OUT"
},
"TESTOUT20": {
"direction": "OUT"
},
"CLKOUT3": {
"direction": "OUT"
},
"DO0": {
"direction": "OUT"
},
"TESTOUT34": {
"direction": "OUT"
},
"DO13": {
"direction": "OUT"
},
"TESTOUT24": {
"direction": "OUT"
},
"TESTIN27": {
"direction": "IN"
},
"TESTOUT58": {
"direction": "OUT"
},
"TESTIN3": {
"direction": "IN"
},
"TESTOUT0": {
"direction": "OUT"
},
"DO15": {
"direction": "OUT"
},
"DI1": {
"direction": "IN"
},
"CLKOUT0B": {
"direction": "OUT"
},
"DADDR4": {
"direction": "IN"
},
"TESTOUT55": {
"direction": "OUT"
},
"TESTOUT10": {
"direction": "OUT"
},
"TESTIN15": {
"direction": "IN"
},
"TESTIN25": {
"direction": "IN"
},
"TESTOUT37": {
"direction": "OUT"
},
"DEN": {
"direction": "IN"
},
"DI14": {
"direction": "IN"
},
"TESTOUT62": {
"direction": "OUT"
},
"DI9": {
"direction": "IN"
},
"DI7": {
"direction": "IN"
},
"TESTIN10": {
"direction": "IN"
},
"TESTOUT36": {
"direction": "OUT"
},
"DI4": {
"direction": "IN"
},
"DI5": {
"direction": "IN"
},
"DI12": {
"direction": "IN"
},
"TESTIN0": {
"direction": "IN"
},
"TESTOUT46": {
"direction": "OUT"
},
"TESTIN7": {
"direction": "IN"
},
"CLKOUT3B": {
"direction": "OUT"
},
"DO10": {
"direction": "OUT"
},
"TESTOUT14": {
"direction": "OUT"
},
"LOCKED": {
"direction": "OUT"
},
"DO14": {
"direction": "OUT"
},
"CLKOUT1": {
"direction": "OUT"
},
"TESTOUT54": {
"direction": "OUT"
},
"PSEN": {
"direction": "IN"
},
"TESTIN4": {
"direction": "IN"
},
"CLKIN2": {
"direction": "IN"
},
"CLKIN1": {
"direction": "IN"
},
"TESTOUT50": {
"direction": "OUT"
},
"CLKOUT4": {
"direction": "OUT"
},
"DO9": {
"direction": "OUT"
},
"DO6": {
"direction": "OUT"
},
"DADDR6": {
"direction": "IN"
},
"PWRDWN": {
"direction": "IN"
},
"DI15": {
"direction": "IN"
},
"DO2": {
"direction": "OUT"
},
"TESTOUT39": {
"direction": "OUT"
},
"TESTOUT48": {
"direction": "OUT"
},
"DADDR0": {
"direction": "IN"
},
"TESTIN26": {
"direction": "IN"
},
"CLKINSTOPPED": {
"direction": "OUT"
},
"PSDONE": {
"direction": "OUT"
},
"DI3": {
"direction": "IN"
},
"TESTOUT30": {
"direction": "OUT"
},
"TESTOUT25": {
"direction": "OUT"
},
"PSINCDEC": {
"direction": "IN"
},
"TESTIN12": {
"direction": "IN"
},
"TESTIN24": {
"direction": "IN"
},
"TESTOUT60": {
"direction": "OUT"
},
"TESTIN16": {
"direction": "IN"
},
"CLKOUT1B": {
"direction": "OUT"
},
"TESTIN5": {
"direction": "IN"
},
"TESTOUT45": {
"direction": "OUT"
}
}
}

92
kintex7/site_type_ODELAYE2.json Normal file
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{
"type": "ODELAYE2",
"site_pips": {
"ODATAININV:ODATAIN_B": {
"from_pin": "ODATAIN_B",
"to_pin": "OUT"
},
"ODATAININV:ODATAIN": {
"from_pin": "ODATAIN",
"to_pin": "OUT"
},
"CINV:C": {
"from_pin": "C",
"to_pin": "OUT"
},
"CINV:C_B": {
"from_pin": "C_B",
"to_pin": "OUT"
}
},
"site_pins": {
"CLKIN": {
"direction": "IN"
},
"CNTVALUEOUT1": {
"direction": "OUT"
},
"CNTVALUEIN1": {
"direction": "IN"
},
"ODATAIN": {
"direction": "IN"
},
"OFDLY0": {
"direction": "IN"
},
"CE": {
"direction": "IN"
},
"DATAOUT": {
"direction": "OUT"
},
"CNTVALUEIN0": {
"direction": "IN"
},
"CNTVALUEIN4": {
"direction": "IN"
},
"CNTVALUEOUT2": {
"direction": "OUT"
},
"C": {
"direction": "IN"
},
"CNTVALUEOUT0": {
"direction": "OUT"
},
"CNTVALUEIN2": {
"direction": "IN"
},
"OFDLY2": {
"direction": "IN"
},
"LDPIPEEN": {
"direction": "IN"
},
"CINVCTRL": {
"direction": "IN"
},
"CNTVALUEOUT3": {
"direction": "OUT"
},
"INC": {
"direction": "IN"
},
"CNTVALUEOUT4": {
"direction": "OUT"
},
"CNTVALUEIN3": {
"direction": "IN"
},
"OFDLY1": {
"direction": "IN"
},
"REGRST": {
"direction": "IN"
},
"LD": {
"direction": "IN"
}
}
}

210
kintex7/site_type_OLOGICE2.json Normal file
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{
"type": "OLOGICE2",
"site_pips": {
"TMUX:TFF": {
"from_pin": "TFF",
"to_pin": "OUT"
},
"CLKINV:CLK": {
"from_pin": "CLK",
"to_pin": "OUT"
},
"D1INV:D1_B": {
"from_pin": "D1_B",
"to_pin": "OUT"
},
"O1USED:0": {
"from_pin": "0",
"to_pin": "OUT"
},
"TCEUSED:0": {
"from_pin": "0",
"to_pin": "OUT"
},
"D2INV:D2": {
"from_pin": "D2",
"to_pin": "OUT"
},
"T2INV:T2": {
"from_pin": "T2",
"to_pin": "OUT"
},
"OREVUSED:0": {
"from_pin": "0",
"to_pin": "OUT"
},
"OMUX:OUTFF": {
"from_pin": "OUTFF",
"to_pin": "OUT"
},
"TQUSED:0": {
"from_pin": "0",
"to_pin": "OUT"
},
"T1INV:T1_B": {
"from_pin": "T1_B",
"to_pin": "OUT"
},
"OSRUSED:0": {
"from_pin": "0",
"to_pin": "OUT"
},
"D2INV:D2_B": {
"from_pin": "D2_B",
"to_pin": "OUT"
},
"OCEUSED:0": {
"from_pin": "0",
"to_pin": "OUT"
},
"T1INV:T1": {
"from_pin": "T1",
"to_pin": "OUT"
},
"OFBUSED:0": {
"from_pin": "0",
"to_pin": "OUT"
},
"OMUX:D1": {
"from_pin": "D1",
"to_pin": "OUT"
},
"TFBUSED:0": {
"from_pin": "0",
"to_pin": "OUT"
},
"TSRUSED:0": {
"from_pin": "0",
"to_pin": "OUT"
},
"TMUX:T1": {
"from_pin": "T1",
"to_pin": "OUT"
},
"T1USED:0": {
"from_pin": "0",
"to_pin": "OUT"
},
"D1INV:D1": {
"from_pin": "D1",
"to_pin": "OUT"
},
"T2INV:T2_B": {
"from_pin": "T2_B",
"to_pin": "OUT"
},
"TREVUSED:0": {
"from_pin": "0",
"to_pin": "OUT"
},
"OQUSED:0": {
"from_pin": "0",
"to_pin": "OUT"
},
"CLKINV:CLK_B": {
"from_pin": "CLK_B",
"to_pin": "OUT"
}
},
"site_pins": {
"T1": {
"direction": "IN"
},
"T2": {
"direction": "IN"
},
"TQ": {
"direction": "OUT"
},
"OFB": {
"direction": "OUT"
},
"TBYTEOUT": {
"direction": "OUT"
},
"REV": {
"direction": "IN"
},
"CLKDIVFB": {
"direction": "IN"
},
"TBYTEIN": {
"direction": "IN"
},
"CLKDIVF": {
"direction": "IN"
},
"SHIFTOUT1": {
"direction": "OUT"
},
"CLKDIV": {
"direction": "IN"
},
"CLKB": {
"direction": "IN"
},
"D7": {
"direction": "IN"
},
"TFB": {
"direction": "OUT"
},
"SHIFTIN1": {
"direction": "IN"
},
"CLK": {
"direction": "IN"
},
"SHIFTOUT2": {
"direction": "OUT"
},
"SHIFTIN2": {
"direction": "IN"
},
"D3": {
"direction": "IN"
},
"T4": {
"direction": "IN"
},
"D6": {
"direction": "IN"
},
"D4": {
"direction": "IN"
},
"OQ": {
"direction": "OUT"
},
"OCE": {
"direction": "IN"
},
"T3": {
"direction": "IN"
},
"D1": {
"direction": "IN"
},
"TCE": {
"direction": "IN"
},
"IOCLKGLITCH": {
"direction": "OUT"
},
"SR": {
"direction": "IN"
},
"CLKDIVB": {
"direction": "IN"
},
"D2": {
"direction": "IN"
},
"D5": {
"direction": "IN"
},
"D8": {
"direction": "IN"
}
}
}

210
kintex7/site_type_OLOGICE3.json Normal file
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@ -0,0 +1,210 @@
{
"type": "OLOGICE3",
"site_pips": {
"TMUX:TFF": {
"from_pin": "TFF",
"to_pin": "OUT"
},
"CLKINV:CLK": {
"from_pin": "CLK",
"to_pin": "OUT"
},
"D1INV:D1_B": {
"from_pin": "D1_B",
"to_pin": "OUT"
},
"O1USED:0": {
"from_pin": "0",
"to_pin": "OUT"
},
"TCEUSED:0": {
"from_pin": "0",
"to_pin": "OUT"
},
"D2INV:D2": {
"from_pin": "D2",
"to_pin": "OUT"
},
"T2INV:T2": {
"from_pin": "T2",
"to_pin": "OUT"
},
"OREVUSED:0": {
"from_pin": "0",
"to_pin": "OUT"
},
"OMUX:OUTFF": {
"from_pin": "OUTFF",
"to_pin": "OUT"
},
"TQUSED:0": {
"from_pin": "0",
"to_pin": "OUT"
},
"T1INV:T1_B": {
"from_pin": "T1_B",
"to_pin": "OUT"
},
"OSRUSED:0": {
"from_pin": "0",
"to_pin": "OUT"
},
"D2INV:D2_B": {
"from_pin": "D2_B",
"to_pin": "OUT"
},
"OCEUSED:0": {
"from_pin": "0",
"to_pin": "OUT"
},
"T1INV:T1": {
"from_pin": "T1",
"to_pin": "OUT"
},
"OFBUSED:0": {
"from_pin": "0",
"to_pin": "OUT"
},
"OMUX:D1": {
"from_pin": "D1",
"to_pin": "OUT"
},
"TFBUSED:0": {
"from_pin": "0",
"to_pin": "OUT"
},
"TSRUSED:0": {
"from_pin": "0",
"to_pin": "OUT"
},
"TMUX:T1": {
"from_pin": "T1",
"to_pin": "OUT"
},
"T1USED:0": {
"from_pin": "0",
"to_pin": "OUT"
},
"D1INV:D1": {
"from_pin": "D1",
"to_pin": "OUT"
},
"T2INV:T2_B": {
"from_pin": "T2_B",
"to_pin": "OUT"
},
"TREVUSED:0": {
"from_pin": "0",
"to_pin": "OUT"
},
"OQUSED:0": {
"from_pin": "0",
"to_pin": "OUT"
},
"CLKINV:CLK_B": {
"from_pin": "CLK_B",
"to_pin": "OUT"
}
},
"site_pins": {
"T1": {
"direction": "IN"
},
"T2": {
"direction": "IN"
},
"TQ": {
"direction": "OUT"
},
"OFB": {
"direction": "OUT"
},
"TBYTEOUT": {
"direction": "OUT"
},
"REV": {
"direction": "IN"
},
"CLKDIVFB": {
"direction": "IN"
},
"TBYTEIN": {
"direction": "IN"
},
"CLKDIVF": {
"direction": "IN"
},
"SHIFTOUT1": {
"direction": "OUT"
},
"CLKDIV": {
"direction": "IN"
},
"CLKB": {
"direction": "IN"
},
"D7": {
"direction": "IN"
},
"TFB": {
"direction": "OUT"
},
"SHIFTIN1": {
"direction": "IN"
},
"CLK": {
"direction": "IN"
},
"SHIFTOUT2": {
"direction": "OUT"
},
"SHIFTIN2": {
"direction": "IN"
},
"D3": {
"direction": "IN"
},
"T4": {
"direction": "IN"
},
"D6": {
"direction": "IN"
},
"D4": {
"direction": "IN"
},
"OQ": {
"direction": "OUT"
},
"OCE": {
"direction": "IN"
},
"T3": {
"direction": "IN"
},
"D1": {
"direction": "IN"
},
"TCE": {
"direction": "IN"
},
"IOCLKGLITCH": {
"direction": "OUT"
},
"SR": {
"direction": "IN"
},
"CLKDIVB": {
"direction": "IN"
},
"D2": {
"direction": "IN"
},
"D5": {
"direction": "IN"
},
"D8": {
"direction": "IN"
}
}
}

9
kintex7/site_type_OPAD.json Normal file
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@ -0,0 +1,9 @@
{
"type": "OPAD",
"site_pips": {},
"site_pins": {
"I": {
"direction": "IN"
}
}
}

453
kintex7/site_type_OUT_FIFO.json Normal file
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@ -0,0 +1,453 @@
{
"type": "OUT_FIFO",
"site_pips": {},
"site_pins": {
"Q53": {
"direction": "OUT"
},
"ALMOSTEMPTY": {
"direction": "OUT"
},
"D53": {
"direction": "IN"
},
"D31": {
"direction": "IN"
},
"D77": {
"direction": "IN"
},
"D16": {
"direction": "IN"
},
"D73": {
"direction": "IN"
},
"D56": {
"direction": "IN"
},
"Q64": {
"direction": "OUT"
},
"Q57": {
"direction": "OUT"
},
"Q12": {
"direction": "OUT"
},
"D66": {
"direction": "IN"
},
"D51": {
"direction": "IN"
},
"Q41": {
"direction": "OUT"
},
"FULL": {
"direction": "OUT"
},
"D71": {
"direction": "IN"
},
"SCANOUT3": {
"direction": "OUT"
},
"Q22": {
"direction": "OUT"
},
"D26": {
"direction": "IN"
},
"D67": {
"direction": "IN"
},
"D25": {
"direction": "IN"
},
"D13": {
"direction": "IN"
},
"WREN": {
"direction": "IN"
},
"D87": {
"direction": "IN"
},
"D85": {
"direction": "IN"
},
"D86": {
"direction": "IN"
},
"Q65": {
"direction": "OUT"
},
"D95": {
"direction": "IN"
},
"Q03": {
"direction": "OUT"
},
"D41": {
"direction": "IN"
},
"Q62": {
"direction": "OUT"
},
"SCANOUT1": {
"direction": "OUT"
},
"D00": {
"direction": "IN"
},
"Q60": {
"direction": "OUT"
},
"D54": {
"direction": "IN"
},
"Q32": {
"direction": "OUT"
},
"D45": {
"direction": "IN"
},
"Q90": {
"direction": "OUT"
},
"D07": {
"direction": "IN"
},
"SCANENB": {
"direction": "IN"
},
"SCANOUT0": {
"direction": "OUT"
},
"D84": {
"direction": "IN"
},
"D50": {
"direction": "IN"
},
"D63": {
"direction": "IN"
},
"D46": {
"direction": "IN"
},
"D62": {
"direction": "IN"
},
"D30": {
"direction": "IN"
},
"D11": {
"direction": "IN"
},
"Q23": {
"direction": "OUT"
},
"D23": {
"direction": "IN"
},
"TESTWRITEDISB": {
"direction": "IN"
},
"Q33": {
"direction": "OUT"
},
"D22": {
"direction": "IN"
},
"D47": {
"direction": "IN"
},
"SCANIN0": {
"direction": "IN"
},
"Q20": {
"direction": "OUT"
},
"D93": {
"direction": "IN"
},
"Q30": {
"direction": "OUT"
},
"D42": {
"direction": "IN"
},
"Q71": {
"direction": "OUT"
},
"Q13": {
"direction": "OUT"
},
"D44": {
"direction": "IN"
},
"D92": {
"direction": "IN"
},
"Q40": {
"direction": "OUT"
},
"D14": {
"direction": "IN"
},
"D91": {
"direction": "IN"
},
"SCANIN1": {
"direction": "IN"
},
"D80": {
"direction": "IN"
},
"Q43": {
"direction": "OUT"
},
"D24": {
"direction": "IN"
},
"D72": {
"direction": "IN"
},
"D81": {
"direction": "IN"
},
"D06": {
"direction": "IN"
},
"Q91": {
"direction": "OUT"
},
"D55": {
"direction": "IN"
},
"Q92": {
"direction": "OUT"
},
"D36": {
"direction": "IN"
},
"Q54": {
"direction": "OUT"
},
"D33": {
"direction": "IN"
},
"D64": {
"direction": "IN"
},
"Q63": {
"direction": "OUT"
},
"D12": {
"direction": "IN"
},
"Q31": {
"direction": "OUT"
},
"D76": {
"direction": "IN"
},
"D94": {
"direction": "IN"
},
"D43": {
"direction": "IN"
},
"SCANIN2": {
"direction": "IN"
},
"D35": {
"direction": "IN"
},
"Q82": {
"direction": "OUT"
},
"D05": {
"direction": "IN"
},
"ALMOSTFULL": {
"direction": "OUT"
},
"D74": {
"direction": "IN"
},
"D21": {
"direction": "IN"
},
"SCANOUT2": {
"direction": "OUT"
},
"Q00": {
"direction": "OUT"
},
"Q21": {
"direction": "OUT"
},
"D03": {
"direction": "IN"
},
"WRCLK": {
"direction": "IN"
},
"SCANIN3": {
"direction": "IN"
},
"D27": {
"direction": "IN"
},
"D10": {
"direction": "IN"
},
"Q67": {
"direction": "OUT"
},
"D01": {
"direction": "IN"
},
"D40": {
"direction": "IN"
},
"EMPTY": {
"direction": "OUT"
},
"D65": {
"direction": "IN"
},
"Q50": {
"direction": "OUT"
},
"Q10": {
"direction": "OUT"
},
"D52": {
"direction": "IN"
},
"D17": {
"direction": "IN"
},
"D34": {
"direction": "IN"
},
"Q01": {
"direction": "OUT"
},
"D82": {
"direction": "IN"
},
"D83": {
"direction": "IN"
},
"D32": {
"direction": "IN"
},
"D15": {
"direction": "IN"
},
"D96": {
"direction": "IN"
},
"Q66": {
"direction": "OUT"
},
"TESTMODEB": {
"direction": "IN"
},
"D37": {
"direction": "IN"
},
"Q55": {
"direction": "OUT"
},
"RESET": {
"direction": "IN"
},
"D97": {
"direction": "IN"
},
"Q52": {
"direction": "OUT"
},
"D75": {
"direction": "IN"
},
"D02": {
"direction": "IN"
},
"D60": {
"direction": "IN"
},
"Q72": {
"direction": "OUT"
},
"Q61": {
"direction": "OUT"
},
"Q70": {
"direction": "OUT"
},
"Q02": {
"direction": "OUT"
},
"Q80": {
"direction": "OUT"
},
"RDCLK": {
"direction": "IN"
},
"D70": {
"direction": "IN"
},
"Q83": {
"direction": "OUT"
},
"D61": {
"direction": "IN"
},
"RDEN": {
"direction": "IN"
},
"Q73": {
"direction": "OUT"
},
"D04": {
"direction": "IN"
},
"Q56": {
"direction": "OUT"
},
"Q42": {
"direction": "OUT"
},
"Q93": {
"direction": "OUT"
},
"Q11": {
"direction": "OUT"
},
"TESTREADDISB": {
"direction": "IN"
},
"D57": {
"direction": "IN"
},
"D20": {
"direction": "IN"
},
"D90": {
"direction": "IN"
},
"Q81": {
"direction": "OUT"
},
"Q51": {
"direction": "OUT"
}
}
}

6753
kintex7/site_type_PCIE_2_1.json Normal file
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291
kintex7/site_type_PHASER_IN_PHY.json Normal file
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@ -0,0 +1,291 @@
{
"type": "PHASER_IN_PHY",
"site_pips": {
"RSTINV:RST": {
"from_pin": "RST",
"to_pin": "OUT"
},
"RSTINV:RST_B": {
"from_pin": "RST_B",
"to_pin": "OUT"
}
},
"site_pins": {
"TESTOUT1": {
"direction": "OUT"
},
"TESTIN11": {
"direction": "IN"
},
"ISERDESRST": {
"direction": "OUT"
},
"COUNTERLOADEN": {
"direction": "IN"
},
"STG1REGL1": {
"direction": "IN"
},
"TESTIN0": {
"direction": "IN"
},
"RST": {
"direction": "IN"
},
"TESTIN6": {
"direction": "IN"
},
"STG1REGR1": {
"direction": "OUT"
},
"TESTIN9": {
"direction": "IN"
},
"COUNTERLOADVAL2": {
"direction": "IN"
},
"SCANMODEB": {
"direction": "IN"
},
"COUNTERREADVAL1": {
"direction": "OUT"
},
"COUNTERLOADVAL1": {
"direction": "IN"
},
"COUNTERREADVAL2": {
"direction": "OUT"
},
"STG1REGR8": {
"direction": "OUT"
},
"ENSTG1ADJUSTB": {
"direction": "IN"
},
"BURSTPENDINGPHY": {
"direction": "IN"
},
"COUNTERREADVAL5": {
"direction": "OUT"
},
"RCLK": {
"direction": "OUT"
},
"DQSFOUND": {
"direction": "OUT"
},
"TESTIN1": {
"direction": "IN"
},
"STG1REGR6": {
"direction": "OUT"
},
"FINEENABLE": {
"direction": "IN"
},
"SCANENB": {
"direction": "IN"
},
"STG1REGL4": {
"direction": "IN"
},
"ICLK": {
"direction": "OUT"
},
"STG1REGR2": {
"direction": "OUT"
},
"STG1INCDEC": {
"direction": "IN"
},
"RANKSEL0": {
"direction": "IN"
},
"BURSTPENDING": {
"direction": "IN"
},
"FINEOVERFLOW": {
"direction": "OUT"
},
"TESTIN8": {
"direction": "IN"
},
"COUNTERLOADVAL3": {
"direction": "IN"
},
"STG1REGR5": {
"direction": "OUT"
},
"COUNTERLOADVAL0": {
"direction": "IN"
},
"COUNTERREADVAL4": {
"direction": "OUT"
},
"TESTOUT2": {
"direction": "OUT"
},
"STG1REGR0": {
"direction": "OUT"
},
"COUNTERLOADVAL4": {
"direction": "IN"
},
"COUNTERREADVAL3": {
"direction": "OUT"
},
"SYSCLK": {
"direction": "IN"
},
"STG1OVERFLOW": {
"direction": "OUT"
},
"COUNTERREADEN": {
"direction": "IN"
},
"TESTIN12": {
"direction": "IN"
},
"FINEINC": {
"direction": "IN"
},
"TESTIN3": {
"direction": "IN"
},
"SCANIN": {
"direction": "IN"
},
"COUNTERREADVAL0": {
"direction": "OUT"
},
"RANKSELPHY1": {
"direction": "IN"
},
"EDGEADV": {
"direction": "IN"
},
"SELCALORSTG1": {
"direction": "IN"
},
"SCANOUT": {
"direction": "OUT"
},
"ICLKDIV": {
"direction": "OUT"
},
"TESTOUT0": {
"direction": "OUT"
},
"MEMREFCLK": {
"direction": "IN"
},
"COUNTERLOADVAL5": {
"direction": "IN"
},
"RANKSEL1": {
"direction": "IN"
},
"STG1REGL6": {
"direction": "IN"
},
"STG1REGR4": {
"direction": "OUT"
},
"ENCALIBPHY1": {
"direction": "IN"
},
"STG1REGL0": {
"direction": "IN"
},
"DIVIDERST": {
"direction": "IN"
},
"TESTIN10": {
"direction": "IN"
},
"WRENABLE": {
"direction": "OUT"
},
"STG1REGR7": {
"direction": "OUT"
},
"TESTIN7": {
"direction": "IN"
},
"PHASELOCKED": {
"direction": "OUT"
},
"RSTDQSFIND": {
"direction": "IN"
},
"STG1REGL3": {
"direction": "IN"
},
"RANKSELPHY0": {
"direction": "IN"
},
"SYNCIN": {
"direction": "IN"
},
"TESTOUT3": {
"direction": "OUT"
},
"STG1LOAD": {
"direction": "IN"
},
"ENCALIB0": {
"direction": "IN"
},
"STG1REGL8": {
"direction": "IN"
},
"ENCALIB1": {
"direction": "IN"
},
"ENSTG1": {
"direction": "IN"
},
"STG1REGL7": {
"direction": "IN"
},
"STG1REGL5": {
"direction": "IN"
},
"TESTIN4": {
"direction": "IN"
},
"STG1REGL2": {
"direction": "IN"
},
"FREQREFCLK": {
"direction": "IN"
},
"TESTIN13": {
"direction": "IN"
},
"SCANCLK": {
"direction": "IN"
},
"ENCALIBPHY0": {
"direction": "IN"
},
"STG1READ": {
"direction": "IN"
},
"PHASEREFCLK": {
"direction": "IN"
},
"TESTIN2": {
"direction": "IN"
},
"STG1REGR3": {
"direction": "OUT"
},
"TESTIN5": {
"direction": "IN"
},
"DQSOUTOFRANGE": {
"direction": "OUT"
}
}
}

246
kintex7/site_type_PHASER_OUT_PHY.json Normal file
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@ -0,0 +1,246 @@
{
"type": "PHASER_OUT_PHY",
"site_pips": {
"RSTINV:RST": {
"from_pin": "RST",
"to_pin": "OUT"
},
"RSTINV:RST_B": {
"from_pin": "RST_B",
"to_pin": "OUT"
}
},
"site_pins": {
"TESTOUT1": {
"direction": "OUT"
},
"FINEINC": {
"direction": "IN"
},
"SCANIN": {
"direction": "IN"
},
"COUNTERREADVAL0": {
"direction": "OUT"
},
"COUNTERLOADVAL8": {
"direction": "IN"
},
"TESTOUT3": {
"direction": "OUT"
},
"EDGEADV": {
"direction": "IN"
},
"COUNTERLOADVAL7": {
"direction": "IN"
},
"SCANOUT": {
"direction": "OUT"
},
"DTSBUS1": {
"direction": "OUT"
},
"DQSBUS1": {
"direction": "OUT"
},
"TESTIN14": {
"direction": "IN"
},
"TESTIN0": {
"direction": "IN"
},
"RST": {
"direction": "IN"
},
"TESTIN6": {
"direction": "IN"
},
"TESTIN9": {
"direction": "IN"
},
"COUNTERLOADVAL2": {
"direction": "IN"
},
"TESTIN3": {
"direction": "IN"
},
"TESTOUT0": {
"direction": "OUT"
},
"COARSEOVERFLOW": {
"direction": "OUT"
},
"COARSEINC": {
"direction": "IN"
},
"SCANMODEB": {
"direction": "IN"
},
"CTSBUS0": {
"direction": "OUT"
},
"COUNTERREADVAL1": {
"direction": "OUT"
},
"COUNTERLOADVAL1": {
"direction": "IN"
},
"COUNTERLOADVAL5": {
"direction": "IN"
},
"COUNTERREADVAL2": {
"direction": "OUT"
},
"OCLKDIV": {
"direction": "OUT"
},
"ENCALIBPHY1": {
"direction": "IN"
},
"DIVIDERST": {
"direction": "IN"
},
"TESTIN10": {
"direction": "IN"
},
"COUNTERREADVAL5": {
"direction": "OUT"
},
"TESTIN1": {
"direction": "IN"
},
"DQSBUS0": {
"direction": "OUT"
},
"FINEENABLE": {
"direction": "IN"
},
"TESTIN7": {
"direction": "IN"
},
"TESTIN12": {
"direction": "IN"
},
"COUNTERLOADEN": {
"direction": "IN"
},
"SCANENB": {
"direction": "IN"
},
"OCLK": {
"direction": "OUT"
},
"SELFINEOCLKDELAY": {
"direction": "IN"
},
"DTSBUS0": {
"direction": "OUT"
},
"COUNTERREADVAL8": {
"direction": "OUT"
},
"MEMREFCLK": {
"direction": "IN"
},
"TESTIN4": {
"direction": "IN"
},
"SYNCIN": {
"direction": "IN"
},
"FINEOVERFLOW": {
"direction": "OUT"
},
"TESTIN8": {
"direction": "IN"
},
"TESTIN11": {
"direction": "IN"
},
"COUNTERLOADVAL3": {
"direction": "IN"
},
"ENCALIB0": {
"direction": "IN"
},
"ENCALIB1": {
"direction": "IN"
},
"COUNTERLOADVAL6": {
"direction": "IN"
},
"OSERDESRST": {
"direction": "OUT"
},
"COUNTERLOADVAL0": {
"direction": "IN"
},
"RDENABLE": {
"direction": "OUT"
},
"COUNTERREADVAL4": {
"direction": "OUT"
},
"TESTOUT2": {
"direction": "OUT"
},
"COUNTERLOADVAL4": {
"direction": "IN"
},
"COARSEENABLE": {
"direction": "IN"
},
"OCLKDELAYED": {
"direction": "OUT"
},
"FREQREFCLK": {
"direction": "IN"
},
"TESTIN13": {
"direction": "IN"
},
"COUNTERREADVAL3": {
"direction": "OUT"
},
"SCANCLK": {
"direction": "IN"
},
"SYSCLK": {
"direction": "IN"
},
"BURSTPENDINGPHY": {
"direction": "IN"
},
"ENCALIBPHY0": {
"direction": "IN"
},
"BURSTPENDING": {
"direction": "IN"
},
"PHASEREFCLK": {
"direction": "IN"
},
"TESTIN15": {
"direction": "IN"
},
"COUNTERREADEN": {
"direction": "IN"
},
"COUNTERREADVAL6": {
"direction": "OUT"
},
"COUNTERREADVAL7": {
"direction": "OUT"
},
"TESTIN5": {
"direction": "IN"
},
"TESTIN2": {
"direction": "IN"
},
"CTSBUS1": {
"direction": "OUT"
}
}
}

89
kintex7/site_type_PHASER_REF.json Normal file
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@ -0,0 +1,89 @@
{
"type": "PHASER_REF",
"site_pips": {
"RSTINV:RST": {
"from_pin": "RST",
"to_pin": "OUT"
},
"PWRDWNINV:PWRDWN_B": {
"from_pin": "PWRDWN_B",
"to_pin": "OUT"
},
"PWRDWNINV:PWRDWN": {
"from_pin": "PWRDWN",
"to_pin": "OUT"
},
"RSTINV:RST_B": {
"from_pin": "RST_B",
"to_pin": "OUT"
}
},
"site_pins": {
"TESTIN7": {
"direction": "IN"
},
"TESTOUT1": {
"direction": "OUT"
},
"TESTOUT4": {
"direction": "OUT"
},
"TESTIN0": {
"direction": "IN"
},
"LOCKED": {
"direction": "OUT"
},
"TESTOUT7": {
"direction": "OUT"
},
"TESTIN4": {
"direction": "IN"
},
"CLKOUT": {
"direction": "OUT"
},
"RST": {
"direction": "IN"
},
"TESTOUT3": {
"direction": "OUT"
},
"TESTIN6": {
"direction": "IN"
},
"CLKIN": {
"direction": "IN"
},
"TESTIN3": {
"direction": "IN"
},
"TESTOUT0": {
"direction": "OUT"
},
"TMUXOUT": {
"direction": "OUT"
},
"TESTOUT2": {
"direction": "OUT"
},
"PWRDWN": {
"direction": "IN"
},
"TESTOUT6": {
"direction": "OUT"
},
"TESTOUT5": {
"direction": "OUT"
},
"TESTIN1": {
"direction": "IN"
},
"TESTIN5": {
"direction": "IN"
},
"TESTIN2": {
"direction": "IN"
}
}
}

318
kintex7/site_type_PHY_CONTROL.json Normal file
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@ -0,0 +1,318 @@
{
"type": "PHY_CONTROL",
"site_pips": {},
"site_pins": {
"TESTINPUT2": {
"direction": "IN"
},
"TESTOUTPUT3": {
"direction": "OUT"
},
"TESTOUTPUT0": {
"direction": "OUT"
},
"PHYCTLWD9": {
"direction": "IN"
},
"PHYCTLWD20": {
"direction": "IN"
},
"TESTOUTPUT7": {
"direction": "OUT"
},
"TESTOUTPUT1": {
"direction": "OUT"
},
"OUTBURSTPENDING2": {
"direction": "OUT"
},
"INBURSTPENDING2": {
"direction": "OUT"
},
"TESTINPUT8": {
"direction": "IN"
},
"REFDLLLOCK": {
"direction": "IN"
},
"OUTBURSTPENDING1": {
"direction": "OUT"
},
"PHYCTLWD6": {
"direction": "IN"
},
"PHYCTLWD17": {
"direction": "IN"
},
"WRITECALIBENABLE": {
"direction": "IN"
},
"PHYCTLEMPTY": {
"direction": "OUT"
},
"INRANKA1": {
"direction": "OUT"
},
"PHYCTLFULL": {
"direction": "OUT"
},
"AUXOUTPUT0": {
"direction": "OUT"
},
"TESTOUTPUT2": {
"direction": "OUT"
},
"PHYCTLWD19": {
"direction": "IN"
},
"INRANKD1": {
"direction": "OUT"
},
"PHYCTLWD10": {
"direction": "IN"
},
"PHYCTLWD14": {
"direction": "IN"
},
"PCENABLECALIB0": {
"direction": "OUT"
},
"TESTOUTPUT12": {
"direction": "OUT"
},
"TESTINPUT7": {
"direction": "IN"
},
"TESTSELECT2": {
"direction": "IN"
},
"TESTOUTPUT15": {
"direction": "OUT"
},
"PHYCTLWD11": {
"direction": "IN"
},
"PHYCLK": {
"direction": "IN"
},
"TESTINPUT13": {
"direction": "IN"
},
"AUXOUTPUT2": {
"direction": "OUT"
},
"INRANKB0": {
"direction": "OUT"
},
"TESTINPUT12": {
"direction": "IN"
},
"TESTINPUT11": {
"direction": "IN"
},
"PHYCTLREADY": {
"direction": "OUT"
},
"TESTSELECT0": {
"direction": "IN"
},
"TESTINPUT0": {
"direction": "IN"
},
"INRANKD0": {
"direction": "OUT"
},
"PHYCTLWD7": {
"direction": "IN"
},
"TESTINPUT10": {
"direction": "IN"
},
"PHYCTLWD5": {
"direction": "IN"
},
"INBURSTPENDING3": {
"direction": "OUT"
},
"PHYCTLWD13": {
"direction": "IN"
},
"PHYCTLWD4": {
"direction": "IN"
},
"TESTOUTPUT11": {
"direction": "OUT"
},
"TESTINPUT5": {
"direction": "IN"
},
"PLLLOCK": {
"direction": "IN"
},
"INBURSTPENDING1": {
"direction": "OUT"
},
"PHYCTLWD26": {
"direction": "IN"
},
"PHYCTLWD1": {
"direction": "IN"
},
"OUTBURSTPENDING0": {
"direction": "OUT"
},
"INBURSTPENDING0": {
"direction": "OUT"
},
"TESTOUTPUT8": {
"direction": "OUT"
},
"PCENABLECALIB1": {
"direction": "OUT"
},
"PHYCTLWD31": {
"direction": "IN"
},
"PHYCTLWD22": {
"direction": "IN"
},
"PHYCTLWD16": {
"direction": "IN"
},
"SCANENABLEN": {
"direction": "IN"
},
"INRANKC0": {
"direction": "OUT"
},
"PHYCTLWD15": {
"direction": "IN"
},
"AUXOUTPUT1": {
"direction": "OUT"
},
"PHYCTLWD27": {
"direction": "IN"
},
"TESTINPUT3": {
"direction": "IN"
},
"INRANKB1": {
"direction": "OUT"
},
"TESTOUTPUT13": {
"direction": "OUT"
},
"PHYCTLWD0": {
"direction": "IN"
},
"MEMREFCLK": {
"direction": "IN"
},
"TESTOUTPUT4": {
"direction": "OUT"
},
"TESTINPUT4": {
"direction": "IN"
},
"PHYCTLWD25": {
"direction": "IN"
},
"INRANKA0": {
"direction": "OUT"
},
"PHYCTLWD30": {
"direction": "IN"
},
"PHYCTLWD21": {
"direction": "IN"
},
"TESTINPUT15": {
"direction": "IN"
},
"PHYCTLWD12": {
"direction": "IN"
},
"PHYCTLWD3": {
"direction": "IN"
},
"PHYCTLWD2": {
"direction": "IN"
},
"PHYCTLWD8": {
"direction": "IN"
},
"TESTSELECT1": {
"direction": "IN"
},
"SYNCIN": {
"direction": "IN"
},
"TESTOUTPUT14": {
"direction": "OUT"
},
"PHYCTLWD23": {
"direction": "IN"
},
"PHYCTLWRENABLE": {
"direction": "IN"
},
"AUXOUTPUT3": {
"direction": "OUT"
},
"TESTINPUT9": {
"direction": "IN"
},
"TESTOUTPUT9": {
"direction": "OUT"
},
"TESTOUTPUT10": {
"direction": "OUT"
},
"TESTINPUT1": {
"direction": "IN"
},
"PHYCTLWD28": {
"direction": "IN"
},
"TESTOUTPUT5": {
"direction": "OUT"
},
"TESTINPUT6": {
"direction": "IN"
},
"TESTOUTPUT6": {
"direction": "OUT"
},
"PHYCTLWD24": {
"direction": "IN"
},
"INRANKC1": {
"direction": "OUT"
},
"TESTINPUT14": {
"direction": "IN"
},
"PHYCTLWD29": {
"direction": "IN"
},
"PHYCTLMSTREMPTY": {
"direction": "IN"
},
"RESET": {
"direction": "IN"
},
"READCALIBENABLE": {
"direction": "IN"
},
"PHYCTLALMOSTFULL": {
"direction": "OUT"
},
"PHYCTLWD18": {
"direction": "IN"
},
"OUTBURSTPENDING3": {
"direction": "OUT"
}
}
}

493
kintex7/site_type_PLLE2_ADV.json Normal file
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{
"type": "PLLE2_ADV",
"site_pips": {
"RSTINV:RST": {
"from_pin": "RST",
"to_pin": "OUT"
},
"CLKINSELINV:CLKINSEL_B": {
"from_pin": "CLKINSEL_B",
"to_pin": "OUT"
},
"PWRDWNINV:PWRDWN_B": {
"from_pin": "PWRDWN_B",
"to_pin": "OUT"
},
"PWRDWNINV:PWRDWN": {
"from_pin": "PWRDWN",
"to_pin": "OUT"
},
"CLKINSELINV:CLKINSEL": {
"from_pin": "CLKINSEL",
"to_pin": "OUT"
},
"RSTINV:RST_B": {
"from_pin": "RST_B",
"to_pin": "OUT"
}
},
"site_pins": {
"TESTOUT31": {
"direction": "OUT"
},
"TESTOUT51": {
"direction": "OUT"
},
"TESTOUT56": {
"direction": "OUT"
},
"DO9": {
"direction": "OUT"
},
"TESTOUT26": {
"direction": "OUT"
},
"TESTOUT7": {
"direction": "OUT"
},
"TESTIN31": {
"direction": "IN"
},
"TESTIN14": {
"direction": "IN"
},
"TESTOUT53": {
"direction": "OUT"
},
"RST": {
"direction": "IN"
},
"TESTIN18": {
"direction": "IN"
},
"TESTIN6": {
"direction": "IN"
},
"TESTOUT28": {
"direction": "OUT"
},
"TESTIN9": {
"direction": "IN"
},
"TESTOUT9": {
"direction": "OUT"
},
"TESTOUT59": {
"direction": "OUT"
},
"TESTOUT35": {
"direction": "OUT"
},
"CLKOUT2": {
"direction": "OUT"
},
"TESTIN29": {
"direction": "IN"
},
"CLKFBOUT": {
"direction": "OUT"
},
"TESTIN30": {
"direction": "IN"
},
"TESTIN23": {
"direction": "IN"
},
"TESTOUT11": {
"direction": "OUT"
},
"TESTIN21": {
"direction": "IN"
},
"TESTOUT41": {
"direction": "OUT"
},
"TESTOUT43": {
"direction": "OUT"
},
"TESTIN22": {
"direction": "IN"
},
"TESTOUT32": {
"direction": "OUT"
},
"TESTIN19": {
"direction": "IN"
},
"TESTOUT5": {
"direction": "OUT"
},
"TESTIN1": {
"direction": "IN"
},
"CLKFBIN": {
"direction": "IN"
},
"DI11": {
"direction": "IN"
},
"TESTOUT15": {
"direction": "OUT"
},
"DO12": {
"direction": "OUT"
},
"TESTOUT44": {
"direction": "OUT"
},
"DI2": {
"direction": "IN"
},
"CLKINSEL": {
"direction": "IN"
},
"DI13": {
"direction": "IN"
},
"TESTOUT27": {
"direction": "OUT"
},
"TESTOUT4": {
"direction": "OUT"
},
"DRDY": {
"direction": "OUT"
},
"TESTIN20": {
"direction": "IN"
},
"TESTOUT22": {
"direction": "OUT"
},
"DO5": {
"direction": "OUT"
},
"TESTOUT49": {
"direction": "OUT"
},
"TESTIN17": {
"direction": "IN"
},
"TESTOUT19": {
"direction": "OUT"
},
"DI4": {
"direction": "IN"
},
"DADDR0": {
"direction": "IN"
},
"DADDR3": {
"direction": "IN"
},
"DO3": {
"direction": "OUT"
},
"TESTIN8": {
"direction": "IN"
},
"DI8": {
"direction": "IN"
},
"TESTOUT61": {
"direction": "OUT"
},
"TESTOUT12": {
"direction": "OUT"
},
"TESTOUT57": {
"direction": "OUT"
},
"TESTOUT42": {
"direction": "OUT"
},
"DO4": {
"direction": "OUT"
},
"TESTOUT3": {
"direction": "OUT"
},
"TESTOUT17": {
"direction": "OUT"
},
"TESTOUT40": {
"direction": "OUT"
},
"TESTOUT2": {
"direction": "OUT"
},
"DI0": {
"direction": "IN"
},
"DADDR4": {
"direction": "IN"
},
"DWE": {
"direction": "IN"
},
"TESTOUT16": {
"direction": "OUT"
},
"DCLK": {
"direction": "IN"
},
"DI6": {
"direction": "IN"
},
"TMUXOUT": {
"direction": "OUT"
},
"DADDR2": {
"direction": "IN"
},
"TESTOUT13": {
"direction": "OUT"
},
"DADDR1": {
"direction": "IN"
},
"DO1": {
"direction": "OUT"
},
"TESTOUT23": {
"direction": "OUT"
},
"TESTIN2": {
"direction": "IN"
},
"TESTOUT8": {
"direction": "OUT"
},
"CLKOUT0": {
"direction": "OUT"
},
"DO11": {
"direction": "OUT"
},
"TESTOUT47": {
"direction": "OUT"
},
"TESTOUT21": {
"direction": "OUT"
},
"DADDR5": {
"direction": "IN"
},
"DI10": {
"direction": "IN"
},
"TESTOUT6": {
"direction": "OUT"
},
"TESTIN28": {
"direction": "IN"
},
"TESTOUT63": {
"direction": "OUT"
},
"TESTOUT33": {
"direction": "OUT"
},
"TESTOUT52": {
"direction": "OUT"
},
"TESTOUT20": {
"direction": "OUT"
},
"CLKOUT3": {
"direction": "OUT"
},
"DO0": {
"direction": "OUT"
},
"TESTOUT34": {
"direction": "OUT"
},
"DO13": {
"direction": "OUT"
},
"TESTOUT24": {
"direction": "OUT"
},
"TESTOUT18": {
"direction": "OUT"
},
"TESTOUT54": {
"direction": "OUT"
},
"TESTOUT58": {
"direction": "OUT"
},
"TESTIN3": {
"direction": "IN"
},
"TESTOUT0": {
"direction": "OUT"
},
"DO15": {
"direction": "OUT"
},
"DI1": {
"direction": "IN"
},
"DI5": {
"direction": "IN"
},
"TESTOUT55": {
"direction": "OUT"
},
"TESTOUT10": {
"direction": "OUT"
},
"TESTIN15": {
"direction": "IN"
},
"TESTIN25": {
"direction": "IN"
},
"TESTOUT37": {
"direction": "OUT"
},
"DEN": {
"direction": "IN"
},
"DI14": {
"direction": "IN"
},
"TESTOUT62": {
"direction": "OUT"
},
"DI9": {
"direction": "IN"
},
"TESTOUT1": {
"direction": "OUT"
},
"DI7": {
"direction": "IN"
},
"TESTIN10": {
"direction": "IN"
},
"TESTOUT36": {
"direction": "OUT"
},
"CLKOUT5": {
"direction": "OUT"
},
"DO7": {
"direction": "OUT"
},
"DI12": {
"direction": "IN"
},
"TESTIN0": {
"direction": "IN"
},
"TESTOUT46": {
"direction": "OUT"
},
"TESTIN7": {
"direction": "IN"
},
"TESTOUT38": {
"direction": "OUT"
},
"DO10": {
"direction": "OUT"
},
"LOCKED": {
"direction": "OUT"
},
"DO14": {
"direction": "OUT"
},
"CLKOUT1": {
"direction": "OUT"
},
"TESTIN27": {
"direction": "IN"
},
"TESTOUT14": {
"direction": "OUT"
},
"TESTIN4": {
"direction": "IN"
},
"CLKIN2": {
"direction": "IN"
},
"CLKIN1": {
"direction": "IN"
},
"TESTOUT50": {
"direction": "OUT"
},
"CLKOUT4": {
"direction": "OUT"
},
"TESTIN11": {
"direction": "IN"
},
"DO6": {
"direction": "OUT"
},
"TESTOUT29": {
"direction": "OUT"
},
"DADDR6": {
"direction": "IN"
},
"PWRDWN": {
"direction": "IN"
},
"DI15": {
"direction": "IN"
},
"DO2": {
"direction": "OUT"
},
"TESTOUT39": {
"direction": "OUT"
},
"TESTOUT48": {
"direction": "OUT"
},
"DO8": {
"direction": "OUT"
},
"TESTIN26": {
"direction": "IN"
},
"TESTIN13": {
"direction": "IN"
},
"DI3": {
"direction": "IN"
},
"TESTOUT30": {
"direction": "OUT"
},
"TESTOUT25": {
"direction": "OUT"
},
"TESTIN12": {
"direction": "IN"
},
"TESTIN24": {
"direction": "IN"
},
"TESTOUT60": {
"direction": "OUT"
},
"TESTIN16": {
"direction": "IN"
},
"TESTIN5": {
"direction": "IN"
},
"TESTOUT45": {
"direction": "OUT"
}
}
}

27
kintex7/site_type_PMV2.json Normal file
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@ -0,0 +1,27 @@
{
"type": "PMV2",
"site_pips": {},
"site_pins": {
"A1": {
"direction": "IN"
},
"EN": {
"direction": "IN"
},
"ODIV2": {
"direction": "OUT"
},
"ODIV4": {
"direction": "OUT"
},
"A0": {
"direction": "IN"
},
"A2": {
"direction": "IN"
},
"O": {
"direction": "OUT"
}
}
}

561
kintex7/site_type_RAMB18E1.json Normal file
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@ -0,0 +1,561 @@
{
"type": "RAMB18E1",
"site_pips": {
"RSTRAMBINV:RSTRAMB": {
"from_pin": "RSTRAMB",
"to_pin": "OUT"
},
"RSTREGBINV:RSTREGB": {
"from_pin": "RSTREGB",
"to_pin": "OUT"
},
"CLKBWRCLKINV:CLKBWRCLK": {
"from_pin": "CLKBWRCLK",
"to_pin": "OUT"
},
"REGCLKARDRCLKINV:REGCLKARDRCLK_B": {
"from_pin": "REGCLKARDRCLK_B",
"to_pin": "OUT"
},
"REGCLKBINV:REGCLKB": {
"from_pin": "REGCLKB",
"to_pin": "OUT"
},
"ENARDENINV:ENARDEN": {
"from_pin": "ENARDEN",
"to_pin": "OUT"
},
"REGCLKBINV:REGCLKB_B": {
"from_pin": "REGCLKB_B",
"to_pin": "OUT"
},
"RSTREGARSTREGINV:RSTREGARSTREG_B": {
"from_pin": "RSTREGARSTREG_B",
"to_pin": "OUT"
},
"REGCLKARDRCLKINV:REGCLKARDRCLK": {
"from_pin": "REGCLKARDRCLK",
"to_pin": "OUT"
},
"ENBWRENINV:ENBWREN_B": {
"from_pin": "ENBWREN_B",
"to_pin": "OUT"
},
"CLKARDCLKINV:CLKARDCLK_B": {
"from_pin": "CLKARDCLK_B",
"to_pin": "OUT"
},
"CLKBWRCLKINV:CLKBWRCLK_B": {
"from_pin": "CLKBWRCLK_B",
"to_pin": "OUT"
},
"RSTREGARSTREGINV:RSTREGARSTREG": {
"from_pin": "RSTREGARSTREG",
"to_pin": "OUT"
},
"RSTRAMBINV:RSTRAMB_B": {
"from_pin": "RSTRAMB_B",
"to_pin": "OUT"
},
"RSTREGBINV:RSTREGB_B": {
"from_pin": "RSTREGB_B",
"to_pin": "OUT"
},
"CLKARDCLKINV:CLKARDCLK": {
"from_pin": "CLKARDCLK",
"to_pin": "OUT"
},
"ENBWRENINV:ENBWREN": {
"from_pin": "ENBWREN",
"to_pin": "OUT"
},
"RSTRAMARSTRAMINV:RSTRAMARSTRAM_B": {
"from_pin": "RSTRAMARSTRAM_B",
"to_pin": "OUT"
},
"ENARDENINV:ENARDEN_B": {
"from_pin": "ENARDEN_B",
"to_pin": "OUT"
},
"RSTRAMARSTRAMINV:RSTRAMARSTRAM": {
"from_pin": "RSTRAMARSTRAM",
"to_pin": "OUT"
}
},
"site_pins": {
"DOADO5": {
"direction": "OUT"
},
"DIADI6": {
"direction": "IN"
},
"WEBWE5": {
"direction": "IN"
},
"ADDRARDADDR8": {
"direction": "IN"
},
"WRCOUNT0": {
"direction": "OUT"
},
"ENBWREN": {
"direction": "IN"
},
"DIADI15": {
"direction": "IN"
},
"ADDRARDADDR5": {
"direction": "IN"
},
"WEA1": {
"direction": "IN"
},
"DOBDO11": {
"direction": "OUT"
},
"DOPADOP1": {
"direction": "OUT"
},
"DOPBDOP0": {
"direction": "OUT"
},
"DOADO3": {
"direction": "OUT"
},
"WEBWE7": {
"direction": "IN"
},
"DOADO6": {
"direction": "OUT"
},
"DOBDO12": {
"direction": "OUT"
},
"ADDRARDADDR13": {
"direction": "IN"
},
"DIADI13": {
"direction": "IN"
},
"ADDRBWRADDR9": {
"direction": "IN"
},
"DOADO4": {
"direction": "OUT"
},
"DOBDO6": {
"direction": "OUT"
},
"DOPADOP0": {
"direction": "OUT"
},
"WRCOUNT4": {
"direction": "OUT"
},
"ALMOSTEMPTY": {
"direction": "OUT"
},
"WRCOUNT8": {
"direction": "OUT"
},
"DIBDI4": {
"direction": "IN"
},
"ADDRBWRADDR0": {
"direction": "IN"
},
"ADDRBTIEHIGH1": {
"direction": "IN"
},
"WEA2": {
"direction": "IN"
},
"RDCOUNT7": {
"direction": "OUT"
},
"DOBDO5": {
"direction": "OUT"
},
"CLKBWRCLK": {
"direction": "IN"
},
"RSTREGARSTREG": {
"direction": "IN"
},
"DOADO0": {
"direction": "OUT"
},
"DIBDI13": {
"direction": "IN"
},
"DOADO9": {
"direction": "OUT"
},
"DOBDO2": {
"direction": "OUT"
},
"RDCOUNT1": {
"direction": "OUT"
},
"DIBDI5": {
"direction": "IN"
},
"ADDRATIEHIGH1": {
"direction": "IN"
},
"DOADO11": {
"direction": "OUT"
},
"WRCOUNT1": {
"direction": "OUT"
},
"RDCOUNT10": {
"direction": "OUT"
},
"DIBDI7": {
"direction": "IN"
},
"RSTRAMB": {
"direction": "IN"
},
"DIADI2": {
"direction": "IN"
},
"DIADI5": {
"direction": "IN"
},
"DIADI10": {
"direction": "IN"
},
"DIADI7": {
"direction": "IN"
},
"DIPBDIP1": {
"direction": "IN"
},
"WEBWE4": {
"direction": "IN"
},
"DOBDO13": {
"direction": "OUT"
},
"RDCOUNT11": {
"direction": "OUT"
},
"WEBWE0": {
"direction": "IN"
},
"DOADO1": {
"direction": "OUT"
},
"DOBDO10": {
"direction": "OUT"
},
"ADDRBWRADDR13": {
"direction": "IN"
},
"DOBDO7": {
"direction": "OUT"
},
"ADDRBWRADDR1": {
"direction": "IN"
},
"DIADI9": {
"direction": "IN"
},
"RDCOUNT8": {
"direction": "OUT"
},
"ADDRBWRADDR6": {
"direction": "IN"
},
"ADDRBWRADDR10": {
"direction": "IN"
},
"RSTREGB": {
"direction": "IN"
},
"WRCOUNT10": {
"direction": "OUT"
},
"ADDRARDADDR1": {
"direction": "IN"
},
"DOBDO9": {
"direction": "OUT"
},
"ADDRARDADDR10": {
"direction": "IN"
},
"DOBDO3": {
"direction": "OUT"
},
"REGCEAREGCE": {
"direction": "IN"
},
"ADDRARDADDR12": {
"direction": "IN"
},
"DIBDI1": {
"direction": "IN"
},
"DIBDI6": {
"direction": "IN"
},
"WEBWE2": {
"direction": "IN"
},
"FULL": {
"direction": "OUT"
},
"DIBDI9": {
"direction": "IN"
},
"ADDRATIEHIGH0": {
"direction": "IN"
},
"WRERR": {
"direction": "OUT"
},
"ADDRBTIEHIGH0": {
"direction": "IN"
},
"DOBDO14": {
"direction": "OUT"
},
"WEA0": {
"direction": "IN"
},
"RDCOUNT0": {
"direction": "OUT"
},
"DIBDI2": {
"direction": "IN"
},
"RDCOUNT5": {
"direction": "OUT"
},
"RDERR": {
"direction": "OUT"
},
"ADDRBWRADDR8": {
"direction": "IN"
},
"ENARDEN": {
"direction": "IN"
},
"DIADI0": {
"direction": "IN"
},
"ADDRBWRADDR2": {
"direction": "IN"
},
"DOADO10": {
"direction": "OUT"
},
"DIBDI3": {
"direction": "IN"
},
"WEBWE1": {
"direction": "IN"
},
"DIPADIP1": {
"direction": "IN"
},
"WRCOUNT11": {
"direction": "OUT"
},
"DIBDI8": {
"direction": "IN"
},
"WRCOUNT9": {
"direction": "OUT"
},
"WRCOUNT2": {
"direction": "OUT"
},
"DOADO13": {
"direction": "OUT"
},
"WRCOUNT6": {
"direction": "OUT"
},
"DIBDI11": {
"direction": "IN"
},
"ADDRBWRADDR11": {
"direction": "IN"
},
"ADDRARDADDR9": {
"direction": "IN"
},
"REGCEB": {
"direction": "IN"
},
"ALMOSTFULL": {
"direction": "OUT"
},
"WEBWE3": {
"direction": "IN"
},
"REGCLKARDRCLK": {
"direction": "IN"
},
"RDCOUNT2": {
"direction": "OUT"
},
"WRCOUNT5": {
"direction": "OUT"
},
"DOADO15": {
"direction": "OUT"
},
"ADDRARDADDR7": {
"direction": "IN"
},
"ADDRARDADDR3": {
"direction": "IN"
},
"DIPBDIP0": {
"direction": "IN"
},
"DOPBDOP1": {
"direction": "OUT"
},
"DIADI11": {
"direction": "IN"
},
"ADDRBWRADDR4": {
"direction": "IN"
},
"DIADI12": {
"direction": "IN"
},
"EMPTY": {
"direction": "OUT"
},
"RDCOUNT6": {
"direction": "OUT"
},
"ADDRARDADDR11": {
"direction": "IN"
},
"DOADO12": {
"direction": "OUT"
},
"RDCOUNT4": {
"direction": "OUT"
},
"DIADI4": {
"direction": "IN"
},
"RSTRAMARSTRAM": {
"direction": "IN"
},
"DIADI8": {
"direction": "IN"
},
"RDCOUNT9": {
"direction": "OUT"
},
"DOBDO15": {
"direction": "OUT"
},
"ADDRARDADDR2": {
"direction": "IN"
},
"ADDRBWRADDR7": {
"direction": "IN"
},
"WRCOUNT7": {
"direction": "OUT"
},
"DOBDO8": {
"direction": "OUT"
},
"DIADI1": {
"direction": "IN"
},
"ADDRARDADDR4": {
"direction": "IN"
},
"WRCOUNT3": {
"direction": "OUT"
},
"DOADO14": {
"direction": "OUT"
},
"CLKARDCLK": {
"direction": "IN"
},
"WEA3": {
"direction": "IN"
},
"DIADI14": {
"direction": "IN"
},
"DOBDO4": {
"direction": "OUT"
},
"ADDRBWRADDR5": {
"direction": "IN"
},
"ADDRBWRADDR3": {
"direction": "IN"
},
"DOBDO0": {
"direction": "OUT"
},
"DIPADIP0": {
"direction": "IN"
},
"WEBWE6": {
"direction": "IN"
},
"DIBDI0": {
"direction": "IN"
},
"ADDRBWRADDR12": {
"direction": "IN"
},
"REGCLKB": {
"direction": "IN"
},
"DOADO7": {
"direction": "OUT"
},
"DOADO8": {
"direction": "OUT"
},
"DIBDI15": {
"direction": "IN"
},
"DOBDO1": {
"direction": "OUT"
},
"ADDRARDADDR6": {
"direction": "IN"
},
"DOADO2": {
"direction": "OUT"
},
"DIBDI14": {
"direction": "IN"
},
"DIBDI12": {
"direction": "IN"
},
"DIADI3": {
"direction": "IN"
},
"RDCOUNT3": {
"direction": "OUT"
},
"ADDRARDADDR0": {
"direction": "IN"
},
"DIBDI10": {
"direction": "IN"
}
}
}

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kintex7/site_type_RAMBFIFO36E1.json Normal file
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kintex7/site_type_SLICEL.json Normal file
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{
"type": "SLICEL",
"site_pips": {
"DOUTMUX:CY": {
"from_pin": "CY",
"to_pin": "OUT"
},
"A5FFMUX:IN_A": {
"from_pin": "IN_A",
"to_pin": "OUT"
},
"B6LUT:A4": {
"from_pin": "A4",
"to_pin": "O6"
},
"D5LUT:A3": {
"from_pin": "A3",
"to_pin": "O5"
},
"A6LUT:A4": {
"from_pin": "A4",
"to_pin": "O6"
},
"C5LUT:A5": {
"from_pin": "A5",
"to_pin": "O5"
},
"D6LUT:A4": {
"from_pin": "A4",
"to_pin": "O6"
},
"A5LUT:A5": {
"from_pin": "A5",
"to_pin": "O5"
},
"A6LUT:A2": {
"from_pin": "A2",
"to_pin": "O6"
},
"AOUTMUX:A5Q": {
"from_pin": "A5Q",
"to_pin": "OUT"
},
"D6LUT:A5": {
"from_pin": "A5",
"to_pin": "O6"
},
"BCY0:BX": {
"from_pin": "BX",
"to_pin": "OUT"
},
"CCY0:CX": {
"from_pin": "CX",
"to_pin": "OUT"
},
"AOUTMUX:O5": {
"from_pin": "O5",
"to_pin": "OUT"
},
"AFFMUX:CY": {
"from_pin": "CY",
"to_pin": "OUT"
},
"SRUSEDMUX:0": {
"from_pin": "0",
"to_pin": "OUT"
},
"DFFMUX:XOR": {
"from_pin": "XOR",
"to_pin": "OUT"
},
"A5LUT:A3": {
"from_pin": "A3",
"to_pin": "O5"
},
"BOUTMUX:B5Q": {
"from_pin": "B5Q",
"to_pin": "OUT"
},
"BOUTMUX:F8": {
"from_pin": "F8",
"to_pin": "OUT"
},
"DFFMUX:CARRY4_MUX": {
"from_pin": "CARRY4_MUX",
"to_pin": "OUT"
},
"DOUTMUX:O6": {
"from_pin": "O6",
"to_pin": "OUT"
},
"AFFMUX:CARRY4_MUX": {
"from_pin": "CARRY4_MUX",
"to_pin": "OUT"
},
"DFFMUX:DX": {
"from_pin": "DX",
"to_pin": "OUT"
},
"BUSED:0": {
"from_pin": "0",
"to_pin": "OUT"
},
"DOUTMUX:CARRY4_MUX": {
"from_pin": "CARRY4_MUX",
"to_pin": "OUT"
},
"BFFMUX:O6": {
"from_pin": "O6",
"to_pin": "OUT"
},
"BFFMUX:O5": {
"from_pin": "O5",
"to_pin": "OUT"
},
"BFFMUX:XOR": {
"from_pin": "XOR",
"to_pin": "OUT"
},
"D5LUT:A4": {
"from_pin": "A4",
"to_pin": "O5"
},
"D5LUT:A2": {
"from_pin": "A2",
"to_pin": "O5"
},
"COUTMUX:CARRY4_MUX": {
"from_pin": "CARRY4_MUX",
"to_pin": "OUT"
},
"D6LUT:A1": {
"from_pin": "A1",
"to_pin": "O6"
},
"CLKINV:CLK_B": {
"from_pin": "CLK_B",
"to_pin": "OUT"
},
"B6LUT:A1": {
"from_pin": "A1",
"to_pin": "O6"
},
"BOUTMUX:O5": {
"from_pin": "O5",
"to_pin": "OUT"
},
"AOUTMUX:XOR": {
"from_pin": "XOR",
"to_pin": "OUT"
},
"B6LUT:A6": {
"from_pin": "A6",
"to_pin": "O6"
},
"C6LUT:A4": {
"from_pin": "A4",
"to_pin": "O6"
},
"C6LUT:A1": {
"from_pin": "A1",
"to_pin": "O6"
},
"BOUTMUX:XOR": {
"from_pin": "XOR",
"to_pin": "OUT"
},
"B5FFMUX:IN_B": {
"from_pin": "IN_B",
"to_pin": "OUT"
},
"CFFMUX:CY": {
"from_pin": "CY",
"to_pin": "OUT"
},
"DFFMUX:O5": {
"from_pin": "O5",
"to_pin": "OUT"
},
"D5FFMUX:IN_B": {
"from_pin": "IN_B",
"to_pin": "OUT"
},
"AFFMUX:O6": {
"from_pin": "O6",
"to_pin": "OUT"
},
"ACY0:O5": {
"from_pin": "O5",
"to_pin": "OUT"
},
"CFFMUX:CARRY4_MUX": {
"from_pin": "CARRY4_MUX",
"to_pin": "OUT"
},
"BOUTMUX:CARRY4_XOR": {
"from_pin": "CARRY4_XOR",
"to_pin": "OUT"
},
"DOUTMUX:O5": {
"from_pin": "O5",
"to_pin": "OUT"
},
"DOUTMUX:XOR": {
"from_pin": "XOR",
"to_pin": "OUT"
},
"DFFMUX:CARRY4_XOR": {
"from_pin": "CARRY4_XOR",
"to_pin": "OUT"
},
"A6LUT:A6": {
"from_pin": "A6",
"to_pin": "O6"
},
"DOUTMUX:D5Q": {
"from_pin": "D5Q",
"to_pin": "OUT"
},
"PRECYINIT:CIN": {
"from_pin": "CIN",
"to_pin": "OUT"
},
"AOUTMUX:CARRY4_XOR": {
"from_pin": "CARRY4_XOR",
"to_pin": "OUT"
},
"DCY0:O5": {
"from_pin": "O5",
"to_pin": "OUT"
},
"A5LUT:A2": {
"from_pin": "A2",
"to_pin": "O5"
},
"A5LUT:A1": {
"from_pin": "A1",
"to_pin": "O5"
},
"C5LUT:A3": {
"from_pin": "A3",
"to_pin": "O5"
},
"PRECYINIT:1": {
"from_pin": "1",
"to_pin": "OUT"
},
"B6LUT:A2": {
"from_pin": "A2",
"to_pin": "O6"
},
"A6LUT:A3": {
"from_pin": "A3",
"to_pin": "O6"
},
"BOUTMUX:O6": {
"from_pin": "O6",
"to_pin": "OUT"
},
"PRECYINIT:0": {
"from_pin": "0",
"to_pin": "OUT"
},
"ACY0:AX": {
"from_pin": "AX",
"to_pin": "OUT"
},
"C5FFMUX:IN_A": {
"from_pin": "IN_A",
"to_pin": "OUT"
},
"COUTUSED:CARRY4_0": {
"from_pin": "CARRY4_0",
"to_pin": "OUT"
},
"B5LUT:A4": {
"from_pin": "A4",
"to_pin": "O5"
},
"CFFMUX:CARRY4_XOR": {
"from_pin": "CARRY4_XOR",
"to_pin": "OUT"
},
"D5LUT:A5": {
"from_pin": "A5",
"to_pin": "O5"
},
"C5FFMUX:IN_B": {
"from_pin": "IN_B",
"to_pin": "OUT"
},
"BFFMUX:F8": {
"from_pin": "F8",
"to_pin": "OUT"
},
"BFFMUX:CY": {
"from_pin": "CY",
"to_pin": "OUT"
},
"AOUTMUX:O6": {
"from_pin": "O6",
"to_pin": "OUT"
},
"CFFMUX:O5": {
"from_pin": "O5",
"to_pin": "OUT"
},
"DUSED:0": {
"from_pin": "0",
"to_pin": "OUT"
},
"AFFMUX:AX": {
"from_pin": "AX",
"to_pin": "OUT"
},
"AFFMUX:O5": {
"from_pin": "O5",
"to_pin": "OUT"
},
"SRUSEDMUX:IN": {
"from_pin": "IN",
"to_pin": "OUT"
},
"B6LUT:A3": {
"from_pin": "A3",
"to_pin": "O6"
},
"AOUTMUX:F7": {
"from_pin": "F7",
"to_pin": "OUT"
},
"C5LUT:A4": {
"from_pin": "A4",
"to_pin": "O5"
},
"BFFMUX:CARRY4_MUX": {
"from_pin": "CARRY4_MUX",
"to_pin": "OUT"
},
"AFFMUX:CARRY4_XOR": {
"from_pin": "CARRY4_XOR",
"to_pin": "OUT"
},
"A5LUT:A4": {
"from_pin": "A4",
"to_pin": "O5"
},
"C6LUT:A3": {
"from_pin": "A3",
"to_pin": "O6"
},
"DFFMUX:O6": {
"from_pin": "O6",
"to_pin": "OUT"
},
"DOUTMUX:CARRY4_XOR": {
"from_pin": "CARRY4_XOR",
"to_pin": "OUT"
},
"B5LUT:A5": {
"from_pin": "A5",
"to_pin": "O5"
},
"D6LUT:A3": {
"from_pin": "A3",
"to_pin": "O6"
},
"CCY0:O5": {
"from_pin": "O5",
"to_pin": "OUT"
},
"C5LUT:A1": {
"from_pin": "A1",
"to_pin": "O5"
},
"COUTMUX:O5": {
"from_pin": "O5",
"to_pin": "OUT"
},
"CFFMUX:XOR": {
"from_pin": "XOR",
"to_pin": "OUT"
},
"BFFMUX:BX": {
"from_pin": "BX",
"to_pin": "OUT"
},
"CFFMUX:F7": {
"from_pin": "F7",
"to_pin": "OUT"
},
"COUTMUX:C5Q": {
"from_pin": "C5Q",
"to_pin": "OUT"
},
"AFFMUX:F7": {
"from_pin": "F7",
"to_pin": "OUT"
},
"AOUTMUX:CY": {
"from_pin": "CY",
"to_pin": "OUT"
},
"D6LUT:A2": {
"from_pin": "A2",
"to_pin": "O6"
},
"B5LUT:A1": {
"from_pin": "A1",
"to_pin": "O5"
},
"B5LUT:A2": {
"from_pin": "A2",
"to_pin": "O5"
},
"AUSED:0": {
"from_pin": "0",
"to_pin": "OUT"
},
"C6LUT:A2": {
"from_pin": "A2",
"to_pin": "O6"
},
"PRECYINIT:AX": {
"from_pin": "AX",
"to_pin": "OUT"
},
"BCY0:O5": {
"from_pin": "O5",
"to_pin": "OUT"
},
"BFFMUX:CARRY4_XOR": {
"from_pin": "CARRY4_XOR",
"to_pin": "OUT"
},
"CEUSEDMUX:IN": {
"from_pin": "IN",
"to_pin": "OUT"
},
"CFFMUX:CX": {
"from_pin": "CX",
"to_pin": "OUT"
},
"C6LUT:A6": {
"from_pin": "A6",
"to_pin": "O6"
},
"D5LUT:A1": {
"from_pin": "A1",
"to_pin": "O5"
},
"D5FFMUX:IN_A": {
"from_pin": "IN_A",
"to_pin": "OUT"
},
"COUTUSED:0": {
"from_pin": "0",
"to_pin": "OUT"
},
"A6LUT:A1": {
"from_pin": "A1",
"to_pin": "O6"
},
"B6LUT:A5": {
"from_pin": "A5",
"to_pin": "O6"
},
"CFFMUX:O6": {
"from_pin": "O6",
"to_pin": "OUT"
},
"A6LUT:A5": {
"from_pin": "A5",
"to_pin": "O6"
},
"D6LUT:A6": {
"from_pin": "A6",
"to_pin": "O6"
},
"CLKINV:CLK": {
"from_pin": "CLK",
"to_pin": "OUT"
},
"COUTMUX:O6": {
"from_pin": "O6",
"to_pin": "OUT"
},
"A5FFMUX:IN_B": {
"from_pin": "IN_B",
"to_pin": "OUT"
},
"AOUTMUX:CARRY4_MUX": {
"from_pin": "CARRY4_MUX",
"to_pin": "OUT"
},
"DFFMUX:CY": {
"from_pin": "CY",
"to_pin": "OUT"
},
"COUTMUX:F7": {
"from_pin": "F7",
"to_pin": "OUT"
},
"DCY0:DX": {
"from_pin": "DX",
"to_pin": "OUT"
},
"BOUTMUX:CARRY4_MUX": {
"from_pin": "CARRY4_MUX",
"to_pin": "OUT"
},
"AFFMUX:XOR": {
"from_pin": "XOR",
"to_pin": "OUT"
},
"C6LUT:A5": {
"from_pin": "A5",
"to_pin": "O6"
},
"B5FFMUX:IN_A": {
"from_pin": "IN_A",
"to_pin": "OUT"
},
"CEUSEDMUX:1": {
"from_pin": "1",
"to_pin": "OUT"
},
"COUTMUX:CARRY4_XOR": {
"from_pin": "CARRY4_XOR",
"to_pin": "OUT"
},
"BOUTMUX:CY": {
"from_pin": "CY",
"to_pin": "OUT"
},
"CUSED:0": {
"from_pin": "0",
"to_pin": "OUT"
},
"B5LUT:A3": {
"from_pin": "A3",
"to_pin": "O5"
},
"COUTMUX:XOR": {
"from_pin": "XOR",
"to_pin": "OUT"
},
"C5LUT:A2": {
"from_pin": "A2",
"to_pin": "O5"
},
"COUTMUX:CY": {
"from_pin": "CY",
"to_pin": "OUT"
}
},
"site_pins": {
"C6": {
"direction": "IN"
},
"B": {
"direction": "OUT"
},
"AQ": {
"direction": "OUT"
},
"D1": {
"direction": "IN"
},
"A4": {
"direction": "IN"
},
"DX": {
"direction": "IN"
},
"BQ": {
"direction": "OUT"
},
"COUT": {
"direction": "OUT"
},
"B6": {
"direction": "IN"
},
"A": {
"direction": "OUT"
},
"CE": {
"direction": "IN"
},
"C": {
"direction": "OUT"
},
"BMUX": {
"direction": "OUT"
},
"A1": {
"direction": "IN"
},
"DMUX": {
"direction": "OUT"
},
"A5": {
"direction": "IN"
},
"CLK": {
"direction": "IN"
},
"AX": {
"direction": "IN"
},
"BX": {
"direction": "IN"
},
"A6": {
"direction": "IN"
},
"B3": {
"direction": "IN"
},
"A3": {
"direction": "IN"
},
"SR": {
"direction": "IN"
},
"B4": {
"direction": "IN"
},
"AMUX": {
"direction": "OUT"
},
"CQ": {
"direction": "OUT"
},
"C1": {
"direction": "IN"
},
"CX": {
"direction": "IN"
},
"A2": {
"direction": "IN"
},
"D": {
"direction": "OUT"
},
"D3": {
"direction": "IN"
},
"D6": {
"direction": "IN"
},
"D4": {
"direction": "IN"
},
"B2": {
"direction": "IN"
},
"D5": {
"direction": "IN"
},
"B5": {
"direction": "IN"
},
"C4": {
"direction": "IN"
},
"DQ": {
"direction": "OUT"
},
"C5": {
"direction": "IN"
},
"CMUX": {
"direction": "OUT"
},
"CIN": {
"direction": "IN"
},
"D2": {
"direction": "IN"
},
"C2": {
"direction": "IN"
},
"C3": {
"direction": "IN"
},
"B1": {
"direction": "IN"
}
}
}

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kintex7/site_type_SLICEM.json Normal file
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@ -0,0 +1,769 @@
{
"type": "SLICEM",
"site_pips": {
"A5FFMUX:IN_A": {
"from_pin": "IN_A",
"to_pin": "OUT"
},
"COUTMUX:C5Q": {
"from_pin": "C5Q",
"to_pin": "OUT"
},
"B6LUT:A4": {
"from_pin": "A4",
"to_pin": "O6"
},
"D5LUT:A3": {
"from_pin": "A3",
"to_pin": "O5"
},
"A6LUT:A4": {
"from_pin": "A4",
"to_pin": "O6"
},
"C5LUT:A5": {
"from_pin": "A5",
"to_pin": "O5"
},
"BOUTMUX:CARRY4_MUX": {
"from_pin": "CARRY4_MUX",
"to_pin": "OUT"
},
"D6LUT:A4": {
"from_pin": "A4",
"to_pin": "O6"
},
"A5LUT:A5": {
"from_pin": "A5",
"to_pin": "O5"
},
"A6LUT:A2": {
"from_pin": "A2",
"to_pin": "O6"
},
"AOUTMUX:A5Q": {
"from_pin": "A5Q",
"to_pin": "OUT"
},
"D6LUT:A5": {
"from_pin": "A5",
"to_pin": "O6"
},
"WA8USED:0": {
"from_pin": "0",
"to_pin": "OUT"
},
"CCY0:CX": {
"from_pin": "CX",
"to_pin": "OUT"
},
"AOUTMUX:O5": {
"from_pin": "O5",
"to_pin": "OUT"
},
"SRUSEDMUX:0": {
"from_pin": "0",
"to_pin": "OUT"
},
"DFFMUX:XOR": {
"from_pin": "XOR",
"to_pin": "OUT"
},
"A5LUT:A3": {
"from_pin": "A3",
"to_pin": "O5"
},
"BOUTMUX:B5Q": {
"from_pin": "B5Q",
"to_pin": "OUT"
},
"ADI1MUX:BMC31": {
"from_pin": "BMC31",
"to_pin": "OUT"
},
"BOUTMUX:F8": {
"from_pin": "F8",
"to_pin": "OUT"
},
"WEMUX:CE": {
"from_pin": "CE",
"to_pin": "OUT"
},
"AFFMUX:O5": {
"from_pin": "O5",
"to_pin": "OUT"
},
"BFFMUX:BX": {
"from_pin": "BX",
"to_pin": "OUT"
},
"AFFMUX:CARRY4_MUX": {
"from_pin": "CARRY4_MUX",
"to_pin": "OUT"
},
"DFFMUX:DX": {
"from_pin": "DX",
"to_pin": "OUT"
},
"BUSED:0": {
"from_pin": "0",
"to_pin": "OUT"
},
"DOUTMUX:CARRY4_MUX": {
"from_pin": "CARRY4_MUX",
"to_pin": "OUT"
},
"BDI1MUX:DI": {
"from_pin": "DI",
"to_pin": "OUT"
},
"BFFMUX:O5": {
"from_pin": "O5",
"to_pin": "OUT"
},
"BFFMUX:XOR": {
"from_pin": "XOR",
"to_pin": "OUT"
},
"D5LUT:A4": {
"from_pin": "A4",
"to_pin": "O5"
},
"BFFMUX:O6": {
"from_pin": "O6",
"to_pin": "OUT"
},
"COUTMUX:CARRY4_MUX": {
"from_pin": "CARRY4_MUX",
"to_pin": "OUT"
},
"D6LUT:A1": {
"from_pin": "A1",
"to_pin": "O6"
},
"DOUTMUX:CY": {
"from_pin": "CY",
"to_pin": "OUT"
},
"CLKINV:CLK_B": {
"from_pin": "CLK_B",
"to_pin": "OUT"
},
"B6LUT:A1": {
"from_pin": "A1",
"to_pin": "O6"
},
"BOUTMUX:O5": {
"from_pin": "O5",
"to_pin": "OUT"
},
"AOUTMUX:XOR": {
"from_pin": "XOR",
"to_pin": "OUT"
},
"B6LUT:A6": {
"from_pin": "A6",
"to_pin": "O6"
},
"C6LUT:A4": {
"from_pin": "A4",
"to_pin": "O6"
},
"C6LUT:A1": {
"from_pin": "A1",
"to_pin": "O6"
},
"BOUTMUX:XOR": {
"from_pin": "XOR",
"to_pin": "OUT"
},
"B5FFMUX:IN_B": {
"from_pin": "IN_B",
"to_pin": "OUT"
},
"CFFMUX:CY": {
"from_pin": "CY",
"to_pin": "OUT"
},
"DFFMUX:O5": {
"from_pin": "O5",
"to_pin": "OUT"
},
"DOUTMUX:O5": {
"from_pin": "O5",
"to_pin": "OUT"
},
"D5FFMUX:IN_B": {
"from_pin": "IN_B",
"to_pin": "OUT"
},
"AFFMUX:O6": {
"from_pin": "O6",
"to_pin": "OUT"
},
"ACY0:O5": {
"from_pin": "O5",
"to_pin": "OUT"
},
"DOUTMUX:O6": {
"from_pin": "O6",
"to_pin": "OUT"
},
"CFFMUX:CARRY4_MUX": {
"from_pin": "CARRY4_MUX",
"to_pin": "OUT"
},
"BOUTMUX:CARRY4_XOR": {
"from_pin": "CARRY4_XOR",
"to_pin": "OUT"
},
"DFFMUX:MC31": {
"from_pin": "MC31",
"to_pin": "OUT"
},
"D5LUT:A2": {
"from_pin": "A2",
"to_pin": "O5"
},
"DOUTMUX:XOR": {
"from_pin": "XOR",
"to_pin": "OUT"
},
"DFFMUX:CARRY4_XOR": {
"from_pin": "CARRY4_XOR",
"to_pin": "OUT"
},
"A6LUT:A6": {
"from_pin": "A6",
"to_pin": "O6"
},
"DOUTMUX:D5Q": {
"from_pin": "D5Q",
"to_pin": "OUT"
},
"PRECYINIT:CIN": {
"from_pin": "CIN",
"to_pin": "OUT"
},
"AOUTMUX:CARRY4_XOR": {
"from_pin": "CARRY4_XOR",
"to_pin": "OUT"
},
"DCY0:O5": {
"from_pin": "O5",
"to_pin": "OUT"
},
"ADI1MUX:BDI1": {
"from_pin": "BDI1",
"to_pin": "OUT"
},
"A5LUT:A2": {
"from_pin": "A2",
"to_pin": "O5"
},
"A5LUT:A1": {
"from_pin": "A1",
"to_pin": "O5"
},
"C5LUT:A3": {
"from_pin": "A3",
"to_pin": "O5"
},
"PRECYINIT:1": {
"from_pin": "1",
"to_pin": "OUT"
},
"B6LUT:A2": {
"from_pin": "A2",
"to_pin": "O6"
},
"A6LUT:A3": {
"from_pin": "A3",
"to_pin": "O6"
},
"BOUTMUX:O6": {
"from_pin": "O6",
"to_pin": "OUT"
},
"PRECYINIT:0": {
"from_pin": "0",
"to_pin": "OUT"
},
"BCY0:BX": {
"from_pin": "BX",
"to_pin": "OUT"
},
"C5FFMUX:IN_A": {
"from_pin": "IN_A",
"to_pin": "OUT"
},
"COUTUSED:CARRY4_0": {
"from_pin": "CARRY4_0",
"to_pin": "OUT"
},
"B5LUT:A4": {
"from_pin": "A4",
"to_pin": "O5"
},
"DCY0:DX": {
"from_pin": "DX",
"to_pin": "OUT"
},
"AFFMUX:CY": {
"from_pin": "CY",
"to_pin": "OUT"
},
"C5FFMUX:IN_B": {
"from_pin": "IN_B",
"to_pin": "OUT"
},
"BFFMUX:F8": {
"from_pin": "F8",
"to_pin": "OUT"
},
"BDI1MUX:BI": {
"from_pin": "BI",
"to_pin": "OUT"
},
"BFFMUX:CY": {
"from_pin": "CY",
"to_pin": "OUT"
},
"ADI1MUX:AI": {
"from_pin": "AI",
"to_pin": "OUT"
},
"CFFMUX:O5": {
"from_pin": "O5",
"to_pin": "OUT"
},
"DUSED:0": {
"from_pin": "0",
"to_pin": "OUT"
},
"AOUTMUX:O6": {
"from_pin": "O6",
"to_pin": "OUT"
},
"WA7USED:0": {
"from_pin": "0",
"to_pin": "OUT"
},
"SRUSEDMUX:IN": {
"from_pin": "IN",
"to_pin": "OUT"
},
"B6LUT:A3": {
"from_pin": "A3",
"to_pin": "O6"
},
"AOUTMUX:F7": {
"from_pin": "F7",
"to_pin": "OUT"
},
"BDI1MUX:CMC31": {
"from_pin": "CMC31",
"to_pin": "OUT"
},
"C5LUT:A4": {
"from_pin": "A4",
"to_pin": "O5"
},
"WEMUX:WE": {
"from_pin": "WE",
"to_pin": "OUT"
},
"BFFMUX:CARRY4_MUX": {
"from_pin": "CARRY4_MUX",
"to_pin": "OUT"
},
"AFFMUX:CARRY4_XOR": {
"from_pin": "CARRY4_XOR",
"to_pin": "OUT"
},
"A5LUT:A4": {
"from_pin": "A4",
"to_pin": "O5"
},
"C6LUT:A3": {
"from_pin": "A3",
"to_pin": "O6"
},
"A6LUT:A1": {
"from_pin": "A1",
"to_pin": "O6"
},
"DOUTMUX:CARRY4_XOR": {
"from_pin": "CARRY4_XOR",
"to_pin": "OUT"
},
"B5LUT:A5": {
"from_pin": "A5",
"to_pin": "O5"
},
"D6LUT:A3": {
"from_pin": "A3",
"to_pin": "O6"
},
"CCY0:O5": {
"from_pin": "O5",
"to_pin": "OUT"
},
"C5LUT:A1": {
"from_pin": "A1",
"to_pin": "O5"
},
"COUTMUX:O5": {
"from_pin": "O5",
"to_pin": "OUT"
},
"CFFMUX:XOR": {
"from_pin": "XOR",
"to_pin": "OUT"
},
"D6LUT:A6": {
"from_pin": "A6",
"to_pin": "O6"
},
"DOUTMUX:MC31": {
"from_pin": "MC31",
"to_pin": "OUT"
},
"CFFMUX:F7": {
"from_pin": "F7",
"to_pin": "OUT"
},
"D5LUT:A5": {
"from_pin": "A5",
"to_pin": "O5"
},
"AFFMUX:F7": {
"from_pin": "F7",
"to_pin": "OUT"
},
"AOUTMUX:CY": {
"from_pin": "CY",
"to_pin": "OUT"
},
"D6LUT:A2": {
"from_pin": "A2",
"to_pin": "O6"
},
"BOUTMUX:CY": {
"from_pin": "CY",
"to_pin": "OUT"
},
"B5LUT:A2": {
"from_pin": "A2",
"to_pin": "O5"
},
"AUSED:0": {
"from_pin": "0",
"to_pin": "OUT"
},
"C6LUT:A2": {
"from_pin": "A2",
"to_pin": "O6"
},
"PRECYINIT:AX": {
"from_pin": "AX",
"to_pin": "OUT"
},
"BCY0:O5": {
"from_pin": "O5",
"to_pin": "OUT"
},
"BFFMUX:CARRY4_XOR": {
"from_pin": "CARRY4_XOR",
"to_pin": "OUT"
},
"CEUSEDMUX:IN": {
"from_pin": "IN",
"to_pin": "OUT"
},
"CFFMUX:CX": {
"from_pin": "CX",
"to_pin": "OUT"
},
"C6LUT:A6": {
"from_pin": "A6",
"to_pin": "O6"
},
"D5LUT:A1": {
"from_pin": "A1",
"to_pin": "O5"
},
"D5FFMUX:IN_A": {
"from_pin": "IN_A",
"to_pin": "OUT"
},
"ACY0:AX": {
"from_pin": "AX",
"to_pin": "OUT"
},
"COUTUSED:0": {
"from_pin": "0",
"to_pin": "OUT"
},
"B6LUT:A5": {
"from_pin": "A5",
"to_pin": "O6"
},
"CFFMUX:O6": {
"from_pin": "O6",
"to_pin": "OUT"
},
"A6LUT:A5": {
"from_pin": "A5",
"to_pin": "O6"
},
"CDI1MUX:CI": {
"from_pin": "CI",
"to_pin": "OUT"
},
"CLKINV:CLK": {
"from_pin": "CLK",
"to_pin": "OUT"
},
"CDI1MUX:DI": {
"from_pin": "DI",
"to_pin": "OUT"
},
"COUTMUX:O6": {
"from_pin": "O6",
"to_pin": "OUT"
},
"A5FFMUX:IN_B": {
"from_pin": "IN_B",
"to_pin": "OUT"
},
"AOUTMUX:CARRY4_MUX": {
"from_pin": "CARRY4_MUX",
"to_pin": "OUT"
},
"CDI1MUX:DMC31": {
"from_pin": "DMC31",
"to_pin": "OUT"
},
"DFFMUX:CY": {
"from_pin": "CY",
"to_pin": "OUT"
},
"COUTMUX:F7": {
"from_pin": "F7",
"to_pin": "OUT"
},
"CFFMUX:CARRY4_XOR": {
"from_pin": "CARRY4_XOR",
"to_pin": "OUT"
},
"AFFMUX:AX": {
"from_pin": "AX",
"to_pin": "OUT"
},
"AFFMUX:XOR": {
"from_pin": "XOR",
"to_pin": "OUT"
},
"C6LUT:A5": {
"from_pin": "A5",
"to_pin": "O6"
},
"B5FFMUX:IN_A": {
"from_pin": "IN_A",
"to_pin": "OUT"
},
"CEUSEDMUX:1": {
"from_pin": "1",
"to_pin": "OUT"
},
"COUTMUX:CARRY4_XOR": {
"from_pin": "CARRY4_XOR",
"to_pin": "OUT"
},
"B5LUT:A1": {
"from_pin": "A1",
"to_pin": "O5"
},
"DFFMUX:O6": {
"from_pin": "O6",
"to_pin": "OUT"
},
"CUSED:0": {
"from_pin": "0",
"to_pin": "OUT"
},
"B5LUT:A3": {
"from_pin": "A3",
"to_pin": "O5"
},
"DFFMUX:CARRY4_MUX": {
"from_pin": "CARRY4_MUX",
"to_pin": "OUT"
},
"COUTMUX:XOR": {
"from_pin": "XOR",
"to_pin": "OUT"
},
"C5LUT:A2": {
"from_pin": "A2",
"to_pin": "O5"
},
"COUTMUX:CY": {
"from_pin": "CY",
"to_pin": "OUT"
}
},
"site_pins": {
"C6": {
"direction": "IN"
},
"BI": {
"direction": "IN"
},
"B6": {
"direction": "IN"
},
"D1": {
"direction": "IN"
},
"B5": {
"direction": "IN"
},
"A4": {
"direction": "IN"
},
"AI": {
"direction": "IN"
},
"DX": {
"direction": "IN"
},
"BQ": {
"direction": "OUT"
},
"CI": {
"direction": "IN"
},
"COUT": {
"direction": "OUT"
},
"A": {
"direction": "OUT"
},
"CE": {
"direction": "IN"
},
"C": {
"direction": "OUT"
},
"BMUX": {
"direction": "OUT"
},
"A1": {
"direction": "IN"
},
"DMUX": {
"direction": "OUT"
},
"A5": {
"direction": "IN"
},
"CLK": {
"direction": "IN"
},
"AX": {
"direction": "IN"
},
"BX": {
"direction": "IN"
},
"A6": {
"direction": "IN"
},
"B3": {
"direction": "IN"
},
"A3": {
"direction": "IN"
},
"CIN": {
"direction": "IN"
},
"B4": {
"direction": "IN"
},
"AMUX": {
"direction": "OUT"
},
"D6": {
"direction": "IN"
},
"CQ": {
"direction": "OUT"
},
"C1": {
"direction": "IN"
},
"CX": {
"direction": "IN"
},
"A2": {
"direction": "IN"
},
"D": {
"direction": "OUT"
},
"D3": {
"direction": "IN"
},
"B": {
"direction": "OUT"
},
"D4": {
"direction": "IN"
},
"AQ": {
"direction": "OUT"
},
"B2": {
"direction": "IN"
},
"D5": {
"direction": "IN"
},
"DI": {
"direction": "IN"
},
"C4": {
"direction": "IN"
},
"DQ": {
"direction": "OUT"
},
"C5": {
"direction": "IN"
},
"CMUX": {
"direction": "OUT"
},
"WE": {
"direction": "IN"
},
"SR": {
"direction": "IN"
},
"D2": {
"direction": "IN"
},
"C2": {
"direction": "IN"
},
"C3": {
"direction": "IN"
},
"B1": {
"direction": "IN"
}
}
}

45
kintex7/site_type_STARTUP.json Normal file
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@ -0,0 +1,45 @@
{
"type": "STARTUP",
"site_pips": {},
"site_pins": {
"USRDONETS": {
"direction": "IN"
},
"PREQ": {
"direction": "OUT"
},
"CFGMCLK": {
"direction": "OUT"
},
"GSR": {
"direction": "IN"
},
"GTS": {
"direction": "IN"
},
"PACK": {
"direction": "IN"
},
"CFGCLK": {
"direction": "OUT"
},
"CLK": {
"direction": "IN"
},
"USRDONEO": {
"direction": "IN"
},
"EOS": {
"direction": "OUT"
},
"USRCCLKO": {
"direction": "IN"
},
"KEYCLEARB": {
"direction": "IN"
},
"USRCCLKTS": {
"direction": "IN"
}
}
}

12
kintex7/site_type_TIEOFF.json Normal file
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@ -0,0 +1,12 @@
{
"type": "TIEOFF",
"site_pips": {},
"site_pins": {
"HARD1": {
"direction": "OUT"
},
"HARD0": {
"direction": "OUT"
}
}
}

108
kintex7/site_type_USR_ACCESS.json Normal file
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@ -0,0 +1,108 @@
{
"type": "USR_ACCESS",
"site_pips": {},
"site_pins": {
"DATA3": {
"direction": "OUT"
},
"DATA1": {
"direction": "OUT"
},
"CFGCLK": {
"direction": "OUT"
},
"DATA14": {
"direction": "OUT"
},
"DATA26": {
"direction": "OUT"
},
"DATA11": {
"direction": "OUT"
},
"DATA4": {
"direction": "OUT"
},
"DATA30": {
"direction": "OUT"
},
"DATA13": {
"direction": "OUT"
},
"DATA15": {
"direction": "OUT"
},
"DATA5": {
"direction": "OUT"
},
"DATA27": {
"direction": "OUT"
},
"DATAVALID": {
"direction": "OUT"
},
"DATA24": {
"direction": "OUT"
},
"DATA12": {
"direction": "OUT"
},
"DATA29": {
"direction": "OUT"
},
"DATA10": {
"direction": "OUT"
},
"DATA9": {
"direction": "OUT"
},
"DATA7": {
"direction": "OUT"
},
"DATA8": {
"direction": "OUT"
},
"DATA17": {
"direction": "OUT"
},
"DATA0": {
"direction": "OUT"
},
"DATA18": {
"direction": "OUT"
},
"DATA19": {
"direction": "OUT"
},
"DATA6": {
"direction": "OUT"
},
"DATA22": {
"direction": "OUT"
},
"DATA20": {
"direction": "OUT"
},
"DATA16": {
"direction": "OUT"
},
"DATA21": {
"direction": "OUT"
},
"DATA25": {
"direction": "OUT"
},
"DATA2": {
"direction": "OUT"
},
"DATA28": {
"direction": "OUT"
},
"DATA23": {
"direction": "OUT"
},
"DATA31": {
"direction": "OUT"
}
}
}

683
kintex7/site_type_XADC.json Normal file
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@ -0,0 +1,683 @@
{
"type": "XADC",
"site_pips": {
"DCLKINV:DCLK_B": {
"from_pin": "DCLK_B",
"to_pin": "OUT"
},
"DCLKINV:DCLK": {
"from_pin": "DCLK",
"to_pin": "OUT"
},
"CONVSTCLKINV:CONVSTCLK_B": {
"from_pin": "CONVSTCLK_B",
"to_pin": "OUT"
},
"CONVSTCLKINV:CONVSTCLK": {
"from_pin": "CONVSTCLK",
"to_pin": "OUT"
}
},
"site_pins": {
"TESTDB5": {
"direction": "OUT"
},
"DO12": {
"direction": "OUT"
},
"DEN": {
"direction": "IN"
},
"VAUXN11": {
"direction": "IN"
},
"VN": {
"direction": "IN"
},
"VAUXP0": {
"direction": "IN"
},
"TESTADCOUT3": {
"direction": "OUT"
},
"DI0": {
"direction": "IN"
},
"TESTADCIN19": {
"direction": "IN"
},
"TESTSCANCLK3": {
"direction": "IN"
},
"JTAGMODIFIED": {
"direction": "OUT"
},
"VAUXN1": {
"direction": "IN"
},
"TESTSE1": {
"direction": "IN"
},
"TESTSCANMODE0": {
"direction": "IN"
},
"MUXADDR1": {
"direction": "OUT"
},
"DO7": {
"direction": "OUT"
},
"TESTADCIN3": {
"direction": "IN"
},
"VAUXN8": {
"direction": "IN"
},
"TESTADCOUT17": {
"direction": "OUT"
},
"TESTSCANMODE4": {
"direction": "IN"
},
"TESTADCCLK0": {
"direction": "IN"
},
"TESTDB14": {
"direction": "OUT"
},
"VAUXP6": {
"direction": "IN"
},
"OT": {
"direction": "OUT"
},
"VAUXN14": {
"direction": "IN"
},
"TESTADCIN217": {
"direction": "IN"
},
"TESTADCOUT16": {
"direction": "OUT"
},
"TESTSE4": {
"direction": "IN"
},
"TESTADCOUT6": {
"direction": "OUT"
},
"VAUXN0": {
"direction": "IN"
},
"TESTADCIN18": {
"direction": "IN"
},
"TESTADCOUT9": {
"direction": "OUT"
},
"VP": {
"direction": "IN"
},
"TESTDB9": {
"direction": "OUT"
},
"DO3": {
"direction": "OUT"
},
"TESTADCIN4": {
"direction": "IN"
},
"VAUXN7": {
"direction": "IN"
},
"DI8": {
"direction": "IN"
},
"VAUXP2": {
"direction": "IN"
},
"DO4": {
"direction": "OUT"
},
"VAUXP1": {
"direction": "IN"
},
"TESTDB0": {
"direction": "OUT"
},
"TESTSEL": {
"direction": "IN"
},
"TESTSO2": {
"direction": "OUT"
},
"TESTADCIN29": {
"direction": "IN"
},
"TESTADCOUT13": {
"direction": "OUT"
},
"TESTADCIN12": {
"direction": "IN"
},
"TESTDB2": {
"direction": "OUT"
},
"CHANNEL1": {
"direction": "OUT"
},
"DI14": {
"direction": "IN"
},
"TESTENJTAG": {
"direction": "IN"
},
"TESTSI0": {
"direction": "IN"
},
"DADDR1": {
"direction": "IN"
},
"TESTADCOUT12": {
"direction": "OUT"
},
"TESTADCIN5": {
"direction": "IN"
},
"TESTDB7": {
"direction": "OUT"
},
"TESTADCIN20": {
"direction": "IN"
},
"TESTDB3": {
"direction": "OUT"
},
"ALM0": {
"direction": "OUT"
},
"TESTTDO": {
"direction": "OUT"
},
"TESTSCANCLK1": {
"direction": "IN"
},
"DO5": {
"direction": "OUT"
},
"DWE": {
"direction": "IN"
},
"DO0": {
"direction": "OUT"
},
"DO13": {
"direction": "OUT"
},
"TESTADCOUT0": {
"direction": "OUT"
},
"ALM6": {
"direction": "OUT"
},
"TESTSO0": {
"direction": "OUT"
},
"EOS": {
"direction": "OUT"
},
"TESTADCIN2": {
"direction": "IN"
},
"DI5": {
"direction": "IN"
},
"TESTSCANMODE1": {
"direction": "IN"
},
"TESTADCOUT14": {
"direction": "OUT"
},
"TESTSCANCLK2": {
"direction": "IN"
},
"VAUXN12": {
"direction": "IN"
},
"DO14": {
"direction": "OUT"
},
"TESTADCOUT5": {
"direction": "OUT"
},
"DI6": {
"direction": "IN"
},
"TESTADCIN213": {
"direction": "IN"
},
"ALM7": {
"direction": "OUT"
},
"DO1": {
"direction": "OUT"
},
"VAUXN9": {
"direction": "IN"
},
"VAUXP8": {
"direction": "IN"
},
"JTAGLOCKED": {
"direction": "OUT"
},
"VAUXN2": {
"direction": "IN"
},
"CHANNEL2": {
"direction": "OUT"
},
"TESTSO3": {
"direction": "OUT"
},
"TESTSI4": {
"direction": "IN"
},
"DO10": {
"direction": "OUT"
},
"DI3": {
"direction": "IN"
},
"VAUXP12": {
"direction": "IN"
},
"TESTADCIN212": {
"direction": "IN"
},
"TESTADCOUT15": {
"direction": "OUT"
},
"VAUXN3": {
"direction": "IN"
},
"TESTADCIN15": {
"direction": "IN"
},
"DO9": {
"direction": "OUT"
},
"TESTADCIN216": {
"direction": "IN"
},
"DO6": {
"direction": "OUT"
},
"TESTADCOUT4": {
"direction": "OUT"
},
"TESTADCIN27": {
"direction": "IN"
},
"DI15": {
"direction": "IN"
},
"TESTADCOUT7": {
"direction": "OUT"
},
"MUXADDR4": {
"direction": "OUT"
},
"TESTSHIFT": {
"direction": "IN"
},
"DI13": {
"direction": "IN"
},
"ALM3": {
"direction": "OUT"
},
"TESTADCIN23": {
"direction": "IN"
},
"TESTADCOUT8": {
"direction": "OUT"
},
"TESTADCIN10": {
"direction": "IN"
},
"TESTADCIN219": {
"direction": "IN"
},
"TESTADCIN210": {
"direction": "IN"
},
"TESTSCANCLK0": {
"direction": "IN"
},
"TESTSE3": {
"direction": "IN"
},
"TESTSE2": {
"direction": "IN"
},
"TESTSCANMODE2": {
"direction": "IN"
},
"TESTDB6": {
"direction": "OUT"
},
"TESTADCIN16": {
"direction": "IN"
},
"TESTADCIN8": {
"direction": "IN"
},
"VAUXN15": {
"direction": "IN"
},
"TESTDB12": {
"direction": "OUT"
},
"DO2": {
"direction": "OUT"
},
"EOC": {
"direction": "OUT"
},
"VAUXP15": {
"direction": "IN"
},
"TESTADCIN9": {
"direction": "IN"
},
"VAUXP7": {
"direction": "IN"
},
"TESTADCIN11": {
"direction": "IN"
},
"DI11": {
"direction": "IN"
},
"VAUXN4": {
"direction": "IN"
},
"TESTTDI": {
"direction": "IN"
},
"DI2": {
"direction": "IN"
},
"TESTRST": {
"direction": "IN"
},
"VAUXP4": {
"direction": "IN"
},
"CONVST": {
"direction": "IN"
},
"DRDY": {
"direction": "OUT"
},
"VAUXP3": {
"direction": "IN"
},
"ALM2": {
"direction": "OUT"
},
"VAUXP10": {
"direction": "IN"
},
"TESTDB13": {
"direction": "OUT"
},
"MUXADDR3": {
"direction": "OUT"
},
"TESTSI1": {
"direction": "IN"
},
"TESTADCIN6": {
"direction": "IN"
},
"DADDR3": {
"direction": "IN"
},
"TESTDB8": {
"direction": "OUT"
},
"BUSY": {
"direction": "OUT"
},
"MUXADDR2": {
"direction": "OUT"
},
"TESTADCIN17": {
"direction": "IN"
},
"ALM5": {
"direction": "OUT"
},
"TESTSCANCLK4": {
"direction": "IN"
},
"VAUXN13": {
"direction": "IN"
},
"TESTDB1": {
"direction": "OUT"
},
"DADDR4": {
"direction": "IN"
},
"TESTADCOUT19": {
"direction": "OUT"
},
"TESTADCIN1": {
"direction": "IN"
},
"TESTADCOUT2": {
"direction": "OUT"
},
"TESTADCOUT1": {
"direction": "OUT"
},
"TESTSE0": {
"direction": "IN"
},
"DADDR0": {
"direction": "IN"
},
"TESTADCIN28": {
"direction": "IN"
},
"TESTDRCK": {
"direction": "IN"
},
"TESTUPDATE": {
"direction": "IN"
},
"CONVSTCLK": {
"direction": "IN"
},
"TESTADCIN14": {
"direction": "IN"
},
"VAUXP13": {
"direction": "IN"
},
"VAUXN10": {
"direction": "IN"
},
"TESTSI3": {
"direction": "IN"
},
"DO11": {
"direction": "OUT"
},
"DI9": {
"direction": "IN"
},
"DADDR5": {
"direction": "IN"
},
"DI10": {
"direction": "IN"
},
"VAUXN6": {
"direction": "IN"
},
"TESTADCOUT18": {
"direction": "OUT"
},
"VAUXN5": {
"direction": "IN"
},
"VAUXP11": {
"direction": "IN"
},
"TESTSCANRESET": {
"direction": "IN"
},
"ALM1": {
"direction": "OUT"
},
"VAUXP9": {
"direction": "IN"
},
"DO15": {
"direction": "OUT"
},
"DI1": {
"direction": "IN"
},
"TESTADCIN218": {
"direction": "IN"
},
"TESTADCCLK2": {
"direction": "IN"
},
"VAUXP5": {
"direction": "IN"
},
"TESTSO1": {
"direction": "OUT"
},
"ALM4": {
"direction": "OUT"
},
"CHANNEL0": {
"direction": "OUT"
},
"TESTADCOUT10": {
"direction": "OUT"
},
"TESTADCIN22": {
"direction": "IN"
},
"CHANNEL4": {
"direction": "OUT"
},
"DI7": {
"direction": "IN"
},
"TESTADCOUT11": {
"direction": "OUT"
},
"TESTSCANMODE3": {
"direction": "IN"
},
"DI4": {
"direction": "IN"
},
"MUXADDR0": {
"direction": "OUT"
},
"TESTADCIN215": {
"direction": "IN"
},
"DCLK": {
"direction": "IN"
},
"DADDR2": {
"direction": "IN"
},
"TESTDB10": {
"direction": "OUT"
},
"TESTADCIN26": {
"direction": "IN"
},
"TESTADCIN214": {
"direction": "IN"
},
"TESTADCIN0": {
"direction": "IN"
},
"TESTDB4": {
"direction": "OUT"
},
"TESTADCIN24": {
"direction": "IN"
},
"DI12": {
"direction": "IN"
},
"RESET": {
"direction": "IN"
},
"VAUXP14": {
"direction": "IN"
},
"TESTCAPTURE": {
"direction": "IN"
},
"DADDR6": {
"direction": "IN"
},
"TESTADCCLK3": {
"direction": "IN"
},
"TESTADCCLK1": {
"direction": "IN"
},
"JTAGBUSY": {
"direction": "OUT"
},
"TESTSO4": {
"direction": "OUT"
},
"TESTDB15": {
"direction": "OUT"
},
"DO8": {
"direction": "OUT"
},
"TESTADCIN7": {
"direction": "IN"
},
"TESTADCIN25": {
"direction": "IN"
},
"TESTADCIN13": {
"direction": "IN"
},
"TESTDB11": {
"direction": "OUT"
},
"TESTSI2": {
"direction": "IN"
},
"TESTADCIN21": {
"direction": "IN"
},
"TESTADCIN211": {
"direction": "IN"
},
"CHANNEL3": {
"direction": "OUT"
}
}
}

476
kintex7/tile_type_BRAM_INT_INTERFACE_L.json Normal file
View File

@ -0,0 +1,476 @@
{
"tile_type": "BRAM_INT_INTERFACE_L",
"sites": [],
"wires": [
"INT_INTERFACE_LOGIC_OUTS_L15",
"INT_INTERFACE_BRAM_UTURN_IMUX47",
"INT_INTERFACE_EE4C1",
"INT_INTERFACE_BRAM_UTURN_IMUX7",
"INT_INTERFACE_BRAM_IMUX14",
"INT_INTERFACE_BRAM_UTURN_IMUX43",
"INT_INTERFACE_BRAM_IMUX19",
"INT_INTERFACE_SW4END0",
"INT_INTERFACE_BRAM_UTURN_IMUX30",
"INT_INTERFACE_BRAM_UTURN_IMUX19",
"INT_INTERFACE_SW4END3",
"INT_INTERFACE_EE4B1",
"INT_INTERFACE_WW4C2",
"INT_INTERFACE_LH7",
"INT_INTERFACE_BRAM_IMUX37",
"INT_INTERFACE_EE4C3",
"INT_INTERFACE_BRAM_UTURN_IMUX28",
"INT_INTERFACE_BRAM_UTURN_IMUX36",
"INT_INTERFACE_LOGIC_OUTS_L_B7",
"INT_INTERFACE_BRAM_UTURN_IMUX16",
"INT_INTERFACE_BRAM_UTURN_IMUX5",
"INT_INTERFACE_LOGIC_OUTS_L11",
"INT_INTERFACE_WL1END2",
"INT_INTERFACE_BYP2",
"INT_INTERFACE_LOGIC_OUTS_L_B2",
"INT_INTERFACE_BLOCK_OUTS_L_B3",
"INT_INTERFACE_BRAM_IMUX13",
"INT_INTERFACE_EE2A2",
"INT_INTERFACE_NW2A1",
"INT_INTERFACE_NW4A0",
"INT_INTERFACE_LOGIC_OUTS_L_B0",
"INT_INTERFACE_BRAM_IMUX44",
"INT_INTERFACE_WW2END2",
"INT_INTERFACE_NW4A1",
"INT_INTERFACE_BRAM_IMUX34",
"INT_INTERFACE_LOGIC_OUTS_L23",
"INT_INTERFACE_BRAM_IMUX17",
"INT_INTERFACE_WW2A1",
"INT_INTERFACE_EE4B3",
"INT_INTERFACE_LOGIC_OUTS_L_B12",
"INT_INTERFACE_BRAM_UTURN_IMUX39",
"INT_INTERFACE_LOGIC_OUTS_L7",
"INT_INTERFACE_WW2A3",
"INT_INTERFACE_SE2A1",
"INT_INTERFACE_LOGIC_OUTS_L3",
"INT_INTERFACE_BRAM_IMUX39",
"INT_INTERFACE_NW4A3",
"INT_INTERFACE_BRAM_IMUX4",
"INT_INTERFACE_LH11",
"INT_INTERFACE_EE4A2",
"INT_INTERFACE_BRAM_UTURN_IMUX6",
"INT_INTERFACE_SE2A2",
"INT_INTERFACE_BRAM_IMUX16",
"INT_INTERFACE_BRAM_IMUX27",
"INT_INTERFACE_WW4C1",
"INT_INTERFACE_BRAM_UTURN_IMUX10",
"INT_INTERFACE_SW2A3",
"INT_INTERFACE_BRAM_UTURN_IMUX35",
"INT_INTERFACE_SE4BEG2",
"INT_INTERFACE_BRAM_UTURN_IMUX44",
"INT_INTERFACE_EL1BEG2",
"INT_INTERFACE_EL1BEG3",
"INT_INTERFACE_BRAM_IMUX1",
"L_INT_INTER_DQS_IOTOPHASER",
"INT_INTERFACE_LH5",
"INT_INTERFACE_BRAM_IMUX12",
"INT_INTERFACE_FAN6",
"INT_INTERFACE_BRAM_IMUX43",
"INT_INTERFACE_PHASER_TO_IO_OCLK",
"INT_INTERFACE_EE4A1",
"INT_INTERFACE_WW4B3",
"INT_INTERFACE_SW4END1",
"INT_INTERFACE_LOGIC_OUTS_L_B9",
"INT_INTERFACE_LOGIC_OUTS_L_B3",
"INT_INTERFACE_SE4BEG3",
"INT_INTERFACE_BRAM_UTURN_IMUX8",
"INT_INTERFACE_BRAM_IMUX29",
"INT_INTERFACE_BRAM_UTURN_IMUX31",
"INT_INTERFACE_WW4END1",
"INT_INTERFACE_BRAM_UTURN_IMUX9",
"INT_INTERFACE_BRAM_UTURN_IMUX27",
"INT_INTERFACE_SE4BEG0",
"INT_INTERFACE_WL1END3",
"INT_INTERFACE_BRAM_UTURN_IMUX25",
"INT_INTERFACE_LOGIC_OUTS_L13",
"INT_INTERFACE_SW2A2",
"INT_INTERFACE_NE2A2",
"INT_INTERFACE_BYP6",
"INT_INTERFACE_WL1END1",
"INT_INTERFACE_BRAM_UTURN_IMUX21",
"INT_INTERFACE_BRAM_UTURN_IMUX2",
"INT_INTERFACE_BRAM_IMUX15",
"INT_INTERFACE_BRAM_UTURN_IMUX11",
"INT_INTERFACE_BRAM_UTURN_IMUX24",
"INT_INTERFACE_WW4A2",
"INT_INTERFACE_LOGIC_OUTS_L_B23",
"INT_INTERFACE_BRAM_IMUX11",
"INT_INTERFACE_NW4END1",
"INT_INTERFACE_LH10",
"INT_INTERFACE_LOGIC_OUTS_L22",
"INT_INTERFACE_BRAM_IMUX42",
"INT_INTERFACE_LOGIC_OUTS_L_B21",
"INT_INTERFACE_NW4END0",
"INT_INTERFACE_BRAM_IMUX7",
"INT_INTERFACE_LOGIC_OUTS_L4",
"INT_INTERFACE_BRAM_IMUX0",
"INT_INTERFACE_BRAM_UTURN_IMUX45",
"INT_INTERFACE_NE4C3",
"INT_INTERFACE_EE4C2",
"INT_INTERFACE_BRAM_IMUX46",
"INT_INTERFACE_BRAM_IMUX28",
"INT_INTERFACE_EL1BEG1",
"INT_INTERFACE_BRAM_IMUX9",
"INT_INTERFACE_PHASER_TO_IO_ICLKDIV",
"INT_INTERFACE_BRAM_UTURN_IMUX12",
"INT_INTERFACE_BRAM_IMUX21",
"INT_INTERFACE_FAN7",
"INT_INTERFACE_LH2",
"INT_INTERFACE_BRAM_IMUX31",
"INT_INTERFACE_BLOCK_OUTS_L_B0",
"INT_INTERFACE_SW4A0",
"INT_INTERFACE_CTRL1",
"INT_INTERFACE_BRAM_IMUX33",
"INT_INTERFACE_BRAM_UTURN_IMUX29",
"INT_INTERFACE_EE2A1",
"INT_INTERFACE_SW4A2",
"INT_INTERFACE_LOGIC_OUTS_L_B18",
"INT_INTERFACE_WW2A2",
"INT_INTERFACE_BRAM_IMUX22",
"INT_INTERFACE_EE4A3",
"INT_INTERFACE_LH1",
"INT_INTERFACE_LOGIC_OUTS_L6",
"INT_INTERFACE_BRAM_UTURN_IMUX41",
"INT_INTERFACE_WW4A3",
"INT_INTERFACE_ER1BEG0",
"INT_INTERFACE_LH9",
"INT_INTERFACE_NW4END2",
"INT_INTERFACE_LH8",
"INT_INTERFACE_BRAM_UTURN_IMUX17",
"INT_INTERFACE_LH4",
"INT_INTERFACE_BRAM_UTURN_IMUX33",
"INT_INTERFACE_LOGIC_OUTS_L19",
"INT_INTERFACE_FAN3",
"INT_INTERFACE_BRAM_IMUX3",
"INT_INTERFACE_NE4C1",
"INT_INTERFACE_NE4BEG1",
"INT_INTERFACE_BRAM_UTURN_IMUX18",
"INT_INTERFACE_FAN4",
"INT_INTERFACE_MONITOR_N",
"INT_INTERFACE_ER1BEG2",
"INT_INTERFACE_WR1END3",
"INT_INTERFACE_BRAM_IMUX32",
"INT_INTERFACE_BYP3",
"INT_INTERFACE_ER1BEG1",
"INT_INTERFACE_LOGIC_OUTS_L12",
"INT_INTERFACE_BRAM_IMUX24",
"INT_INTERFACE_BRAM_UTURN_IMUX23",
"INT_INTERFACE_LOGIC_OUTS_L_B19",
"INT_INTERFACE_EE4B0",
"INT_INTERFACE_NW4A2",
"INT_INTERFACE_BRAM_IMUX8",
"INT_INTERFACE_BLOCK_OUTS_L_B1",
"INT_INTERFACE_WL1END0",
"INT_INTERFACE_SW4END2",
"INT_INTERFACE_LH3",
"INT_INTERFACE_SE4C0",
"INT_INTERFACE_LOGIC_OUTS_L18",
"INT_INTERFACE_BYP4",
"INT_INTERFACE_SW4A3",
"INT_INTERFACE_SW4A1",
"INT_INTERFACE_EE4B2",
"INT_INTERFACE_LOGIC_OUTS_L_B14",
"INT_INTERFACE_LOGIC_OUTS_L1",
"INT_INTERFACE_BRAM_UTURN_IMUX1",
"INT_INTERFACE_LOGIC_OUTS_L2",
"INT_INTERFACE_CTRL0",
"INT_INTERFACE_BRAM_UTURN_IMUX3",
"INT_INTERFACE_BRAM_IMUX30",
"INT_INTERFACE_WW4B2",
"INT_INTERFACE_BRAM_IMUX6",
"INT_INTERFACE_LOGIC_OUTS_L_B20",
"INT_INTERFACE_NE4C2",
"INT_INTERFACE_SW2A0",
"INT_INTERFACE_LOGIC_OUTS_L_B5",
"INT_INTERFACE_LOGIC_OUTS_L_B1",
"INT_INTERFACE_BRAM_UTURN_IMUX13",
"INT_INTERFACE_WW4A0",
"INT_INTERFACE_FAN5",
"INT_INTERFACE_LOGIC_OUTS_L8",
"INT_INTERFACE_CLK1",
"INT_INTERFACE_LOGIC_OUTS_L_B4",
"INT_INTERFACE_SE4C3",
"INT_INTERFACE_LOGIC_OUTS_L21",
"INT_INTERFACE_SE4C1",
"INT_INTERFACE_BRAM_UTURN_IMUX20",
"INT_INTERFACE_BYP5",
"INT_INTERFACE_BRAM_UTURN_IMUX34",
"INT_INTERFACE_SE2A0",
"INT_INTERFACE_EE4BEG2",
"INT_INTERFACE_SE4BEG1",
"INT_INTERFACE_BRAM_IMUX47",
"INT_INTERFACE_LOGIC_OUTS_L14",
"INT_INTERFACE_BRAM_UTURN_IMUX14",
"INT_INTERFACE_LOGIC_OUTS_L10",
"INT_INTERFACE_NE4BEG0",
"INT_INTERFACE_WW2A0",
"INT_INTERFACE_BRAM_IMUX35",
"INT_INTERFACE_ER1BEG3",
"INT_INTERFACE_BRAM_UTURN_IMUX37",
"INT_INTERFACE_WW2END0",
"INT_INTERFACE_LOGIC_OUTS_L_B11",
"INT_INTERFACE_SW2A1",
"INT_INTERFACE_PHASER_TO_IO_OCLK1X_90",
"INT_INTERFACE_BRAM_UTURN_IMUX22",
"INT_INTERFACE_WW4B1",
"INT_INTERFACE_WW4END2",
"INT_INTERFACE_WW2END3",
"INT_INTERFACE_EE2BEG3",
"INT_INTERFACE_BRAM_UTURN_IMUX38",
"INT_INTERFACE_NW2A2",
"INT_INTERFACE_BRAM_IMUX10",
"INT_INTERFACE_LOGIC_OUTS_L_B10",
"INT_INTERFACE_BYP0",
"INT_INTERFACE_BRAM_IMUX2",
"INT_INTERFACE_LOGIC_OUTS_L_B8",
"INT_INTERFACE_WW4A1",
"INT_INTERFACE_NW2A0",
"INT_INTERFACE_BRAM_IMUX41",
"INT_INTERFACE_LOGIC_OUTS_L16",
"INT_INTERFACE_WW4C0",
"INT_INTERFACE_BRAM_IMUX45",
"INT_INTERFACE_FAN2",
"INT_INTERFACE_NW2A3",
"INT_INTERFACE_NE2A1",
"INT_INTERFACE_FAN0",
"INT_INTERFACE_EE4BEG0",
"INT_INTERFACE_EE2BEG1",
"INT_INTERFACE_BRAM_UTURN_IMUX15",
"INT_INTERFACE_LH6",
"INT_INTERFACE_BRAM_IMUX20",
"INT_INTERFACE_BRAM_UTURN_IMUX0",
"INT_INTERFACE_BRAM_IMUX36",
"INT_INTERFACE_CLK0",
"INT_INTERFACE_WW4B0",
"INT_INTERFACE_EL1BEG0",
"INT_INTERFACE_BRAM_UTURN_IMUX32",
"INT_INTERFACE_LH12",
"INT_INTERFACE_LOGIC_OUTS_L20",
"INT_INTERFACE_EE4BEG3",
"INT_INTERFACE_WR1END2",
"INT_INTERFACE_EE4C0",
"INT_INTERFACE_WR1END0",
"INT_INTERFACE_LOGIC_OUTS_L_B22",
"INT_INTERFACE_WR1END1",
"INT_INTERFACE_BRAM_UTURN_IMUX40",
"INT_INTERFACE_LOGIC_OUTS_L_B13",
"INT_INTERFACE_NE4BEG3",
"INT_INTERFACE_NE4C0",
"INT_INTERFACE_LOGIC_OUTS_L_B6",
"INT_INTERFACE_BYP1",
"INT_INTERFACE_BRAM_IMUX40",
"INT_INTERFACE_BRAM_IMUX5",
"INT_INTERFACE_EE2A0",
"INT_INTERFACE_FAN1",
"INT_INTERFACE_SE4C2",
"INT_INTERFACE_SE2A3",
"INT_INTERFACE_BRAM_IMUX26",
"INT_INTERFACE_WW4END0",
"INT_INTERFACE_BRAM_UTURN_IMUX26",
"INT_INTERFACE_BRAM_UTURN_IMUX42",
"INT_INTERFACE_LOGIC_OUTS_L_B17",
"INT_INTERFACE_WW4END3",
"INT_INTERFACE_BRAM_IMUX25",
"INT_INTERFACE_WW4C3",
"INT_INTERFACE_BRAM_UTURN_IMUX46",
"INT_INTERFACE_NW4END3",
"INT_INTERFACE_MONITOR_P",
"INT_INTERFACE_EE2A3",
"INT_INTERFACE_NE2A0",
"INT_INTERFACE_BRAM_IMUX23",
"INT_INTERFACE_BRAM_IMUX18",
"INT_INTERFACE_LOGIC_OUTS_L5",
"INT_INTERFACE_BRAM_UTURN_IMUX4",
"INT_INTERFACE_PHASER_TO_IO_ICLK",
"INT_INTERFACE_PHASER_TO_IO_OCLKDIV",
"INT_INTERFACE_WW2END1",
"INT_INTERFACE_LOGIC_OUTS_L9",
"INT_INTERFACE_BYP7",
"INT_INTERFACE_NE2A3",
"INT_INTERFACE_EE4A0",
"INT_INTERFACE_BRAM_IMUX38",
"INT_INTERFACE_EE4BEG1",
"INT_INTERFACE_BLOCK_OUTS_L_B2",
"INT_INTERFACE_LOGIC_OUTS_L17",
"INT_INTERFACE_EE2BEG0",
"INT_INTERFACE_LOGIC_OUTS_L_B16",
"INT_INTERFACE_LOGIC_OUTS_L_B15",
"INT_INTERFACE_EE2BEG2",
"INT_INTERFACE_NE4BEG2",
"INT_INTERFACE_LOGIC_OUTS_L0"
],
"pips": {
"BRAM_INT_INTERFACE_L.INT_INTERFACE_LOGIC_OUTS_L_B10->>INT_INTERFACE_LOGIC_OUTS_L10": {
"src_wire": "INT_INTERFACE_LOGIC_OUTS_L_B10",
"is_pseudo": "0",
"dst_wire": "INT_INTERFACE_LOGIC_OUTS_L10",
"is_directional": "1",
"can_invert": "0"
},
"BRAM_INT_INTERFACE_L.INT_INTERFACE_LOGIC_OUTS_L_B13->>INT_INTERFACE_LOGIC_OUTS_L13": {
"src_wire": "INT_INTERFACE_LOGIC_OUTS_L_B13",
"is_pseudo": "0",
"dst_wire": "INT_INTERFACE_LOGIC_OUTS_L13",
"is_directional": "1",
"can_invert": "0"
},
"BRAM_INT_INTERFACE_L.INT_INTERFACE_LOGIC_OUTS_L_B0->>INT_INTERFACE_LOGIC_OUTS_L0": {
"src_wire": "INT_INTERFACE_LOGIC_OUTS_L_B0",
"is_pseudo": "0",
"dst_wire": "INT_INTERFACE_LOGIC_OUTS_L0",
"is_directional": "1",
"can_invert": "0"
},
"BRAM_INT_INTERFACE_L.INT_INTERFACE_LOGIC_OUTS_L_B1->>INT_INTERFACE_LOGIC_OUTS_L1": {
"src_wire": "INT_INTERFACE_LOGIC_OUTS_L_B1",
"is_pseudo": "0",
"dst_wire": "INT_INTERFACE_LOGIC_OUTS_L1",
"is_directional": "1",
"can_invert": "0"
},
"BRAM_INT_INTERFACE_L.INT_INTERFACE_LOGIC_OUTS_L_B15->>INT_INTERFACE_LOGIC_OUTS_L15": {
"src_wire": "INT_INTERFACE_LOGIC_OUTS_L_B15",
"is_pseudo": "0",
"dst_wire": "INT_INTERFACE_LOGIC_OUTS_L15",
"is_directional": "1",
"can_invert": "0"
},
"BRAM_INT_INTERFACE_L.INT_INTERFACE_LOGIC_OUTS_L_B11->>INT_INTERFACE_LOGIC_OUTS_L11": {
"src_wire": "INT_INTERFACE_LOGIC_OUTS_L_B11",
"is_pseudo": "0",
"dst_wire": "INT_INTERFACE_LOGIC_OUTS_L11",
"is_directional": "1",
"can_invert": "0"
},
"BRAM_INT_INTERFACE_L.INT_INTERFACE_LOGIC_OUTS_L_B6->>INT_INTERFACE_LOGIC_OUTS_L6": {
"src_wire": "INT_INTERFACE_LOGIC_OUTS_L_B6",
"is_pseudo": "0",
"dst_wire": "INT_INTERFACE_LOGIC_OUTS_L6",
"is_directional": "1",
"can_invert": "0"
},
"BRAM_INT_INTERFACE_L.INT_INTERFACE_LOGIC_OUTS_L_B18->>INT_INTERFACE_LOGIC_OUTS_L18": {
"src_wire": "INT_INTERFACE_LOGIC_OUTS_L_B18",
"is_pseudo": "0",
"dst_wire": "INT_INTERFACE_LOGIC_OUTS_L18",
"is_directional": "1",
"can_invert": "0"
},
"BRAM_INT_INTERFACE_L.INT_INTERFACE_LOGIC_OUTS_L_B3->>INT_INTERFACE_LOGIC_OUTS_L3": {
"src_wire": "INT_INTERFACE_LOGIC_OUTS_L_B3",
"is_pseudo": "0",
"dst_wire": "INT_INTERFACE_LOGIC_OUTS_L3",
"is_directional": "1",
"can_invert": "0"
},
"BRAM_INT_INTERFACE_L.INT_INTERFACE_LOGIC_OUTS_L_B9->>INT_INTERFACE_LOGIC_OUTS_L9": {
"src_wire": "INT_INTERFACE_LOGIC_OUTS_L_B9",
"is_pseudo": "0",
"dst_wire": "INT_INTERFACE_LOGIC_OUTS_L9",
"is_directional": "1",
"can_invert": "0"
},
"BRAM_INT_INTERFACE_L.INT_INTERFACE_LOGIC_OUTS_L_B5->>INT_INTERFACE_LOGIC_OUTS_L5": {
"src_wire": "INT_INTERFACE_LOGIC_OUTS_L_B5",
"is_pseudo": "0",
"dst_wire": "INT_INTERFACE_LOGIC_OUTS_L5",
"is_directional": "1",
"can_invert": "0"
},
"BRAM_INT_INTERFACE_L.INT_INTERFACE_LOGIC_OUTS_L_B22->>INT_INTERFACE_LOGIC_OUTS_L22": {
"src_wire": "INT_INTERFACE_LOGIC_OUTS_L_B22",
"is_pseudo": "0",
"dst_wire": "INT_INTERFACE_LOGIC_OUTS_L22",
"is_directional": "1",
"can_invert": "0"
},
"BRAM_INT_INTERFACE_L.INT_INTERFACE_LOGIC_OUTS_L_B16->>INT_INTERFACE_LOGIC_OUTS_L16": {
"src_wire": "INT_INTERFACE_LOGIC_OUTS_L_B16",
"is_pseudo": "0",
"dst_wire": "INT_INTERFACE_LOGIC_OUTS_L16",
"is_directional": "1",
"can_invert": "0"
},
"BRAM_INT_INTERFACE_L.INT_INTERFACE_LOGIC_OUTS_L_B4->>INT_INTERFACE_LOGIC_OUTS_L4": {
"src_wire": "INT_INTERFACE_LOGIC_OUTS_L_B4",
"is_pseudo": "0",
"dst_wire": "INT_INTERFACE_LOGIC_OUTS_L4",
"is_directional": "1",
"can_invert": "0"
},
"BRAM_INT_INTERFACE_L.INT_INTERFACE_LOGIC_OUTS_L_B7->>INT_INTERFACE_LOGIC_OUTS_L7": {
"src_wire": "INT_INTERFACE_LOGIC_OUTS_L_B7",
"is_pseudo": "0",
"dst_wire": "INT_INTERFACE_LOGIC_OUTS_L7",
"is_directional": "1",
"can_invert": "0"
},
"BRAM_INT_INTERFACE_L.INT_INTERFACE_LOGIC_OUTS_L_B23->>INT_INTERFACE_LOGIC_OUTS_L23": {
"src_wire": "INT_INTERFACE_LOGIC_OUTS_L_B23",
"is_pseudo": "0",
"dst_wire": "INT_INTERFACE_LOGIC_OUTS_L23",
"is_directional": "1",
"can_invert": "0"
},
"BRAM_INT_INTERFACE_L.INT_INTERFACE_LOGIC_OUTS_L_B20->>INT_INTERFACE_LOGIC_OUTS_L20": {
"src_wire": "INT_INTERFACE_LOGIC_OUTS_L_B20",
"is_pseudo": "0",
"dst_wire": "INT_INTERFACE_LOGIC_OUTS_L20",
"is_directional": "1",
"can_invert": "0"
},
"BRAM_INT_INTERFACE_L.INT_INTERFACE_LOGIC_OUTS_L_B14->>INT_INTERFACE_LOGIC_OUTS_L14": {
"src_wire": "INT_INTERFACE_LOGIC_OUTS_L_B14",
"is_pseudo": "0",
"dst_wire": "INT_INTERFACE_LOGIC_OUTS_L14",
"is_directional": "1",
"can_invert": "0"
},
"BRAM_INT_INTERFACE_L.INT_INTERFACE_LOGIC_OUTS_L_B21->>INT_INTERFACE_LOGIC_OUTS_L21": {
"src_wire": "INT_INTERFACE_LOGIC_OUTS_L_B21",
"is_pseudo": "0",
"dst_wire": "INT_INTERFACE_LOGIC_OUTS_L21",
"is_directional": "1",
"can_invert": "0"
},
"BRAM_INT_INTERFACE_L.INT_INTERFACE_LOGIC_OUTS_L_B12->>INT_INTERFACE_LOGIC_OUTS_L12": {
"src_wire": "INT_INTERFACE_LOGIC_OUTS_L_B12",
"is_pseudo": "0",
"dst_wire": "INT_INTERFACE_LOGIC_OUTS_L12",
"is_directional": "1",
"can_invert": "0"
},
"BRAM_INT_INTERFACE_L.INT_INTERFACE_LOGIC_OUTS_L_B8->>INT_INTERFACE_LOGIC_OUTS_L8": {
"src_wire": "INT_INTERFACE_LOGIC_OUTS_L_B8",
"is_pseudo": "0",
"dst_wire": "INT_INTERFACE_LOGIC_OUTS_L8",
"is_directional": "1",
"can_invert": "0"
},
"BRAM_INT_INTERFACE_L.INT_INTERFACE_LOGIC_OUTS_L_B2->>INT_INTERFACE_LOGIC_OUTS_L2": {
"src_wire": "INT_INTERFACE_LOGIC_OUTS_L_B2",
"is_pseudo": "0",
"dst_wire": "INT_INTERFACE_LOGIC_OUTS_L2",
"is_directional": "1",
"can_invert": "0"
},
"BRAM_INT_INTERFACE_L.INT_INTERFACE_LOGIC_OUTS_L_B19->>INT_INTERFACE_LOGIC_OUTS_L19": {
"src_wire": "INT_INTERFACE_LOGIC_OUTS_L_B19",
"is_pseudo": "0",
"dst_wire": "INT_INTERFACE_LOGIC_OUTS_L19",
"is_directional": "1",
"can_invert": "0"
},
"BRAM_INT_INTERFACE_L.INT_INTERFACE_LOGIC_OUTS_L_B17->>INT_INTERFACE_LOGIC_OUTS_L17": {
"src_wire": "INT_INTERFACE_LOGIC_OUTS_L_B17",
"is_pseudo": "0",
"dst_wire": "INT_INTERFACE_LOGIC_OUTS_L17",
"is_directional": "1",
"can_invert": "0"
}
}
}

476
kintex7/tile_type_BRAM_INT_INTERFACE_R.json Normal file
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{
"tile_type": "BRAM_INT_INTERFACE_R",
"sites": [],
"wires": [
"INT_INTERFACE_EE4C1",
"INT_INTERFACE_BRAM_UTURN_R_IMUX19",
"INT_INTERFACE_BRAM_IMUX14",
"INT_INTERFACE_BRAM_IMUX19",
"INT_INTERFACE_SW4END0",
"INT_INTERFACE_BRAM_UTURN_R_IMUX39",
"INT_INTERFACE_SW4END3",
"INT_INTERFACE_EE4B1",
"INT_INTERFACE_WW4C2",
"INT_INTERFACE_LH7",
"INT_INTERFACE_BRAM_IMUX37",
"INT_INTERFACE_EE4C3",
"INT_INTERFACE_BRAM_UTURN_R_IMUX41",
"INT_INTERFACE_BRAM_UTURN_R_IMUX0",
"INT_INTERFACE_WL1END2",
"INT_INTERFACE_LOGIC_OUTS_B22",
"INT_INTERFACE_BYP2",
"INT_INTERFACE_LOGIC_OUTS16",
"INT_INTERFACE_BRAM_IMUX13",
"INT_INTERFACE_EE2A2",
"INT_INTERFACE_NW2A1",
"INT_INTERFACE_NW4A0",
"INT_INTERFACE_LOGIC_OUTS3",
"INT_INTERFACE_BRAM_IMUX44",
"INT_INTERFACE_WW2END2",
"INT_INTERFACE_LOGIC_OUTS20",
"INT_INTERFACE_LOGIC_OUTS22",
"INT_INTERFACE_BRAM_IMUX34",
"INT_INTERFACE_NW4A1",
"INT_INTERFACE_BRAM_IMUX17",
"INT_INTERFACE_WW2A1",
"INT_INTERFACE_EE4B3",
"INT_INTERFACE_WW2A3",
"INT_INTERFACE_LH8",
"INT_INTERFACE_SE2A1",
"INT_INTERFACE_LH11",
"INT_INTERFACE_BRAM_IMUX39",
"INT_INTERFACE_BRAM_IMUX4",
"INT_INTERFACE_NW4A3",
"INT_INTERFACE_LOGIC_OUTS1",
"INT_INTERFACE_BRAM_UTURN_R_IMUX33",
"INT_INTERFACE_EE4A2",
"INT_INTERFACE_LOGIC_OUTS0",
"INT_INTERFACE_BLOCK_OUTS_B0",
"INT_INTERFACE_SE2A2",
"INT_INTERFACE_BRAM_IMUX16",
"INT_INTERFACE_BRAM_UTURN_R_IMUX24",
"INT_INTERFACE_BRAM_IMUX27",
"INT_INTERFACE_BRAM_UTURN_R_IMUX18",
"INT_INTERFACE_BRAM_UTURN_R_IMUX10",
"INT_INTERFACE_WW4C1",
"INT_INTERFACE_BRAM_UTURN_R_IMUX6",
"INT_INTERFACE_SW2A3",
"INT_INTERFACE_SE4BEG2",
"INT_INTERFACE_EL1BEG2",
"INT_INTERFACE_EL1BEG3",
"INT_INTERFACE_BRAM_UTURN_R_IMUX26",
"INT_INTERFACE_BRAM_IMUX1",
"L_INT_INTER_DQS_IOTOPHASER",
"INT_INTERFACE_LH5",
"INT_INTERFACE_BRAM_UTURN_R_IMUX28",
"INT_INTERFACE_BRAM_IMUX12",
"INT_INTERFACE_BLOCK_OUTS_B3",
"INT_INTERFACE_EE4A1",
"INT_INTERFACE_FAN6",
"INT_INTERFACE_BRAM_IMUX43",
"INT_INTERFACE_BRAM_UTURN_R_IMUX5",
"INT_INTERFACE_BRAM_UTURN_R_IMUX25",
"INT_INTERFACE_WW4B3",
"INT_INTERFACE_PHASER_TO_IO_OCLK",
"INT_INTERFACE_SW4END1",
"INT_INTERFACE_SE4BEG3",
"INT_INTERFACE_BRAM_IMUX29",
"INT_INTERFACE_LOGIC_OUTS_B2",
"INT_INTERFACE_WW4END1",
"INT_INTERFACE_SE4BEG0",
"INT_INTERFACE_WL1END3",
"INT_INTERFACE_LOGIC_OUTS_B20",
"INT_INTERFACE_BRAM_UTURN_R_IMUX7",
"INT_INTERFACE_SW2A2",
"INT_INTERFACE_NE2A2",
"INT_INTERFACE_BYP6",
"INT_INTERFACE_BRAM_UTURN_R_IMUX42",
"INT_INTERFACE_BRAM_UTURN_R_IMUX16",
"INT_INTERFACE_WL1END1",
"INT_INTERFACE_BRAM_IMUX15",
"INT_INTERFACE_LOGIC_OUTS_B23",
"INT_INTERFACE_BRAM_UTURN_R_IMUX9",
"INT_INTERFACE_WW4A2",
"INT_INTERFACE_BRAM_UTURN_R_IMUX29",
"INT_INTERFACE_BRAM_UTURN_R_IMUX1",
"INT_INTERFACE_BRAM_IMUX11",
"INT_INTERFACE_NW4END1",
"INT_INTERFACE_LH10",
"INT_INTERFACE_BRAM_IMUX42",
"INT_INTERFACE_NW4END0",
"INT_INTERFACE_BRAM_IMUX7",
"INT_INTERFACE_LOGIC_OUTS_B6",
"INT_INTERFACE_BRAM_IMUX0",
"INT_INTERFACE_NE4C3",
"INT_INTERFACE_BRAM_UTURN_R_IMUX31",
"INT_INTERFACE_EE4C2",
"INT_INTERFACE_BRAM_IMUX46",
"INT_INTERFACE_LOGIC_OUTS18",
"INT_INTERFACE_BRAM_UTURN_R_IMUX35",
"INT_INTERFACE_BRAM_IMUX28",
"INT_INTERFACE_EL1BEG1",
"INT_INTERFACE_BRAM_IMUX9",
"INT_INTERFACE_PHASER_TO_IO_ICLKDIV",
"INT_INTERFACE_BRAM_IMUX21",
"INT_INTERFACE_LOGIC_OUTS_B16",
"INT_INTERFACE_FAN7",
"INT_INTERFACE_LH2",
"INT_INTERFACE_BRAM_IMUX31",
"INT_INTERFACE_LOGIC_OUTS_B14",
"INT_INTERFACE_BRAM_UTURN_R_IMUX21",
"INT_INTERFACE_SW4A0",
"INT_INTERFACE_CTRL1",
"INT_INTERFACE_BRAM_UTURN_R_IMUX37",
"INT_INTERFACE_BRAM_IMUX33",
"INT_INTERFACE_BRAM_UTURN_R_IMUX27",
"INT_INTERFACE_EE2A1",
"INT_INTERFACE_BRAM_UTURN_R_IMUX4",
"INT_INTERFACE_SW4A2",
"INT_INTERFACE_BRAM_UTURN_R_IMUX45",
"INT_INTERFACE_LOGIC_OUTS23",
"INT_INTERFACE_WW2A2",
"INT_INTERFACE_BRAM_IMUX22",
"INT_INTERFACE_EE4A3",
"INT_INTERFACE_BRAM_UTURN_R_IMUX11",
"INT_INTERFACE_LH1",
"INT_INTERFACE_BRAM_UTURN_R_IMUX17",
"INT_INTERFACE_LOGIC_OUTS5",
"INT_INTERFACE_WW4A3",
"INT_INTERFACE_ER1BEG0",
"INT_INTERFACE_LH9",
"INT_INTERFACE_NW4END2",
"INT_INTERFACE_LH4",
"INT_INTERFACE_FAN3",
"INT_INTERFACE_BRAM_IMUX3",
"INT_INTERFACE_NE4C1",
"INT_INTERFACE_NE4BEG1",
"INT_INTERFACE_FAN4",
"INT_INTERFACE_MONITOR_N",
"INT_INTERFACE_ER1BEG2",
"INT_INTERFACE_WR1END3",
"INT_INTERFACE_BRAM_IMUX32",
"INT_INTERFACE_BYP3",
"INT_INTERFACE_ER1BEG1",
"INT_INTERFACE_LOGIC_OUTS15",
"INT_INTERFACE_BRAM_IMUX24",
"INT_INTERFACE_LOGIC_OUTS_B19",
"INT_INTERFACE_EE4B0",
"INT_INTERFACE_NW4A2",
"INT_INTERFACE_BRAM_UTURN_R_IMUX43",
"INT_INTERFACE_LOGIC_OUTS11",
"INT_INTERFACE_WL1END0",
"INT_INTERFACE_BRAM_IMUX8",
"INT_INTERFACE_SW4END2",
"INT_INTERFACE_LOGIC_OUTS_B17",
"INT_INTERFACE_LH3",
"INT_INTERFACE_SE4C0",
"INT_INTERFACE_BYP4",
"INT_INTERFACE_LOGIC_OUTS_B15",
"INT_INTERFACE_LOGIC_OUTS_B9",
"INT_INTERFACE_SW4A3",
"INT_INTERFACE_LOGIC_OUTS_B0",
"INT_INTERFACE_BRAM_UTURN_R_IMUX12",
"INT_INTERFACE_SW4A1",
"INT_INTERFACE_EE4B2",
"INT_INTERFACE_BLOCK_OUTS_B1",
"INT_INTERFACE_LOGIC_OUTS_B7",
"INT_INTERFACE_BRAM_UTURN_R_IMUX14",
"INT_INTERFACE_LOGIC_OUTS_B8",
"INT_INTERFACE_LOGIC_OUTS14",
"INT_INTERFACE_CTRL0",
"INT_INTERFACE_LOGIC_OUTS8",
"INT_INTERFACE_BRAM_IMUX30",
"INT_INTERFACE_WW4B2",
"INT_INTERFACE_BRAM_IMUX6",
"INT_INTERFACE_LOGIC_OUTS12",
"INT_INTERFACE_BRAM_UTURN_R_IMUX36",
"INT_INTERFACE_NE4C2",
"INT_INTERFACE_SW2A0",
"INT_INTERFACE_LOGIC_OUTS4",
"INT_INTERFACE_BRAM_UTURN_R_IMUX2",
"INT_INTERFACE_WW4A0",
"INT_INTERFACE_LOGIC_OUTS_B3",
"INT_INTERFACE_LOGIC_OUTS21",
"INT_INTERFACE_FAN5",
"INT_INTERFACE_CLK1",
"INT_INTERFACE_BRAM_UTURN_R_IMUX46",
"INT_INTERFACE_LOGIC_OUTS7",
"INT_INTERFACE_SE4C3",
"INT_INTERFACE_BRAM_UTURN_R_IMUX30",
"INT_INTERFACE_SE4C1",
"INT_INTERFACE_LOGIC_OUTS_B18",
"INT_INTERFACE_BYP5",
"INT_INTERFACE_SE2A0",
"INT_INTERFACE_EE4BEG2",
"INT_INTERFACE_SE4BEG1",
"INT_INTERFACE_BRAM_IMUX47",
"INT_INTERFACE_BRAM_UTURN_R_IMUX38",
"INT_INTERFACE_NE4BEG0",
"INT_INTERFACE_WW2A0",
"INT_INTERFACE_BRAM_IMUX35",
"INT_INTERFACE_ER1BEG3",
"INT_INTERFACE_WW2END0",
"INT_INTERFACE_LOGIC_OUTS_B4",
"INT_INTERFACE_SW2A1",
"INT_INTERFACE_PHASER_TO_IO_OCLK1X_90",
"INT_INTERFACE_WW4B1",
"INT_INTERFACE_WW4END2",
"INT_INTERFACE_WW2END3",
"INT_INTERFACE_EE2BEG3",
"INT_INTERFACE_LOGIC_OUTS_B21",
"INT_INTERFACE_NW2A2",
"INT_INTERFACE_BRAM_IMUX10",
"INT_INTERFACE_BYP0",
"INT_INTERFACE_BRAM_UTURN_R_IMUX23",
"INT_INTERFACE_WW4A1",
"INT_INTERFACE_BRAM_IMUX2",
"INT_INTERFACE_NW2A0",
"INT_INTERFACE_BRAM_IMUX41",
"INT_INTERFACE_WW4C0",
"INT_INTERFACE_BRAM_IMUX45",
"INT_INTERFACE_FAN2",
"INT_INTERFACE_NW2A3",
"INT_INTERFACE_NE2A1",
"INT_INTERFACE_FAN0",
"INT_INTERFACE_BRAM_UTURN_R_IMUX8",
"INT_INTERFACE_EE4BEG0",
"INT_INTERFACE_EE2BEG1",
"INT_INTERFACE_LH6",
"INT_INTERFACE_BRAM_IMUX20",
"INT_INTERFACE_BRAM_IMUX36",
"INT_INTERFACE_CLK0",
"INT_INTERFACE_WW4B0",
"INT_INTERFACE_EL1BEG0",
"INT_INTERFACE_LH12",
"INT_INTERFACE_BRAM_UTURN_R_IMUX40",
"INT_INTERFACE_WR1END2",
"INT_INTERFACE_EE4BEG3",
"INT_INTERFACE_EE4C0",
"INT_INTERFACE_WR1END0",
"INT_INTERFACE_WR1END1",
"INT_INTERFACE_LOGIC_OUTS10",
"INT_INTERFACE_BRAM_UTURN_R_IMUX3",
"INT_INTERFACE_NE4BEG3",
"INT_INTERFACE_NE4C0",
"INT_INTERFACE_LOGIC_OUTS13",
"INT_INTERFACE_BRAM_UTURN_R_IMUX47",
"INT_INTERFACE_BRAM_UTURN_R_IMUX44",
"INT_INTERFACE_LOGIC_OUTS_B11",
"INT_INTERFACE_LOGIC_OUTS9",
"INT_INTERFACE_BYP1",
"INT_INTERFACE_BRAM_IMUX40",
"INT_INTERFACE_BRAM_IMUX5",
"INT_INTERFACE_EE2A0",
"INT_INTERFACE_BRAM_UTURN_R_IMUX13",
"INT_INTERFACE_LOGIC_OUTS_B10",
"INT_INTERFACE_FAN1",
"INT_INTERFACE_LOGIC_OUTS_B5",
"INT_INTERFACE_SE4C2",
"INT_INTERFACE_LOGIC_OUTS19",
"INT_INTERFACE_BRAM_UTURN_R_IMUX20",
"INT_INTERFACE_SE2A3",
"INT_INTERFACE_BRAM_IMUX26",
"INT_INTERFACE_BLOCK_OUTS_B2",
"INT_INTERFACE_WW4END0",
"INT_INTERFACE_LOGIC_OUTS17",
"INT_INTERFACE_BRAM_IMUX25",
"INT_INTERFACE_WW4END3",
"INT_INTERFACE_LOGIC_OUTS_B13",
"INT_INTERFACE_WW4C3",
"INT_INTERFACE_MONITOR_P",
"INT_INTERFACE_NW4END3",
"INT_INTERFACE_EE2A3",
"INT_INTERFACE_NE2A0",
"INT_INTERFACE_BRAM_IMUX23",
"INT_INTERFACE_BRAM_IMUX18",
"INT_INTERFACE_LOGIC_OUTS2",
"INT_INTERFACE_PHASER_TO_IO_ICLK",
"INT_INTERFACE_PHASER_TO_IO_OCLKDIV",
"INT_INTERFACE_WW2END1",
"INT_INTERFACE_BRAM_UTURN_R_IMUX34",
"INT_INTERFACE_LOGIC_OUTS6",
"INT_INTERFACE_BYP7",
"INT_INTERFACE_NE2A3",
"INT_INTERFACE_EE4A0",
"INT_INTERFACE_BRAM_IMUX38",
"INT_INTERFACE_EE4BEG1",
"INT_INTERFACE_BRAM_UTURN_R_IMUX32",
"INT_INTERFACE_EE2BEG0",
"INT_INTERFACE_BRAM_UTURN_R_IMUX15",
"INT_INTERFACE_LOGIC_OUTS_B12",
"INT_INTERFACE_BRAM_UTURN_R_IMUX22",
"INT_INTERFACE_EE2BEG2",
"INT_INTERFACE_NE4BEG2",
"INT_INTERFACE_LOGIC_OUTS_B1"
],
"pips": {
"BRAM_INT_INTERFACE_R.INT_INTERFACE_LOGIC_OUTS_B2->>INT_INTERFACE_LOGIC_OUTS2": {
"src_wire": "INT_INTERFACE_LOGIC_OUTS_B2",
"is_pseudo": "0",
"dst_wire": "INT_INTERFACE_LOGIC_OUTS2",
"is_directional": "1",
"can_invert": "0"
},
"BRAM_INT_INTERFACE_R.INT_INTERFACE_LOGIC_OUTS_B19->>INT_INTERFACE_LOGIC_OUTS19": {
"src_wire": "INT_INTERFACE_LOGIC_OUTS_B19",
"is_pseudo": "0",
"dst_wire": "INT_INTERFACE_LOGIC_OUTS19",
"is_directional": "1",
"can_invert": "0"
},
"BRAM_INT_INTERFACE_R.INT_INTERFACE_LOGIC_OUTS_B4->>INT_INTERFACE_LOGIC_OUTS4": {
"src_wire": "INT_INTERFACE_LOGIC_OUTS_B4",
"is_pseudo": "0",
"dst_wire": "INT_INTERFACE_LOGIC_OUTS4",
"is_directional": "1",
"can_invert": "0"
},
"BRAM_INT_INTERFACE_R.INT_INTERFACE_LOGIC_OUTS_B6->>INT_INTERFACE_LOGIC_OUTS6": {
"src_wire": "INT_INTERFACE_LOGIC_OUTS_B6",
"is_pseudo": "0",
"dst_wire": "INT_INTERFACE_LOGIC_OUTS6",
"is_directional": "1",
"can_invert": "0"
},
"BRAM_INT_INTERFACE_R.INT_INTERFACE_LOGIC_OUTS_B0->>INT_INTERFACE_LOGIC_OUTS0": {
"src_wire": "INT_INTERFACE_LOGIC_OUTS_B0",
"is_pseudo": "0",
"dst_wire": "INT_INTERFACE_LOGIC_OUTS0",
"is_directional": "1",
"can_invert": "0"
},
"BRAM_INT_INTERFACE_R.INT_INTERFACE_LOGIC_OUTS_B21->>INT_INTERFACE_LOGIC_OUTS21": {
"src_wire": "INT_INTERFACE_LOGIC_OUTS_B21",
"is_pseudo": "0",
"dst_wire": "INT_INTERFACE_LOGIC_OUTS21",
"is_directional": "1",
"can_invert": "0"
},
"BRAM_INT_INTERFACE_R.INT_INTERFACE_LOGIC_OUTS_B1->>INT_INTERFACE_LOGIC_OUTS1": {
"src_wire": "INT_INTERFACE_LOGIC_OUTS_B1",
"is_pseudo": "0",
"dst_wire": "INT_INTERFACE_LOGIC_OUTS1",
"is_directional": "1",
"can_invert": "0"
},
"BRAM_INT_INTERFACE_R.INT_INTERFACE_LOGIC_OUTS_B15->>INT_INTERFACE_LOGIC_OUTS15": {
"src_wire": "INT_INTERFACE_LOGIC_OUTS_B15",
"is_pseudo": "0",
"dst_wire": "INT_INTERFACE_LOGIC_OUTS15",
"is_directional": "1",
"can_invert": "0"
},
"BRAM_INT_INTERFACE_R.INT_INTERFACE_LOGIC_OUTS_B22->>INT_INTERFACE_LOGIC_OUTS22": {
"src_wire": "INT_INTERFACE_LOGIC_OUTS_B22",
"is_pseudo": "0",
"dst_wire": "INT_INTERFACE_LOGIC_OUTS22",
"is_directional": "1",
"can_invert": "0"
},
"BRAM_INT_INTERFACE_R.INT_INTERFACE_LOGIC_OUTS_B14->>INT_INTERFACE_LOGIC_OUTS14": {
"src_wire": "INT_INTERFACE_LOGIC_OUTS_B14",
"is_pseudo": "0",
"dst_wire": "INT_INTERFACE_LOGIC_OUTS14",
"is_directional": "1",
"can_invert": "0"
},
"BRAM_INT_INTERFACE_R.INT_INTERFACE_LOGIC_OUTS_B5->>INT_INTERFACE_LOGIC_OUTS5": {
"src_wire": "INT_INTERFACE_LOGIC_OUTS_B5",
"is_pseudo": "0",
"dst_wire": "INT_INTERFACE_LOGIC_OUTS5",
"is_directional": "1",
"can_invert": "0"
},
"BRAM_INT_INTERFACE_R.INT_INTERFACE_LOGIC_OUTS_B11->>INT_INTERFACE_LOGIC_OUTS11": {
"src_wire": "INT_INTERFACE_LOGIC_OUTS_B11",
"is_pseudo": "0",
"dst_wire": "INT_INTERFACE_LOGIC_OUTS11",
"is_directional": "1",
"can_invert": "0"
},
"BRAM_INT_INTERFACE_R.INT_INTERFACE_LOGIC_OUTS_B12->>INT_INTERFACE_LOGIC_OUTS12": {
"src_wire": "INT_INTERFACE_LOGIC_OUTS_B12",
"is_pseudo": "0",
"dst_wire": "INT_INTERFACE_LOGIC_OUTS12",
"is_directional": "1",
"can_invert": "0"
},
"BRAM_INT_INTERFACE_R.INT_INTERFACE_LOGIC_OUTS_B16->>INT_INTERFACE_LOGIC_OUTS16": {
"src_wire": "INT_INTERFACE_LOGIC_OUTS_B16",
"is_pseudo": "0",
"dst_wire": "INT_INTERFACE_LOGIC_OUTS16",
"is_directional": "1",
"can_invert": "0"
},
"BRAM_INT_INTERFACE_R.INT_INTERFACE_LOGIC_OUTS_B9->>INT_INTERFACE_LOGIC_OUTS9": {
"src_wire": "INT_INTERFACE_LOGIC_OUTS_B9",
"is_pseudo": "0",
"dst_wire": "INT_INTERFACE_LOGIC_OUTS9",
"is_directional": "1",
"can_invert": "0"
},
"BRAM_INT_INTERFACE_R.INT_INTERFACE_LOGIC_OUTS_B23->>INT_INTERFACE_LOGIC_OUTS23": {
"src_wire": "INT_INTERFACE_LOGIC_OUTS_B23",
"is_pseudo": "0",
"dst_wire": "INT_INTERFACE_LOGIC_OUTS23",
"is_directional": "1",
"can_invert": "0"
},
"BRAM_INT_INTERFACE_R.INT_INTERFACE_LOGIC_OUTS_B7->>INT_INTERFACE_LOGIC_OUTS7": {
"src_wire": "INT_INTERFACE_LOGIC_OUTS_B7",
"is_pseudo": "0",
"dst_wire": "INT_INTERFACE_LOGIC_OUTS7",
"is_directional": "1",
"can_invert": "0"
},
"BRAM_INT_INTERFACE_R.INT_INTERFACE_LOGIC_OUTS_B13->>INT_INTERFACE_LOGIC_OUTS13": {
"src_wire": "INT_INTERFACE_LOGIC_OUTS_B13",
"is_pseudo": "0",
"dst_wire": "INT_INTERFACE_LOGIC_OUTS13",
"is_directional": "1",
"can_invert": "0"
},
"BRAM_INT_INTERFACE_R.INT_INTERFACE_LOGIC_OUTS_B10->>INT_INTERFACE_LOGIC_OUTS10": {
"src_wire": "INT_INTERFACE_LOGIC_OUTS_B10",
"is_pseudo": "0",
"dst_wire": "INT_INTERFACE_LOGIC_OUTS10",
"is_directional": "1",
"can_invert": "0"
},
"BRAM_INT_INTERFACE_R.INT_INTERFACE_LOGIC_OUTS_B17->>INT_INTERFACE_LOGIC_OUTS17": {
"src_wire": "INT_INTERFACE_LOGIC_OUTS_B17",
"is_pseudo": "0",
"dst_wire": "INT_INTERFACE_LOGIC_OUTS17",
"is_directional": "1",
"can_invert": "0"
},
"BRAM_INT_INTERFACE_R.INT_INTERFACE_LOGIC_OUTS_B20->>INT_INTERFACE_LOGIC_OUTS20": {
"src_wire": "INT_INTERFACE_LOGIC_OUTS_B20",
"is_pseudo": "0",
"dst_wire": "INT_INTERFACE_LOGIC_OUTS20",
"is_directional": "1",
"can_invert": "0"
},
"BRAM_INT_INTERFACE_R.INT_INTERFACE_LOGIC_OUTS_B8->>INT_INTERFACE_LOGIC_OUTS8": {
"src_wire": "INT_INTERFACE_LOGIC_OUTS_B8",
"is_pseudo": "0",
"dst_wire": "INT_INTERFACE_LOGIC_OUTS8",
"is_directional": "1",
"can_invert": "0"
},
"BRAM_INT_INTERFACE_R.INT_INTERFACE_LOGIC_OUTS_B3->>INT_INTERFACE_LOGIC_OUTS3": {
"src_wire": "INT_INTERFACE_LOGIC_OUTS_B3",
"is_pseudo": "0",
"dst_wire": "INT_INTERFACE_LOGIC_OUTS3",
"is_directional": "1",
"can_invert": "0"
},
"BRAM_INT_INTERFACE_R.INT_INTERFACE_LOGIC_OUTS_B18->>INT_INTERFACE_LOGIC_OUTS18": {
"src_wire": "INT_INTERFACE_LOGIC_OUTS_B18",
"is_pseudo": "0",
"dst_wire": "INT_INTERFACE_LOGIC_OUTS18",
"is_directional": "1",
"can_invert": "0"
}
}
}

9834
kintex7/tile_type_BRAM_L.json Normal file
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9834
kintex7/tile_type_BRAM_R.json Normal file
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71
kintex7/tile_type_BRKH_BRAM.json Normal file
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@ -0,0 +1,71 @@
{
"tile_type": "BRKH_BRAM",
"sites": [],
"wires": [
"BRKH_BRAM_CASCADEA_L",
"BRKH_BRAM_CASCIN_L_ADDRARDADDRU8",
"BRKH_BRAM_CASCIN_L_ADDRBWRADDRU9",
"BRKH_BRAM_CASCOUT_L_ADDRARDADDRU11",
"BRKH_BRAM_CASCIN_L_ADDRARDADDRU7",
"BRKH_BRAM_CASCIN_L_ADDRBWRADDRU3",
"BRKH_BRAM_CASCIN_L_ADDRBWRADDRU1",
"BRKH_BRAM_CASCADEA_R",
"BRKH_BRAM_CASCOUT_L_ADDRBWRADDRU13",
"BRKH_BRAM_CASCOUT_L_ADDRBWRADDRU4",
"BRKH_BRAM_CASCOUT_L_ADDRBWRADDRU5",
"BRKH_BRAM_CASCOUT_L_ADDRBWRADDRU11",
"BRKH_BRAM_CASCIN_L_ADDRBWRADDRU12",
"BRKH_BRAM_CASCOUT_L_ADDRARDADDRU10",
"BRKH_BRAM_CASCIN_L_ADDRBWRADDRU6",
"BRKH_BRAM_CASCIN_L_ADDRARDADDRU4",
"BRKH_BRAM_CASCOUT_L_ADDRARDADDRU9",
"BRKH_BRAM_CASCADEB_L",
"BRKH_BRAM_CASCOUT_L_ADDRBWRADDRU0",
"BRKH_BRAM_CASCOUT_L_ADDRARDADDRU5",
"BRKH_BRAM_CASCOUT_L_ADDRBWRADDRU9",
"BRKH_BRAM_CASCOUT_L_ADDRARDADDRU3",
"BRKH_BRAM_CASCIN_L_ADDRARDADDRU2",
"BRKH_BRAM_CASCIN_L_ADDRBWRADDRU14",
"BRKH_BRAM_CASCOUT_L_ADDRBWRADDRU2",
"BRKH_BRAM_CASCOUT_L_ADDRARDADDRU13",
"BRKH_BRAM_CASCOUT_L_ADDRARDADDRU1",
"BRKH_BRAM_CASCOUT_L_ADDRBWRADDRU12",
"BRKH_BRAM_CASCADEB_R",
"BRKH_BRAM_CASCOUT_L_ADDRBWRADDRU10",
"BRKH_BRAM_CASCOUT_L_ADDRBWRADDRU1",
"BRKH_BRAM_CASCIN_L_ADDRBWRADDRU2",
"BRKH_BRAM_CASCIN_L_ADDRARDADDRU0",
"BRKH_BRAM_CASCIN_L_ADDRBWRADDRU11",
"BRKH_BRAM_CASCIN_L_ADDRBWRADDRU4",
"BRKH_BRAM_CASCOUT_L_ADDRBWRADDRU6",
"BRKH_BRAM_CASCIN_L_ADDRBWRADDRU8",
"BRKH_BRAM_CASCOUT_L_ADDRARDADDRU12",
"BRKH_BRAM_CASCOUT_L_ADDRARDADDRU0",
"BRKH_BRAM_CASCOUT_L_ADDRARDADDRU14",
"BRKH_BRAM_CASCOUT_L_ADDRARDADDRU8",
"BRKH_BRAM_CASCOUT_L_ADDRBWRADDRU7",
"BRKH_BRAM_CASCIN_L_ADDRBWRADDRU0",
"BRKH_BRAM_CASCIN_L_ADDRARDADDRU6",
"BRKH_BRAM_CASCIN_L_ADDRARDADDRU13",
"BRKH_BRAM_CASCIN_L_ADDRARDADDRU14",
"BRKH_BRAM_CASCIN_L_ADDRBWRADDRU13",
"BRKH_BRAM_CASCOUT_L_ADDRARDADDRU6",
"BRKH_BRAM_CASCIN_L_ADDRARDADDRU1",
"BRKH_BRAM_CASCOUT_L_ADDRBWRADDRU3",
"BRKH_BRAM_CASCOUT_L_ADDRARDADDRU2",
"BRKH_BRAM_CASCOUT_L_ADDRBWRADDRU14",
"BRKH_BRAM_CASCIN_L_ADDRARDADDRU5",
"BRKH_BRAM_CASCIN_L_ADDRARDADDRU12",
"BRKH_BRAM_CASCIN_L_ADDRARDADDRU11",
"BRKH_BRAM_CASCIN_L_ADDRBWRADDRU7",
"BRKH_BRAM_CASCOUT_L_ADDRBWRADDRU8",
"BRKH_BRAM_CASCOUT_L_ADDRARDADDRU4",
"BRKH_BRAM_CASCIN_L_ADDRARDADDRU10",
"BRKH_BRAM_CASCIN_L_ADDRBWRADDRU5",
"BRKH_BRAM_CASCIN_L_ADDRARDADDRU3",
"BRKH_BRAM_CASCIN_L_ADDRBWRADDRU10",
"BRKH_BRAM_CASCIN_L_ADDRARDADDRU9",
"BRKH_BRAM_CASCOUT_L_ADDRARDADDRU7"
],
"pips": {}
}

125
kintex7/tile_type_BRKH_B_TERM_INT.json Normal file
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{
"tile_type": "BRKH_B_TERM_INT",
"sites": [],
"wires": [
"B_TERM_UTURN_INT_SW6D0",
"B_TERM_UTURN_INT_SS6A1",
"B_TERM_UTURN_INT_LVB5",
"B_TERM_UTURN_INT_SS2BEG2",
"B_TERM_UTURN_INT_LV8",
"B_TERM_UTURN_INT_SW2BEG2",
"B_TERM_UTURN_INT_SS6E0",
"B_TERM_UTURN_INT_SE6A0",
"B_TERM_UTURN_INT_SS6B3",
"B_TERM_UTURN_INT_FAN_BOUNCE4",
"B_TERM_UTURN_INT_SS6A2",
"B_TERM_UTURN_INT_LV9",
"B_TERM_UTURN_INT_SS6B0",
"B_TERM_UTURN_INT_SR1BEG3",
"B_TERM_UTURN_INT_LV_L2",
"B_TERM_UTURN_INT_SS6BEG3",
"B_TERM_UTURN_INT_LVB_L4",
"B_TERM_UTURN_INT_SW6A2",
"B_TERM_UTURN_INT_SE6C0",
"B_TERM_UTURN_INT_LVB_L5",
"B_TERM_UTURN_INT_ER1BEG0",
"B_TERM_UTURN_INT_LVB1",
"B_TERM_UTURN_INT_LVB_L3",
"B_TERM_UTURN_INT_SE6C3",
"B_TERM_UTURN_INT_SS6C3",
"B_TERM_UTURN_INT_FAN_BOUNCE2",
"B_TERM_UTURN_INT_LV_L9",
"B_TERM_UTURN_INT_SS6D0",
"B_TERM_UTURN_INT_LV2",
"B_TERM_UTURN_INT_LVB_L1",
"B_TERM_UTURN_INT_SS6E2",
"B_TERM_UTURN_INT_SE6D3",
"B_TERM_UTURN_INT_SW6D3",
"B_TERM_UTURN_INT_LVB0",
"B_TERM_UTURN_INT_SS2BEG0",
"B_TERM_UTURN_INT_SS6D2",
"B_TERM_UTURN_INT_SR1BEG1",
"B_TERM_UTURN_INT_SS6E3",
"B_TERM_UTURN_INT_SW2BEG0",
"B_TERM_UTURN_INT_SS6D1",
"B_TERM_UTURN_INT_LVB2",
"B_TERM_UTURN_INT_SS6BEG1",
"B_TERM_UTURN_INT_SE6D2",
"B_TERM_UTURN_INT_SR1BEG2",
"B_TERM_UTURN_INT_SL1BEG1",
"B_TERM_UTURN_INT_SE6B1",
"B_TERM_UTURN_INT_LV_L7",
"B_TERM_UTURN_INT_LVB_L2",
"B_TERM_UTURN_INT_SW6A0",
"B_TERM_UTURN_INT_SW6A1",
"B_TERM_UTURN_INT_FAN_BOUNCE6",
"B_TERM_UTURN_INT_LV_L8",
"B_TERM_UTURN_INT_SW6C3",
"B_TERM_UTURN_INT_SW6B2",
"B_TERM_UTURN_INT_SS6B2",
"B_TERM_UTURN_INT_SS6BEG2",
"B_TERM_UTURN_INT_SS6BEG0",
"B_TERM_UTURN_INT_LVB3",
"B_TERM_UTURN_INT_SE6B3",
"B_TERM_UTURN_INT_SS2BEG3",
"B_TERM_UTURN_INT_SS2A0",
"B_TERM_UTURN_INT_LV3",
"B_TERM_UTURN_INT_SW6C1",
"B_TERM_UTURN_INT_LV7",
"B_TERM_UTURN_INT_SS6C0",
"B_TERM_UTURN_INT_LV_L5",
"B_TERM_UTURN_INT_SE6B0",
"B_TERM_UTURN_INT_SE2BEG1",
"B_TERM_UTURN_INT_SE6A3",
"B_TERM_UTURN_INT_SW6B1",
"B_TERM_UTURN_INT_SW6A3",
"B_TERM_UTURN_INT_SE2BEG0",
"B_TERM_UTURN_INT_SS6B1",
"B_TERM_UTURN_INT_SE6C2",
"B_TERM_UTURN_INT_SW6D2",
"B_TERM_UTURN_INT_SW2BEG1",
"B_TERM_UTURN_INT_SE6B2",
"B_TERM_UTURN_INT_SW6D1",
"B_TERM_UTURN_INT_SW6C0",
"B_TERM_UTURN_INT_ER1END_N3_3",
"B_TERM_UTURN_INT_SE6A2",
"B_TERM_UTURN_INT_LV_L4",
"B_TERM_UTURN_INT_SW2BEG3",
"B_TERM_UTURN_INT_SS6A3",
"B_TERM_UTURN_INT_SL1BEG0",
"B_TERM_UTURN_INT_SE6A1",
"B_TERM_UTURN_INT_LV4",
"B_TERM_UTURN_INT_SS2A2",
"B_TERM_UTURN_INT_SE6C1",
"B_TERM_UTURN_INT_SS2BEG1",
"B_TERM_UTURN_INT_LVB_L0",
"B_TERM_UTURN_INT_SS6A0",
"B_TERM_UTURN_INT_SE6D1",
"B_TERM_UTURN_INT_SE2BEG3",
"B_TERM_UTURN_INT_SL1BEG3",
"B_TERM_UTURN_INT_LV_L3",
"B_TERM_UTURN_INT_SW6B0",
"B_TERM_UTURN_INT_LV5",
"B_TERM_UTURN_INT_LVB4",
"B_TERM_UTURN_INT_WR1END0",
"B_TERM_UTURN_INT_LV_L6",
"B_TERM_UTURN_INT_LV_L18",
"B_TERM_UTURN_INT_SE2BEG2",
"B_TERM_UTURN_INT_SS2A3",
"B_TERM_UTURN_INT_SW6B3",
"B_TERM_UTURN_INT_SS6C1",
"B_TERM_UTURN_INT_WR1BEG0",
"B_TERM_UTURN_INT_SE6D0",
"B_TERM_UTURN_INT_SL1BEG2",
"B_TERM_UTURN_INT_FAN_BOUNCE0",
"B_TERM_UTURN_INT_SW6END_N0_3",
"B_TERM_UTURN_INT_SS6E1",
"B_TERM_UTURN_INT_SS6C2",
"B_TERM_UTURN_INT_SS6D3",
"B_TERM_UTURN_INT_LV6",
"B_TERM_UTURN_INT_SS2A1",
"B_TERM_UTURN_INT_SW6C2",
"B_TERM_UTURN_INT_LV18"
],
"pips": {}
}

11
kintex7/tile_type_BRKH_CLB.json Normal file
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{
"tile_type": "BRKH_CLB",
"sites": [],
"wires": [
"BRKH_CLB_COUT1_R",
"BRKH_CLB_COUT0_R",
"BRKH_CLB_COUT0_L",
"BRKH_CLB_COUT1_L"
],
"pips": {}
}

135
kintex7/tile_type_BRKH_CLK.json Normal file
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@ -0,0 +1,135 @@
{
"tile_type": "BRKH_CLK",
"sites": [],
"wires": [
"BRKH_CLK_CK_BUFG_CASC28",
"BRKH_CLK_R_CK_BUFG_CASC8",
"BRKH_CLK_R_CK_BUFG_CASC19",
"BRKH_CLK_CK_GCLK16",
"BRKH_CLK_CK_GCLK13",
"BRKH_CLK_R_CK_BUFG_CASC29",
"BRKH_CLK_R_CK_GCLK2",
"BRKH_CLK_R_CK_GCLK27",
"BRKH_CLK_CK_BUFG_CASC10",
"BRKH_CLK_CK_GCLK22",
"BRKH_CLK_R_CK_BUFG_CASC11",
"BRKH_CLK_R_CK_BUFG_CASC3",
"BRKH_CLK_CK_GCLK10",
"BRKH_CLK_R_CK_GCLK13",
"BRKH_CLK_CK_GCLK0",
"BRKH_CLK_CK_BUFG_CASC17",
"BRKH_CLK_R_CK_GCLK11",
"BRKH_CLK_CK_GCLK30",
"BRKH_CLK_CK_BUFG_CASC30",
"BRKH_CLK_CK_BUFG_CASC18",
"BRKH_CLK_CK_BUFG_CASC26",
"BRKH_CLK_R_CK_BUFG_CASC1",
"BRKH_CLK_CK_BUFG_CASC11",
"BRKH_CLK_CK_GCLK29",
"BRKH_CLK_CK_GCLK26",
"BRKH_CLK_CK_BUFG_CASC31",
"BRKH_CLK_R_CK_GCLK10",
"BRKH_CLK_R_CK_GCLK15",
"BRKH_CLK_CK_BUFG_CASC20",
"BRKH_CLK_R_CK_BUFG_CASC17",
"BRKH_CLK_R_CK_GCLK24",
"BRKH_CLK_R_CK_BUFG_CASC15",
"BRKH_CLK_R_CK_BUFG_CASC10",
"BRKH_CLK_R_CK_BUFG_CASC16",
"BRKH_CLK_CK_BUFG_CASC14",
"BRKH_CLK_CK_GCLK15",
"BRKH_CLK_CK_GCLK1",
"BRKH_CLK_R_CK_BUFG_CASC2",
"BRKH_CLK_R_CK_BUFG_CASC13",
"BRKH_CLK_CK_BUFG_CASC3",
"BRKH_CLK_R_CK_GCLK29",
"BRKH_CLK_CK_BUFG_CASC5",
"BRKH_CLK_CK_BUFG_CASC1",
"BRKH_CLK_R_CK_BUFG_CASC14",
"BRKH_CLK_R_CK_GCLK31",
"BRKH_CLK_R_CK_BUFG_CASC27",
"BRKH_CLK_R_CK_GCLK18",
"BRKH_CLK_R_CK_BUFG_CASC21",
"BRKH_CLK_CK_BUFG_CASC6",
"BRKH_CLK_CK_BUFG_CASC8",
"BRKH_CLK_R_CK_GCLK25",
"BRKH_CLK_CK_GCLK4",
"BRKH_CLK_CK_GCLK23",
"BRKH_CLK_CK_GCLK6",
"BRKH_CLK_CK_GCLK3",
"BRKH_CLK_R_CK_BUFG_CASC20",
"BRKH_CLK_CK_BUFG_CASC16",
"BRKH_CLK_R_CK_BUFG_CASC28",
"BRKH_CLK_R_CK_BUFG_CASC30",
"BRKH_CLK_CK_GCLK14",
"BRKH_CLK_R_CK_GCLK17",
"BRKH_CLK_CK_BUFG_CASC21",
"BRKH_CLK_CK_BUFG_CASC29",
"BRKH_CLK_CK_GCLK5",
"BRKH_CLK_R_CK_BUFG_CASC26",
"BRKH_CLK_R_CK_GCLK28",
"BRKH_CLK_R_CK_BUFG_CASC12",
"BRKH_CLK_CK_BUFG_CASC12",
"BRKH_CLK_CK_GCLK12",
"BRKH_CLK_R_CK_GCLK4",
"BRKH_CLK_R_CK_GCLK3",
"BRKH_CLK_CK_BUFG_CASC13",
"BRKH_CLK_CK_GCLK9",
"BRKH_CLK_R_CK_GCLK7",
"BRKH_CLK_CK_GCLK24",
"BRKH_CLK_CK_BUFG_CASC7",
"BRKH_CLK_CK_GCLK7",
"BRKH_CLK_CK_BUFG_CASC25",
"BRKH_CLK_R_CK_GCLK19",
"BRKH_CLK_R_CK_GCLK23",
"BRKH_CLK_R_CK_BUFG_CASC5",
"BRKH_CLK_R_CK_GCLK20",
"BRKH_CLK_R_CK_GCLK0",
"BRKH_CLK_R_CK_GCLK16",
"BRKH_CLK_R_CK_GCLK6",
"BRKH_CLK_CK_GCLK27",
"BRKH_CLK_R_CK_BUFG_CASC6",
"BRKH_CLK_R_CK_BUFG_CASC22",
"BRKH_CLK_CK_GCLK28",
"BRKH_CLK_CK_BUFG_CASC22",
"BRKH_CLK_R_CK_BUFG_CASC18",
"BRKH_CLK_R_CK_BUFG_CASC24",
"BRKH_CLK_R_CK_GCLK5",
"BRKH_CLK_R_CK_GCLK9",
"BRKH_CLK_R_CK_BUFG_CASC7",
"BRKH_CLK_CK_GCLK17",
"BRKH_CLK_CK_GCLK19",
"BRKH_CLK_CK_BUFG_CASC2",
"BRKH_CLK_CK_BUFG_CASC19",
"BRKH_CLK_CK_BUFG_CASC9",
"BRKH_CLK_CK_GCLK21",
"BRKH_CLK_CK_GCLK31",
"BRKH_CLK_CK_GCLK20",
"BRKH_CLK_R_CK_BUFG_CASC23",
"BRKH_CLK_CK_BUFG_CASC4",
"BRKH_CLK_CK_GCLK2",
"BRKH_CLK_R_CK_BUFG_CASC9",
"BRKH_CLK_R_CK_GCLK21",
"BRKH_CLK_R_CK_BUFG_CASC25",
"BRKH_CLK_R_CK_GCLK1",
"BRKH_CLK_R_CK_BUFG_CASC4",
"BRKH_CLK_CK_GCLK18",
"BRKH_CLK_R_CK_GCLK14",
"BRKH_CLK_CK_BUFG_CASC24",
"BRKH_CLK_CK_BUFG_CASC0",
"BRKH_CLK_R_CK_GCLK12",
"BRKH_CLK_CK_BUFG_CASC15",
"BRKH_CLK_R_CK_GCLK8",
"BRKH_CLK_CK_GCLK11",
"BRKH_CLK_CK_GCLK8",
"BRKH_CLK_R_CK_GCLK26",
"BRKH_CLK_CK_GCLK25",
"BRKH_CLK_R_CK_BUFG_CASC31",
"BRKH_CLK_CK_BUFG_CASC23",
"BRKH_CLK_R_CK_BUFG_CASC0",
"BRKH_CLK_R_CK_GCLK22",
"BRKH_CLK_CK_BUFG_CASC27",
"BRKH_CLK_R_CK_GCLK30"
],
"pips": {}
}

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kintex7/tile_type_BRKH_CMT.json Normal file
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{
"tile_type": "BRKH_CMT",
"sites": [],
"wires": [
"BRKH_CMT_FREQ_REF_NS3",
"BRKH_CMT_FREQ_REF_NS2",
"BRKH_CMT_PHYCTRL_SYNC_BB",
"BRKH_CMT_PHASEREF_BELOW1",
"BRKH_CMT_FREQ_REF_NS1",
"BRKH_CMT_FREQ_REF_NS0",
"BRKH_CMT_PHASEREF0",
"BRKH_CMT_PHASEREF1",
"BRKH_CMT_PHASEREF_BELOW0"
],
"pips": {}
}

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kintex7/tile_type_BRKH_DSP_L.json Normal file
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{
"tile_type": "BRKH_DSP_L",
"sites": [],
"wires": [
"BRKH_DSP_PCIN20",
"BRKH_DSP_ACIN7",
"BRKH_DSP_PCIN16",
"BRKH_DSP_PCIN3",
"BRKH_DSP_BCIN5",
"BRKH_DSP_PCIN25",
"BRKH_DSP_PCIN39",
"BRKH_DSP_PCIN30",
"BRKH_DSP_ACIN25",
"BRKH_DSP_PCIN6",
"BRKH_DSP_PCIN35",
"BRKH_DSP_BCIN14",
"BRKH_DSP_BCIN17",
"BRKH_DSP_PCIN14",
"BRKH_DSP_PCIN7",
"BRKH_DSP_BCIN3",
"BRKH_DSP_ACIN28",
"BRKH_DSP_BCIN8",
"BRKH_DSP_ACIN17",
"BRKH_DSP_BCIN15",
"BRKH_DSP_BCIN12",
"BRKH_DSP_ACIN20",
"BRKH_DSP_PCIN28",
"BRKH_DSP_ACIN1",
"BRKH_DSP_ACIN8",
"BRKH_DSP_PCIN40",
"BRKH_DSP_PCIN19",
"BRKH_DSP_BCIN13",
"BRKH_DSP_ACIN13",
"BRKH_DSP_BCIN0",
"BRKH_DSP_ACIN24",
"BRKH_DSP_PCIN46",
"BRKH_DSP_PCIN24",
"BRKH_DSP_PCIN21",
"BRKH_DSP_BCIN1",
"BRKH_DSP_PCIN23",
"BRKH_DSP_PCIN4",
"BRKH_DSP_BCIN16",
"BRKH_DSP_ACIN16",
"BRKH_DSP_BCIN6",
"BRKH_DSP_PCIN11",
"BRKH_DSP_PCIN8",
"BRKH_DSP_ACIN5",
"BRKH_DSP_ACIN11",
"BRKH_DSP_ACIN4",
"BRKH_DSP_ACIN26",
"BRKH_DSP_PCIN10",
"BRKH_DSP_ACIN29",
"BRKH_DSP_MULTSIGNIN",
"BRKH_DSP_PCIN12",
"BRKH_DSP_PCIN18",
"BRKH_DSP_PCIN15",
"BRKH_DSP_BCIN11",
"BRKH_DSP_PCIN17",
"BRKH_DSP_PCIN32",
"BRKH_DSP_PCIN37",
"BRKH_DSP_ACIN23",
"BRKH_DSP_PCIN13",
"BRKH_DSP_PCIN5",
"BRKH_DSP_ACIN10",
"BRKH_DSP_PCIN34",
"BRKH_DSP_ACIN14",
"BRKH_DSP_PCIN26",
"BRKH_DSP_PCIN0",
"BRKH_DSP_PCIN1",
"BRKH_DSP_ACIN2",
"BRKH_DSP_CARRYCASCIN",
"BRKH_DSP_PCIN33",
"BRKH_DSP_ACIN12",
"BRKH_DSP_ACIN3",
"BRKH_DSP_PCIN27",
"BRKH_DSP_BCIN7",
"BRKH_DSP_PCIN42",
"BRKH_DSP_PCIN31",
"BRKH_DSP_ACIN9",
"BRKH_DSP_ACIN27",
"BRKH_DSP_PCIN47",
"BRKH_DSP_PCIN41",
"BRKH_DSP_PCIN38",
"BRKH_DSP_BCIN10",
"BRKH_DSP_ACIN21",
"BRKH_DSP_ACIN15",
"BRKH_DSP_ACIN18",
"BRKH_DSP_ACIN22",
"BRKH_DSP_PCIN29",
"BRKH_DSP_BCIN9",
"BRKH_DSP_PCIN9",
"BRKH_DSP_PCIN43",
"BRKH_DSP_ACIN0",
"BRKH_DSP_PCIN44",
"BRKH_DSP_BCIN2",
"BRKH_DSP_PCIN45",
"BRKH_DSP_BCIN4",
"BRKH_DSP_PCIN22",
"BRKH_DSP_ACIN19",
"BRKH_DSP_ACIN6",
"BRKH_DSP_PCIN2",
"BRKH_DSP_PCIN36"
],
"pips": {}
}

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kintex7/tile_type_BRKH_DSP_R.json Normal file
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{
"tile_type": "BRKH_DSP_R",
"sites": [],
"wires": [
"BRKH_DSP_PCIN20",
"BRKH_DSP_ACIN7",
"BRKH_DSP_PCIN16",
"BRKH_DSP_PCIN3",
"BRKH_DSP_BCIN5",
"BRKH_DSP_PCIN25",
"BRKH_DSP_PCIN39",
"BRKH_DSP_PCIN30",
"BRKH_DSP_ACIN25",
"BRKH_DSP_PCIN6",
"BRKH_DSP_PCIN35",
"BRKH_DSP_BCIN14",
"BRKH_DSP_BCIN17",
"BRKH_DSP_PCIN14",
"BRKH_DSP_PCIN7",
"BRKH_DSP_BCIN3",
"BRKH_DSP_ACIN28",
"BRKH_DSP_BCIN8",
"BRKH_DSP_ACIN17",
"BRKH_DSP_BCIN15",
"BRKH_DSP_BCIN12",
"BRKH_DSP_ACIN20",
"BRKH_DSP_PCIN28",
"BRKH_DSP_ACIN1",
"BRKH_DSP_ACIN8",
"BRKH_DSP_PCIN40",
"BRKH_DSP_PCIN19",
"BRKH_DSP_BCIN13",
"BRKH_DSP_ACIN13",
"BRKH_DSP_BCIN0",
"BRKH_DSP_ACIN24",
"BRKH_DSP_PCIN46",
"BRKH_DSP_PCIN24",
"BRKH_DSP_PCIN21",
"BRKH_DSP_BCIN1",
"BRKH_DSP_PCIN23",
"BRKH_DSP_PCIN4",
"BRKH_DSP_BCIN16",
"BRKH_DSP_ACIN16",
"BRKH_DSP_BCIN6",
"BRKH_DSP_PCIN11",
"BRKH_DSP_PCIN8",
"BRKH_DSP_ACIN5",
"BRKH_DSP_ACIN11",
"BRKH_DSP_ACIN4",
"BRKH_DSP_ACIN26",
"BRKH_DSP_PCIN10",
"BRKH_DSP_ACIN29",
"BRKH_DSP_MULTSIGNIN",
"BRKH_DSP_PCIN12",
"BRKH_DSP_PCIN18",
"BRKH_DSP_PCIN15",
"BRKH_DSP_BCIN11",
"BRKH_DSP_PCIN17",
"BRKH_DSP_PCIN32",
"BRKH_DSP_PCIN37",
"BRKH_DSP_ACIN23",
"BRKH_DSP_PCIN13",
"BRKH_DSP_PCIN5",
"BRKH_DSP_ACIN10",
"BRKH_DSP_PCIN34",
"BRKH_DSP_ACIN14",
"BRKH_DSP_PCIN26",
"BRKH_DSP_PCIN0",
"BRKH_DSP_PCIN1",
"BRKH_DSP_ACIN2",
"BRKH_DSP_CARRYCASCIN",
"BRKH_DSP_PCIN33",
"BRKH_DSP_ACIN12",
"BRKH_DSP_ACIN3",
"BRKH_DSP_PCIN27",
"BRKH_DSP_BCIN7",
"BRKH_DSP_PCIN42",
"BRKH_DSP_PCIN31",
"BRKH_DSP_ACIN9",
"BRKH_DSP_ACIN27",
"BRKH_DSP_PCIN47",
"BRKH_DSP_PCIN41",
"BRKH_DSP_PCIN38",
"BRKH_DSP_BCIN10",
"BRKH_DSP_ACIN21",
"BRKH_DSP_ACIN15",
"BRKH_DSP_ACIN18",
"BRKH_DSP_ACIN22",
"BRKH_DSP_PCIN29",
"BRKH_DSP_BCIN9",
"BRKH_DSP_PCIN9",
"BRKH_DSP_PCIN43",
"BRKH_DSP_ACIN0",
"BRKH_DSP_PCIN44",
"BRKH_DSP_BCIN2",
"BRKH_DSP_PCIN45",
"BRKH_DSP_BCIN4",
"BRKH_DSP_PCIN22",
"BRKH_DSP_ACIN19",
"BRKH_DSP_ACIN6",
"BRKH_DSP_PCIN2",
"BRKH_DSP_PCIN36"
],
"pips": {}
}

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kintex7/tile_type_BRKH_GTX.json Normal file
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{
"tile_type": "BRKH_GTX",
"sites": [],
"wires": [
"BRKH_GTX_NORTHREFCLK0_UPPER",
"BRKH_GTX_REFCLK0_LOWER",
"BRKH_GTX_REFCLK1_LOWER",
"BRKH_GTX_NORTHREFCLK0_LOWER",
"BRKH_GTX_SOUTHREFCLK1_UPPER",
"BRKH_GTX_SOUTHREFCLK0_LOWER",
"BRKH_GTX_NORTHREFCLK1_LOWER",
"BRKH_GTX_REFCLK0_UPPER",
"BRKH_GTX_NORTHREFCLK1_UPPER",
"BRKH_GTX_SOUTHREFCLK1_LOWER",
"BRKH_GTX_REFCLK1_UPPER",
"BRKH_GTX_SOUTHREFCLK0_UPPER"
],
"pips": {
"BRKH_GTX.BRKH_GTX_REFCLK1_LOWER->BRKH_GTX_NORTHREFCLK0_UPPER": {
"src_wire": "BRKH_GTX_REFCLK1_LOWER",
"is_pseudo": "0",
"dst_wire": "BRKH_GTX_NORTHREFCLK0_UPPER",
"is_directional": "1",
"can_invert": "0"
},
"BRKH_GTX.BRKH_GTX_REFCLK0_UPPER->BRKH_GTX_SOUTHREFCLK1_LOWER": {
"src_wire": "BRKH_GTX_REFCLK0_UPPER",
"is_pseudo": "0",
"dst_wire": "BRKH_GTX_SOUTHREFCLK1_LOWER",
"is_directional": "1",
"can_invert": "0"
},
"BRKH_GTX.BRKH_GTX_SOUTHREFCLK0_UPPER->BRKH_GTX_SOUTHREFCLK0_LOWER": {
"src_wire": "BRKH_GTX_SOUTHREFCLK0_UPPER",
"is_pseudo": "0",
"dst_wire": "BRKH_GTX_SOUTHREFCLK0_LOWER",
"is_directional": "1",
"can_invert": "0"
},
"BRKH_GTX.BRKH_GTX_SOUTHREFCLK1_UPPER->BRKH_GTX_SOUTHREFCLK1_LOWER": {
"src_wire": "BRKH_GTX_SOUTHREFCLK1_UPPER",
"is_pseudo": "0",
"dst_wire": "BRKH_GTX_SOUTHREFCLK1_LOWER",
"is_directional": "1",
"can_invert": "0"
},
"BRKH_GTX.BRKH_GTX_REFCLK1_UPPER->BRKH_GTX_SOUTHREFCLK0_LOWER": {
"src_wire": "BRKH_GTX_REFCLK1_UPPER",
"is_pseudo": "0",
"dst_wire": "BRKH_GTX_SOUTHREFCLK0_LOWER",
"is_directional": "1",
"can_invert": "0"
},
"BRKH_GTX.BRKH_GTX_NORTHREFCLK0_LOWER->BRKH_GTX_NORTHREFCLK0_UPPER": {
"src_wire": "BRKH_GTX_NORTHREFCLK0_LOWER",
"is_pseudo": "0",
"dst_wire": "BRKH_GTX_NORTHREFCLK0_UPPER",
"is_directional": "1",
"can_invert": "0"
},
"BRKH_GTX.BRKH_GTX_NORTHREFCLK1_LOWER->BRKH_GTX_NORTHREFCLK1_UPPER": {
"src_wire": "BRKH_GTX_NORTHREFCLK1_LOWER",
"is_pseudo": "0",
"dst_wire": "BRKH_GTX_NORTHREFCLK1_UPPER",
"is_directional": "1",
"can_invert": "0"
},
"BRKH_GTX.BRKH_GTX_REFCLK0_LOWER->BRKH_GTX_NORTHREFCLK0_UPPER": {
"src_wire": "BRKH_GTX_REFCLK0_LOWER",
"is_pseudo": "0",
"dst_wire": "BRKH_GTX_NORTHREFCLK0_UPPER",
"is_directional": "1",
"can_invert": "0"
},
"BRKH_GTX.BRKH_GTX_REFCLK0_LOWER->BRKH_GTX_NORTHREFCLK1_UPPER": {
"src_wire": "BRKH_GTX_REFCLK0_LOWER",
"is_pseudo": "0",
"dst_wire": "BRKH_GTX_NORTHREFCLK1_UPPER",
"is_directional": "1",
"can_invert": "0"
},
"BRKH_GTX.BRKH_GTX_REFCLK1_LOWER->BRKH_GTX_NORTHREFCLK1_UPPER": {
"src_wire": "BRKH_GTX_REFCLK1_LOWER",
"is_pseudo": "0",
"dst_wire": "BRKH_GTX_NORTHREFCLK1_UPPER",
"is_directional": "1",
"can_invert": "0"
},
"BRKH_GTX.BRKH_GTX_REFCLK1_UPPER->BRKH_GTX_SOUTHREFCLK1_LOWER": {
"src_wire": "BRKH_GTX_REFCLK1_UPPER",
"is_pseudo": "0",
"dst_wire": "BRKH_GTX_SOUTHREFCLK1_LOWER",
"is_directional": "1",
"can_invert": "0"
},
"BRKH_GTX.BRKH_GTX_REFCLK0_UPPER->BRKH_GTX_SOUTHREFCLK0_LOWER": {
"src_wire": "BRKH_GTX_REFCLK0_UPPER",
"is_pseudo": "0",
"dst_wire": "BRKH_GTX_SOUTHREFCLK0_LOWER",
"is_directional": "1",
"can_invert": "0"
}
}
}

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{
"tile_type": "BRKH_INT",
"sites": [],
"wires": [
"BRKH_INT_LV14",
"BRKH_INT_NR1BEG1",
"BRKH_INT_SE2A3",
"BRKH_INT_NE6B0",
"BRKH_INT_L_LV0",
"BRKH_INT_NE6C0",
"BRKH_INT_SS6E2",
"BRKH_INT_NE6A3",
"BRKH_INT_SS6END3",
"BRKH_INT_LVB11",
"BRKH_INT_NE2BEG0",
"BRKH_INT_NE2END_S3_0",
"BRKH_INT_SW6E0",
"BRKH_INT_SW6E3",
"BRKH_INT_SW6C1",
"BRKH_INT_L_LV2",
"BRKH_INT_SS6D3",
"BRKH_INT_SE6E0",
"BRKH_INT_LVB5",
"BRKH_INT_LV15",
"BRKH_INT_NL1BEG0",
"BRKH_INT_NN6BEG2",
"BRKH_INT_SS2END_N0_3",
"BRKH_INT_SW6E1",
"BRKH_INT_FAN_BOUNCE_S3_0",
"BRKH_INT_NL1BEG1",
"BRKH_INT_LVB2",
"BRKH_INT_L_LV7",
"BRKH_INT_SW2A2",
"BRKH_INT_WL1BEG3",
"BRKH_INT_NW2BEG2",
"BRKH_INT_SE6B2",
"BRKH_INT_NW6END_S0_0",
"BRKH_INT_SE6B3",
"BRKH_INT_SS6D1",
"BRKH_INT_NE6A0",
"BRKH_INT_ER1BEG_S0",
"BRKH_INT_NW6A1",
"BRKH_INT_NN6E3",
"BRKH_INT_NR1BEG1_SLOW",
"BRKH_INT_LV3",
"BRKH_INT_WW4END_S0_0",
"BRKH_INT_WL1END3",
"BRKH_INT_NN6B0",
"BRKH_INT_WW2END3",
"BRKH_INT_NN6C3",
"BRKH_INT_SR1END3",
"BRKH_INT_LVB4",
"BRKH_INT_LV9",
"BRKH_INT_SS6E3",
"BRKH_INT_NN6BEG0",
"BRKH_INT_SW6D0",
"BRKH_INT_NW6B0",
"BRKH_INT_SS6C0",
"BRKH_INT_LV12",
"BRKH_INT_LVB_L7",
"BRKH_INT_L_LV10",
"BRKH_INT_NN6D0",
"BRKH_INT_SS6B3",
"BRKH_INT_NN2BEG2",
"BRKH_INT_L_LV13",
"BRKH_INT_NW6B1",
"BRKH_INT_SS6C1",
"BRKH_INT_NE2BEG1",
"BRKH_INT_NE2BEG2",
"BRKH_INT_SS2A0",
"BRKH_INT_NR1BEG0_SLOW",
"BRKH_INT_SW6D3",
"BRKH_INT_NW6C1",
"BRKH_INT_LVB_L3",
"BRKH_INT_NN6D1",
"BRKH_INT_NL1BEG2",
"BRKH_INT_LVB9",
"BRKH_INT_NW6A0",
"BRKH_INT_EL1BEG3",
"BRKH_INT_SS2END0",
"BRKH_INT_NN2A0",
"BRKH_INT_NW6D0",
"BRKH_INT_SS2END1",
"BRKH_INT_NW6A2",
"BRKH_INT_SS6A2",
"BRKH_INT_SS2A3",
"BRKH_INT_L_LV3",
"BRKH_INT_SE2A0",
"BRKH_INT_SS2END2",
"BRKH_INT_SE6C3",
"BRKH_INT_LVB_L11",
"BRKH_INT_NN6BEG1",
"BRKH_INT_LVB_L2",
"BRKH_INT_L_LV5",
"BRKH_INT_SE6B1",
"BRKH_INT_SW2A1",
"BRKH_INT_SE6C2",
"BRKH_INT_BYP_BOUNCE6",
"BRKH_INT_L_LV14",
"BRKH_INT_SE6D2",
"BRKH_INT_NR1BEG0",
"BRKH_INT_NN6D2",
"BRKH_INT_NW6A3",
"BRKH_INT_L_LV15",
"BRKH_INT_NE6C3",
"BRKH_INT_SE6C1",
"BRKH_INT_LV10",
"BRKH_INT_LV11",
"BRKH_INT_SR1END1",
"BRKH_INT_NN6E1",
"BRKH_INT_SS6C3",
"BRKH_INT_SS6END0",
"BRKH_INT_LVB7",
"BRKH_INT_LVB8",
"BRKH_INT_LVB_L9",
"BRKH_INT_SE6C0",
"BRKH_INT_NN2BEG0",
"BRKH_INT_NR1BEG2_SLOW",
"BRKH_INT_SW2END3",
"BRKH_INT_SS6B1",
"BRKH_INT_NL1BEG2_SLOW",
"BRKH_INT_EL1END_S3_0",
"BRKH_INT_NE2BEG3",
"BRKH_INT_NE6A2",
"BRKH_INT_LVB_L6",
"BRKH_INT_L_LV16",
"BRKH_INT_NN2BEG3",
"BRKH_INT_L_LV9",
"BRKH_INT_LVB3",
"BRKH_INT_NN6A3",
"BRKH_INT_L_LV8",
"BRKH_INT_NL1BEG1_SLOW",
"BRKH_INT_SR1END2_SLOW",
"BRKH_INT_SS6C2",
"BRKH_INT_LVB_L4",
"BRKH_INT_LV13",
"BRKH_INT_SR1END3_SLOW",
"BRKH_INT_SW2A3",
"BRKH_INT_NN6B1",
"BRKH_INT_SE6E3",
"BRKH_INT_LV5",
"BRKH_INT_SE2A1",
"BRKH_INT_L_LV17",
"BRKH_INT_LV16",
"BRKH_INT_NE6B2",
"BRKH_INT_FAN_BOUNCE_S3_4",
"BRKH_INT_SW2A0",
"BRKH_INT_SS6A1",
"BRKH_INT_SW6C2",
"BRKH_INT_LV0",
"BRKH_INT_LV7",
"BRKH_INT_LVB_L12",
"BRKH_INT_SR1END1_SLOW",
"BRKH_INT_SR1END_N3_3",
"BRKH_INT_NL1BEG0_SLOW",
"BRKH_INT_L_LV4",
"BRKH_INT_SE6D3",
"BRKH_INT_SW6B0",
"BRKH_INT_BYP_BOUNCE2",
"BRKH_INT_NN2BEG1",
"BRKH_INT_SS6B0",
"BRKH_INT_SS6D2",
"BRKH_INT_ER1END3",
"BRKH_INT_SL1END3",
"BRKH_INT_NW6D3",
"BRKH_INT_SL1END3_SLOW",
"BRKH_INT_SW6C0",
"BRKH_INT_NW6D2",
"BRKH_INT_SL1END1_SLOW",
"BRKH_INT_NN6A1",
"BRKH_INT_NE6D3",
"BRKH_INT_LVB10",
"BRKH_INT_FAN_BOUNCE_S3_2",
"BRKH_INT_SR1END2",
"BRKH_INT_SS6D0",
"BRKH_INT_LVB1",
"BRKH_INT_NE6A1",
"BRKH_INT_SS6A0",
"BRKH_INT_NN6C1",
"BRKH_INT_NN6E2",
"BRKH_INT_SL1END2_SLOW",
"BRKH_INT_SE6D0",
"BRKH_INT_SE6B0",
"BRKH_INT_LVB_L5",
"BRKH_INT_SS2END3",
"BRKH_INT_NW6B2",
"BRKH_INT_NR1BEG3_SLOW",
"BRKH_INT_SW6B2",
"BRKH_INT_LVB6",
"BRKH_INT_SS2A1",
"BRKH_INT_LV17",
"BRKH_INT_BYP_BOUNCE7",
"BRKH_INT_NN2END_S2_0",
"BRKH_INT_LV6",
"BRKH_INT_NN6B2",
"BRKH_INT_LVB_L8",
"BRKH_INT_SW6B3",
"BRKH_INT_NN6E0",
"BRKH_INT_NE6D1",
"BRKH_INT_FAN_BOUNCE_S3_6",
"BRKH_INT_NW6D1",
"BRKH_INT_LV4",
"BRKH_INT_NW6C0",
"BRKH_INT_SW6B1",
"BRKH_INT_NE6D2",
"BRKH_INT_LVB12",
"BRKH_INT_SW6E2",
"BRKH_INT_NN6A2",
"BRKH_INT_NN6BEG3",
"BRKH_INT_SE6E2",
"BRKH_INT_NN6END_S1_0",
"BRKH_INT_NW6C3",
"BRKH_INT_WR1END_S1_0",
"BRKH_INT_SW6C3",
"BRKH_INT_NL1END_S3_0",
"BRKH_INT_NN2A1",
"BRKH_INT_NN6A0",
"BRKH_INT_LVB_L10",
"BRKH_INT_NE6C2",
"BRKH_INT_SS2A2",
"BRKH_INT_NN6C0",
"BRKH_INT_NW2BEG1",
"BRKH_INT_NW2BEG0",
"BRKH_INT_SS6B2",
"BRKH_INT_SW6END3",
"BRKH_INT_SS6END1",
"BRKH_INT_NE6D0",
"BRKH_INT_NW2END_S0_0",
"BRKH_INT_SS6END_N0_3",
"BRKH_INT_NW2BEG3",
"BRKH_INT_SS6E1",
"BRKH_INT_LV8",
"BRKH_INT_SL1END2",
"BRKH_INT_SS6END2",
"BRKH_INT_SL1END0",
"BRKH_INT_NE6B3",
"BRKH_INT_NE6B1",
"BRKH_INT_WR1BEG_S0",
"BRKH_INT_NN6B3",
"BRKH_INT_NW6C2",
"BRKH_INT_SE6D1",
"BRKH_INT_NW6B3",
"BRKH_INT_LVB_L1",
"BRKH_INT_NN2A3",
"BRKH_INT_NN2A2",
"BRKH_INT_L_LV1",
"BRKH_INT_SL1END1",
"BRKH_INT_L_LV12",
"BRKH_INT_NE6C1",
"BRKH_INT_NR1BEG2",
"BRKH_INT_SE6E1",
"BRKH_INT_SE2A2",
"BRKH_INT_SS6A3",
"BRKH_INT_LV2",
"BRKH_INT_NR1BEG3",
"BRKH_INT_SS6E0",
"BRKH_INT_SW6D1",
"BRKH_INT_LV1",
"BRKH_INT_SL1END0_SLOW",
"BRKH_INT_NN6D3",
"BRKH_INT_SW6D2",
"BRKH_INT_NN6C2",
"BRKH_INT_L_LV6",
"BRKH_INT_BYP_BOUNCE3",
"BRKH_INT_L_LV11"
],
"pips": {
"BRKH_INT.BRKH_INT_SR1END1_SLOW->>BRKH_INT_SR1END1": {
"src_wire": "BRKH_INT_SR1END1_SLOW",
"is_pseudo": "0",
"dst_wire": "BRKH_INT_SR1END1",
"is_directional": "1",
"can_invert": "0"
},
"BRKH_INT.BRKH_INT_SR1END3_SLOW->>BRKH_INT_SR1END3": {
"src_wire": "BRKH_INT_SR1END3_SLOW",
"is_pseudo": "0",
"dst_wire": "BRKH_INT_SR1END3",
"is_directional": "1",
"can_invert": "0"
},
"BRKH_INT.BRKH_INT_NL1BEG1->>BRKH_INT_NL1BEG1_SLOW": {
"src_wire": "BRKH_INT_NL1BEG1",
"is_pseudo": "0",
"dst_wire": "BRKH_INT_NL1BEG1_SLOW",
"is_directional": "1",
"can_invert": "0"
},
"BRKH_INT.BRKH_INT_SL1END1_SLOW->>BRKH_INT_SL1END1": {
"src_wire": "BRKH_INT_SL1END1_SLOW",
"is_pseudo": "0",
"dst_wire": "BRKH_INT_SL1END1",
"is_directional": "1",
"can_invert": "0"
},
"BRKH_INT.BRKH_INT_NR1BEG3->>BRKH_INT_NR1BEG3_SLOW": {
"src_wire": "BRKH_INT_NR1BEG3",
"is_pseudo": "0",
"dst_wire": "BRKH_INT_NR1BEG3_SLOW",
"is_directional": "1",
"can_invert": "0"
},
"BRKH_INT.BRKH_INT_SL1END3_SLOW->>BRKH_INT_SL1END3": {
"src_wire": "BRKH_INT_SL1END3_SLOW",
"is_pseudo": "0",
"dst_wire": "BRKH_INT_SL1END3",
"is_directional": "1",
"can_invert": "0"
},
"BRKH_INT.BRKH_INT_NR1BEG2->>BRKH_INT_NR1BEG2_SLOW": {
"src_wire": "BRKH_INT_NR1BEG2",
"is_pseudo": "0",
"dst_wire": "BRKH_INT_NR1BEG2_SLOW",
"is_directional": "1",
"can_invert": "0"
},
"BRKH_INT.BRKH_INT_SL1END0_SLOW->>BRKH_INT_SL1END0": {
"src_wire": "BRKH_INT_SL1END0_SLOW",
"is_pseudo": "0",
"dst_wire": "BRKH_INT_SL1END0",
"is_directional": "1",
"can_invert": "0"
},
"BRKH_INT.BRKH_INT_SL1END2_SLOW->>BRKH_INT_SL1END2": {
"src_wire": "BRKH_INT_SL1END2_SLOW",
"is_pseudo": "0",
"dst_wire": "BRKH_INT_SL1END2",
"is_directional": "1",
"can_invert": "0"
},
"BRKH_INT.BRKH_INT_NR1BEG0->>BRKH_INT_NR1BEG0_SLOW": {
"src_wire": "BRKH_INT_NR1BEG0",
"is_pseudo": "0",
"dst_wire": "BRKH_INT_NR1BEG0_SLOW",
"is_directional": "1",
"can_invert": "0"
},
"BRKH_INT.BRKH_INT_NL1BEG2->>BRKH_INT_NL1BEG2_SLOW": {
"src_wire": "BRKH_INT_NL1BEG2",
"is_pseudo": "0",
"dst_wire": "BRKH_INT_NL1BEG2_SLOW",
"is_directional": "1",
"can_invert": "0"
},
"BRKH_INT.BRKH_INT_NL1BEG0->>BRKH_INT_NL1BEG0_SLOW": {
"src_wire": "BRKH_INT_NL1BEG0",
"is_pseudo": "0",
"dst_wire": "BRKH_INT_NL1BEG0_SLOW",
"is_directional": "1",
"can_invert": "0"
},
"BRKH_INT.BRKH_INT_SR1END2_SLOW->>BRKH_INT_SR1END2": {
"src_wire": "BRKH_INT_SR1END2_SLOW",
"is_pseudo": "0",
"dst_wire": "BRKH_INT_SR1END2",
"is_directional": "1",
"can_invert": "0"
},
"BRKH_INT.BRKH_INT_NR1BEG1->>BRKH_INT_NR1BEG1_SLOW": {
"src_wire": "BRKH_INT_NR1BEG1",
"is_pseudo": "0",
"dst_wire": "BRKH_INT_NR1BEG1_SLOW",
"is_directional": "1",
"can_invert": "0"
}
}
}

124
kintex7/tile_type_BRKH_TERM_INT.json Normal file
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@ -0,0 +1,124 @@
{
"tile_type": "BRKH_TERM_INT",
"sites": [],
"wires": [
"T_TERM_UTURN_INT_SE6D1",
"T_TERM_UTURN_INT_SW6E2",
"T_TERM_INT_UTURN_LV_R7",
"T_TERM_UTURN_INT_SW6C0",
"T_TERM_UTURN_INT_SW6D1",
"T_TERM_UTURN_INT_LV_L3",
"T_TERM_UTURN_INT_SW6E3",
"T_TERM_INT_UTURN_LV_R17",
"T_TERM_UTURN_INT_SS6A3",
"T_TERM_UTURN_INT_SE6E2",
"T_TERM_UTURN_INT_FAN_BOUNCE_S3_2",
"T_TERM_UTURN_INT_SS2END3",
"T_TERM_UTURN_INT_SS6A0",
"T_TERM_UTURN_INT_LVB2",
"T_TERM_UTURN_INT_SE6B3",
"T_TERM_UTURN_INT_SS6E2",
"T_TERM_UTURN_INT_SW2A1",
"T_TERM_UTURN_INT_LVB1",
"T_TERM_UTURN_INT_SS2A1",
"T_TERM_UTURN_INT_SS6E3",
"T_TERM_UTURN_INT_SS6END3",
"T_TERM_UTURN_INT_SW6C3",
"T_TERM_UTURN_INT_SE6E0",
"T_TERM_UTURN_INT_FAN_BOUNCE_S3_4",
"T_TERM_UTURN_INT_SS6D3",
"T_TERM_UTURN_INT_SW2A0",
"T_TERM_UTURN_INT_SE6B1",
"T_TERM_UTURN_INT_SS6END0",
"T_TERM_UTURN_INT_SL1END0_SLOW",
"T_TERM_UTURN_INT_SE6B0",
"T_TERM_UTURN_INT_LV_L5",
"T_TERM_UTURN_INT_LV_L17",
"T_TERM_UTURN_INT_SS6D1",
"T_TERM_UTURN_INT_SE2A2",
"T_TERM_UTURN_INT_SE6C1",
"T_TERM_UTURN_INT_LV_L6",
"T_TERM_UTURN_INT_SS6C3",
"T_TERM_UTURN_INT_SW6C2",
"T_TERM_UTURN_INT_SR1END1_SLOW",
"T_TERM_UTURN_INT_SE2A3",
"T_TERM_UTURN_INT_SS2END0",
"T_TERM_UTURN_INT_SL1END1_SLOW",
"T_TERM_UTURN_INT_SW6D0",
"T_TERM_UTURN_INT_LVB_L4",
"T_TERM_UTURN_INT_SW6E0",
"T_TERM_UTURN_INT_SW2A3",
"T_TERM_UTURN_INT_LV_L16",
"T_TERM_UTURN_INT_LV_L9",
"T_TERM_UTURN_INT_SE6D2",
"T_TERM_UTURN_INT_SS2A0",
"T_TERM_UTURN_INT_SE6C0",
"T_TERM_UTURN_INT_SS2END2",
"T_TERM_UTURN_INT_LVB3",
"T_TERM_UTURN_INT_SL1END2_SLOW",
"T_TERM_UTURN_INT_SS6D0",
"T_TERM_UTURN_INT_SE2A0",
"T_TERM_UTURN_INT_SS6E1",
"T_TERM_UTURN_INT_SR1END2_SLOW",
"T_TERM_UTURN_INT_SE6E3",
"T_TERM_UTURN_INT_ER1BEG_S0",
"T_TERM_UTURN_INT_LVB4",
"T_TERM_UTURN_INT_SE6D3",
"T_TERM_UTURN_INT_SS6END2",
"T_TERM_UTURN_INT_LV_L7",
"T_TERM_UTURN_INT_SS6B2",
"T_TERM_UTURN_INT_LVB_L5",
"T_TERM_UTURN_INT_SS6B3",
"T_TERM_UTURN_INT_LVB5",
"T_TERM_UTURN_INT_SW6D3",
"T_TERM_INT_UTURN_LV_R5",
"T_TERM_UTURN_INT_SS6C0",
"T_TERM_UTURN_INT_SS2END1",
"T_TERM_UTURN_INT_SS6B0",
"T_TERM_INT_UTURN_LV_R16",
"T_TERM_UTURN_INT_SS2A3",
"T_TERM_UTURN_INT_SW6B1",
"T_TERM_UTURN_INT_SW6B2",
"T_TERM_INT_UTURN_LV_R3",
"T_TERM_UTURN_INT_SW6E1",
"T_TERM_INT_UTURN_LV_R6",
"T_TERM_UTURN_INT_SE6C2",
"T_TERM_UTURN_INT_SL1END3_SLOW",
"T_TERM_UTURN_INT_LVB_L0",
"T_TERM_INT_UTURN_LV_R4",
"T_TERM_UTURN_INT_SS6E0",
"T_TERM_UTURN_INT_FAN_BOUNCE_S3_0",
"T_TERM_UTURN_INT_WR1END_S1_0",
"T_TERM_UTURN_INT_ER1END3",
"T_TERM_UTURN_INT_SS6A1",
"T_TERM_UTURN_INT_SS6B1",
"T_TERM_UTURN_INT_SS6A2",
"T_TERM_UTURN_INT_SS6D2",
"T_TERM_UTURN_INT_SW2A2",
"T_TERM_UTURN_INT_LVB_L2",
"T_TERM_UTURN_INT_SE6D0",
"T_TERM_UTURN_INT_SW6B3",
"T_TERM_INT_UTURN_LV_R9",
"T_TERM_INT_UTURN_LV_R2",
"T_TERM_UTURN_INT_SE6E1",
"T_TERM_UTURN_INT_SW6D2",
"T_TERM_UTURN_INT_SS2A2",
"T_TERM_UTURN_INT_LV_L2",
"T_TERM_UTURN_INT_SE2A1",
"T_TERM_UTURN_INT_SS6C1",
"T_TERM_UTURN_INT_SS6END1",
"T_TERM_UTURN_INT_LV_L4",
"T_TERM_UTURN_INT_WR1BEG_S0",
"T_TERM_UTURN_INT_SE6B2",
"T_TERM_UTURN_INT_SE6C3",
"T_TERM_UTURN_INT_SS6C2",
"T_TERM_UTURN_INT_LVB0",
"T_TERM_UTURN_INT_FAN_BOUNCE_S3_6",
"T_TERM_UTURN_INT_SR1END3_SLOW",
"T_TERM_UTURN_INT_LVB_L3",
"T_TERM_UTURN_INT_SW6B0",
"T_TERM_UTURN_INT_LVB_L1",
"T_TERM_UTURN_INT_SW6C1"
],
"pips": {}
}

125
kintex7/tile_type_B_TERM_INT.json Normal file
View File

@ -0,0 +1,125 @@
{
"tile_type": "B_TERM_INT",
"sites": [],
"wires": [
"B_TERM_UTURN_INT_SW6D0",
"B_TERM_UTURN_INT_SS6A1",
"B_TERM_UTURN_INT_LVB5",
"B_TERM_UTURN_INT_SS2BEG2",
"B_TERM_UTURN_INT_LV8",
"B_TERM_UTURN_INT_SW2BEG2",
"B_TERM_UTURN_INT_SS6E0",
"B_TERM_UTURN_INT_SE6A0",
"B_TERM_UTURN_INT_SS6B3",
"B_TERM_UTURN_INT_FAN_BOUNCE4",
"B_TERM_UTURN_INT_SS6A2",
"B_TERM_UTURN_INT_LV9",
"B_TERM_UTURN_INT_SR1BEG3",
"B_TERM_UTURN_INT_LV_L2",
"B_TERM_UTURN_INT_SS6BEG3",
"B_TERM_UTURN_INT_LVB_L4",
"B_TERM_UTURN_INT_SW6A2",
"B_TERM_UTURN_INT_SE6C0",
"B_TERM_UTURN_INT_LVB_L5",
"B_TERM_UTURN_INT_ER1BEG0",
"B_TERM_UTURN_INT_LVB1",
"B_TERM_UTURN_INT_LVB_L3",
"B_TERM_UTURN_INT_SE6C3",
"B_TERM_UTURN_INT_SS6C3",
"B_TERM_UTURN_INT_FAN_BOUNCE2",
"B_TERM_UTURN_INT_LV_L9",
"B_TERM_UTURN_INT_SS6D0",
"B_TERM_UTURN_INT_LV2",
"B_TERM_UTURN_INT_LVB_L1",
"B_TERM_UTURN_INT_SS6E2",
"B_TERM_UTURN_INT_SE6D3",
"B_TERM_UTURN_INT_SW6D3",
"B_TERM_UTURN_INT_LVB0",
"B_TERM_UTURN_INT_SS2BEG0",
"B_TERM_UTURN_INT_SS6D2",
"B_TERM_UTURN_INT_SR1BEG1",
"B_TERM_UTURN_INT_SS6E3",
"B_TERM_UTURN_INT_SW2BEG0",
"B_TERM_UTURN_INT_SS6D1",
"B_TERM_UTURN_INT_LVB2",
"B_TERM_UTURN_INT_SS6BEG1",
"B_TERM_UTURN_INT_SE6D2",
"B_TERM_UTURN_INT_SR1BEG2",
"B_TERM_UTURN_INT_SL1BEG1",
"B_TERM_UTURN_INT_SE6B1",
"B_TERM_UTURN_INT_LV_L7",
"B_TERM_UTURN_INT_LVB_L2",
"B_TERM_UTURN_INT_SW6A0",
"B_TERM_UTURN_INT_SW6A1",
"B_TERM_UTURN_INT_FAN_BOUNCE6",
"B_TERM_UTURN_INT_LV_L8",
"B_TERM_UTURN_INT_SW6C3",
"B_TERM_UTURN_INT_SW6B2",
"B_TERM_UTURN_INT_SS6B2",
"B_TERM_UTURN_INT_SS6BEG2",
"B_TERM_UTURN_INT_SS6BEG0",
"B_TERM_UTURN_INT_LVB3",
"B_TERM_UTURN_INT_SE6B3",
"B_TERM_UTURN_INT_SS2BEG3",
"B_TERM_UTURN_INT_SS2A0",
"B_TERM_UTURN_INT_LV3",
"B_TERM_UTURN_INT_SW6C1",
"B_TERM_UTURN_INT_LV7",
"B_TERM_UTURN_INT_SS6C0",
"B_TERM_UTURN_INT_LV_L5",
"B_TERM_UTURN_INT_SE6B0",
"B_TERM_UTURN_INT_SE2BEG1",
"B_TERM_UTURN_INT_SE6A3",
"B_TERM_UTURN_INT_SW6B1",
"B_TERM_UTURN_INT_SW6A3",
"B_TERM_UTURN_INT_SE2BEG0",
"B_TERM_UTURN_INT_SS6B1",
"B_TERM_UTURN_INT_SE6C2",
"B_TERM_UTURN_INT_SW6D2",
"B_TERM_UTURN_INT_SW2BEG1",
"B_TERM_UTURN_INT_SE6B2",
"B_TERM_UTURN_INT_SW6D1",
"B_TERM_UTURN_INT_SW6C0",
"B_TERM_UTURN_INT_ER1END_N3_3",
"B_TERM_UTURN_INT_SE6A2",
"B_TERM_UTURN_INT_LV_L4",
"B_TERM_UTURN_INT_SW2BEG3",
"B_TERM_UTURN_INT_SW6C2",
"B_TERM_UTURN_INT_SS6A3",
"B_TERM_UTURN_INT_SL1BEG0",
"B_TERM_UTURN_INT_SE6A1",
"B_TERM_UTURN_INT_LV4",
"B_TERM_UTURN_INT_SS2A2",
"B_TERM_UTURN_INT_SE6C1",
"B_TERM_UTURN_INT_SS2BEG1",
"B_TERM_UTURN_INT_LVB_L0",
"B_TERM_UTURN_INT_SS6A0",
"B_TERM_UTURN_INT_SE6D1",
"B_TERM_UTURN_INT_SE2BEG3",
"B_TERM_UTURN_INT_SL1BEG3",
"B_TERM_UTURN_INT_LV_L3",
"B_TERM_UTURN_INT_SW6B0",
"B_TERM_UTURN_INT_LV5",
"B_TERM_UTURN_INT_LVB4",
"B_TERM_UTURN_INT_WR1END0",
"B_TERM_UTURN_INT_LV_L6",
"B_TERM_UTURN_INT_LV_L18",
"B_TERM_UTURN_INT_SE2BEG2",
"B_TERM_UTURN_INT_SS2A3",
"B_TERM_UTURN_INT_SW6B3",
"B_TERM_UTURN_INT_SS6C1",
"B_TERM_UTURN_INT_WR1BEG0",
"B_TERM_UTURN_INT_SE6D0",
"B_TERM_UTURN_INT_SL1BEG2",
"B_TERM_UTURN_INT_FAN_BOUNCE0",
"B_TERM_UTURN_INT_SW6END_N0_3",
"B_TERM_UTURN_INT_SS6E1",
"B_TERM_UTURN_INT_SS6C2",
"B_TERM_UTURN_INT_SS6D3",
"B_TERM_UTURN_INT_LV6",
"B_TERM_UTURN_INT_SS2A1",
"B_TERM_UTURN_INT_SS6B0",
"B_TERM_UTURN_INT_LV18"
],
"pips": {}
}

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