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Unify naming and add RAM block parsing

This commit is contained in:
Miodrag Milanovic 2024-12-04 13:57:00 +01:00
parent 4e2d297d54
commit 004171eadb
3 changed files with 41 additions and 12 deletions
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2
libgm/include/ChipConfig.hpp
View File

@ -52,7 +52,7 @@ class ChipConfig
string chip_name; string chip_name;
string chip_package; string chip_package;
std::map<CfgLoc, TileConfig> tiles; std::map<CfgLoc, TileConfig> tiles;
std::map<CfgLoc, TileConfig> rams; std::map<CfgLoc, TileConfig> brams;
// Block RAM initialisation // Block RAM initialisation
std::map<CfgLoc, std::vector<uint8_t>> bram_data; std::map<CfgLoc, std::vector<uint8_t>> bram_data;

20
libgm/src/ChipConfig.cpp
View File

@ -38,10 +38,10 @@ std::string ChipConfig::to_string() const
ss << endl; ss << endl;
} }
} }
for (const auto &ram : rams) { for (const auto &bram : brams) {
if (!ram.second.empty()) { if (!bram.second.empty()) {
ss << ".ram " << ram.first.die << " " << ram.first.x << " " << ram.first.y << endl; ss << ".bram " << bram.first.die << " " << bram.first.x << " " << bram.first.y << endl;
ss << ram.second; ss << bram.second;
ss << endl; ss << endl;
} }
} }
@ -80,14 +80,14 @@ ChipConfig ChipConfig::from_string(const std::string &config)
TileConfig tc; TileConfig tc;
ss >> tc; ss >> tc;
cc.tiles.emplace(loc, tc); cc.tiles.emplace(loc, tc);
} else if (verb == ".ram") { } else if (verb == ".bram") {
CfgLoc loc; CfgLoc loc;
ss >> loc.die; ss >> loc.die;
ss >> loc.x; ss >> loc.x;
ss >> loc.y; ss >> loc.y;
TileConfig tc; TileConfig tc;
ss >> tc; ss >> tc;
cc.rams.emplace(loc, tc); cc.brams.emplace(loc, tc);
} else if (verb == ".bram_init") { } else if (verb == ".bram_init") {
CfgLoc loc; CfgLoc loc;
ss >> loc.die; ss >> loc.die;
@ -95,7 +95,7 @@ ChipConfig ChipConfig::from_string(const std::string &config)
ss >> loc.y; ss >> loc.y;
ios_base::fmtflags f(ss.flags()); ios_base::fmtflags f(ss.flags());
while (!skip_check_eor(ss)) { while (!skip_check_eor(ss)) {
uint8_t value; uint16_t value;
ss >> hex >> value; ss >> hex >> value;
cc.bram_data[loc].push_back(value); cc.bram_data[loc].push_back(value);
} }
@ -130,8 +130,8 @@ Chip ChipConfig::to_chip() const
loc.y = y; loc.y = y;
for (int x = 0; x < die.get_max_ram_col(); x++) { for (int x = 0; x < die.get_max_ram_col(); x++) {
loc.x = x; loc.x = x;
if (rams.count(loc)) { if (brams.count(loc)) {
const TileConfig &cfg = rams.at(loc); const TileConfig &cfg = brams.at(loc);
die.write_ram(x, y, ram_db.config_to_ram_data(cfg)); die.write_ram(x, y, ram_db.config_to_ram_data(cfg));
} }
if (bram_data.count(loc)) if (bram_data.count(loc))
@ -166,7 +166,7 @@ ChipConfig ChipConfig::from_chip(const Chip &chip)
for (int x = 0; x < die.get_max_ram_col(); x++) { for (int x = 0; x < die.get_max_ram_col(); x++) {
loc.x = x; loc.x = x;
if (!die.is_ram_empty(x, y)) { if (!die.is_ram_empty(x, y)) {
cc.rams.emplace(loc, ram_db.ram_data_to_config(die.get_ram_config(x, y))); cc.brams.emplace(loc, ram_db.ram_data_to_config(die.get_ram_config(x, y)));
if (!die.is_ram_data_empty(x, y)) { if (!die.is_ram_data_empty(x, y)) {
cc.bram_data.emplace(loc, die.get_ram_data(x, y)); cc.bram_data.emplace(loc, die.get_ram_data(x, y));
} }

31
libgm/src/TileBitDatabase.cpp
View File

@ -203,7 +203,36 @@ TileConfig TileBitDatabase::tile_data_to_config(const vector<uint8_t> &data)
return cfg; return cfg;
} }
RamBitDatabase::RamBitDatabase() : BaseBitDatabase() {} RamBitDatabase::RamBitDatabase() : BaseBitDatabase()
{
add_word_settings("RAM_cfg_forward_a_addr", 0 * 8, 8);
add_word_settings("RAM_cfg_forward_b_addr", 1 * 8, 8);
add_word_settings("RAM_cfg_forward_a0_clk", 2 * 8, 8);
add_word_settings("RAM_cfg_forward_a0_en", 3 * 8, 8);
add_word_settings("RAM_cfg_forward_a0_we", 4 * 8, 8);
add_word_settings("RAM_cfg_forward_a1_clk", 5 * 8, 8);
add_word_settings("RAM_cfg_forward_a1_en", 6 * 8, 8);
add_word_settings("RAM_cfg_forward_a1_we", 7 * 8, 8);
add_word_settings("RAM_cfg_forward_b0_clk", 8 * 8, 8);
add_word_settings("RAM_cfg_forward_b0_en", 9 * 8, 8);
add_word_settings("RAM_cfg_forward_b0_we", 10 * 8, 8);
add_word_settings("RAM_cfg_forward_b1_clk", 11 * 8, 8);
add_word_settings("RAM_cfg_forward_b1_en", 12 * 8, 8);
add_word_settings("RAM_cfg_forward_b1_we", 13 * 8, 8);
add_word_settings("RAM_cfg_sram_mode_i_cfg", 14 * 8, 8);
add_word_settings("RAM_cfg_in_out_cfg", 15 * 8, 8);
add_word_settings("RAM_cfg_out_cfg", 16 * 8, 8);
add_word_settings("RAM_cfg_out_b1_cfg", 17 * 8, 8);
add_word_settings("RAM_cfg_wrmode_outreg", 18 * 8, 8);
add_word_settings("RAM_cfg_inversion", 19 * 8, 8);
add_word_settings("RAM_cfg_inv_ecc_dyn", 20 * 8, 8);
add_word_settings("RAM_cfg_fifo_sync_empty", 21 * 8, 8);
add_word_settings("RAM_cfg_fifo_empty", 22 * 8, 8);
add_word_settings("RAM_cfg_fifo_aync_full", 23 * 8, 8);
add_word_settings("RAM_cfg_fifo_full", 24 * 8, 8);
add_word_settings("RAM_cfg_sram_delay", 25 * 8, 8);
add_word_settings("RAM_cfg_datbm_cascade", 26 * 8, 8);
}
std::vector<uint8_t> RamBitDatabase::config_to_ram_data(const TileConfig &cfg) std::vector<uint8_t> RamBitDatabase::config_to_ram_data(const TileConfig &cfg)
{ {