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Use stl types instead of arrays

This commit is contained in:
Miodrag Milanovic 2024-12-04 12:52:10 +01:00
parent 0666b68314
commit 4e2d297d54
6 changed files with 55 additions and 60 deletions
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15
libgm/include/Die.hpp
View File

@ -21,6 +21,7 @@
#define LIBGATEMATE_DIE_HPP
#include <cstdint>
#include <map>
#include <string>
#include <vector>
@ -47,8 +48,6 @@ class Die
int get_max_ram_row() const { return MAX_RAM_ROWS; }
int get_max_ram_col() const { return MAX_RAM_COLS; }
void clear();
bool is_latch_empty(int x, int y) const;
bool is_ram_empty(int x, int y) const;
bool is_ram_data_empty(int x, int y) const;
@ -57,14 +56,14 @@ class Die
void write_ram(int x, int y, const std::vector<uint8_t> &data);
void write_ram_data(int x, int y, const std::vector<uint8_t> &data, uint16_t addr);
const uint8_t *get_latch_config(int x, int y) const { return &latch[y * MAX_COLS + x][0]; }
const uint8_t *get_ram_config(int x, int y) const { return &ram[y * MAX_RAM_COLS + x][0]; }
const uint8_t *get_ram_data(int x, int y) const { return &ram_data[y * MAX_RAM_COLS + x][0]; }
const std::vector<uint8_t> get_latch_config(int x, int y) const { return latch.at(std::make_pair(x, y)); }
const std::vector<uint8_t> get_ram_config(int x, int y) const { return ram.at(std::make_pair(x, y)); }
const std::vector<uint8_t> get_ram_data(int x, int y) const { return ram_data.at(std::make_pair(x, y)); }
private:
uint8_t latch[MAX_ROWS * MAX_COLS][LATCH_BLOCK_SIZE]; // Config latches
uint8_t ram[MAX_RAM][RAM_BLOCK_SIZE]; // Config RAM
uint8_t ram_data[MAX_RAM][MEMORY_SIZE]; // RAM data content FRAM
std::map<std::pair<int, int>, std::vector<uint8_t>> latch; // Config latches
std::map<std::pair<int, int>, std::vector<uint8_t>> ram; // Config RAM
std::map<std::pair<int, int>, std::vector<uint8_t>> ram_data; // RAM data content FRAM
};
} // namespace GateMate

4
libgm/include/TileBitDatabase.hpp
View File

@ -56,7 +56,7 @@ class TileBitDatabase : BaseBitDatabase
{
public:
TileBitDatabase(const int x, const int y);
TileConfig tile_data_to_config(const uint8_t *data);
TileConfig tile_data_to_config(const vector<uint8_t> &data);
std::vector<uint8_t> config_to_tile_data(const TileConfig &cfg);
private:
@ -80,7 +80,7 @@ class RamBitDatabase : BaseBitDatabase
{
public:
RamBitDatabase();
TileConfig ram_data_to_config(const uint8_t *data);
TileConfig ram_data_to_config(const vector<uint8_t> &data);
std::vector<uint8_t> config_to_ram_data(const TileConfig &cfg);
};

24
libgm/src/Bitstream.cpp
View File

@ -167,6 +167,12 @@ class BitstreamReadWriter
write_byte(*(in++));
}
void write_bytes(std::vector<uint8_t> in)
{
for (auto val : in)
write_byte(val);
}
// Skip over bytes while updating CRC
void skip_bytes(size_t count)
{
@ -580,16 +586,14 @@ Bitstream Bitstream::serialise_chip(const Chip &chip)
if (iteration != 0 && is_edge_location(x, y))
continue;
wr.write_cmd_lxlys(x, y);
const uint8_t *ptr = die.get_latch_config(x, y);
int size = 112;
for (int i = 111; i > 0; i--)
if (ptr[i] == 0)
size--;
else
break;
wr.write_header(CMD_DLCU, size);
for (int i = 0; i < size; i++)
wr.write_byte(ptr[i]);
std::vector<uint8_t> data = die.get_latch_config(x, y);
if (iteration == 0 && !is_edge_location(x, y)) {
std::fill(data.begin(), data.begin() + 40, 0);
}
auto rit = std::find_if(data.rbegin(), data.rend(), [](uint8_t val) { return val != 0; });
data.erase(rit.base(), end(data));
wr.write_header(CMD_DLCU, data.size());
wr.write_bytes(data);
wr.insert_crc16();
}
}

6
libgm/src/ChipConfig.cpp
View File

@ -168,11 +168,7 @@ ChipConfig ChipConfig::from_chip(const Chip &chip)
if (!die.is_ram_empty(x, y)) {
cc.rams.emplace(loc, ram_db.ram_data_to_config(die.get_ram_config(x, y)));
if (!die.is_ram_data_empty(x, y)) {
std::vector<uint8_t> content(Die::MEMORY_SIZE, 0);
const uint8_t *ptr = die.get_ram_data(x, y);
for (int i = 0; i < Die::MEMORY_SIZE; i++)
content.push_back(ptr[i]);
cc.bram_data.emplace(loc, content);
cc.bram_data.emplace(loc, die.get_ram_data(x, y));
}
}
}

56
libgm/src/Die.cpp
View File

@ -22,58 +22,54 @@
namespace GateMate {
Die::Die() { clear(); }
void Die::clear()
Die::Die()
{
memset(latch, 0, sizeof(uint8_t) * MAX_ROWS * MAX_COLS * LATCH_BLOCK_SIZE);
memset(ram, 0, sizeof(uint8_t) * MAX_RAM * RAM_BLOCK_SIZE);
memset(ram_data, 0, sizeof(uint8_t) * MAX_RAM * MEMORY_SIZE);
for (int y = 0; y < MAX_ROWS; y++) {
for (int x = 0; x < MAX_COLS; x++) {
latch[std::make_pair(x, y)] = std::vector<u_int8_t>();
latch[std::make_pair(x, y)].reserve(LATCH_BLOCK_SIZE);
}
}
for (int y = 0; y < MAX_RAM_ROWS; y++) {
for (int x = 0; x < MAX_RAM_COLS; x++) {
ram[std::make_pair(x, y)] = std::vector<u_int8_t>();
ram[std::make_pair(x, y)].reserve(LATCH_BLOCK_SIZE);
ram_data[std::make_pair(x, y)] = std::vector<u_int8_t>();
}
}
}
bool Die::is_latch_empty(int x, int y) const
{
for (int i = 0; i < LATCH_BLOCK_SIZE; i++)
if (latch[y * MAX_COLS + x][i] != 0)
return false;
return true;
}
bool Die::is_latch_empty(int x, int y) const { return latch.at(std::make_pair(x, y)).empty(); }
bool Die::is_ram_empty(int x, int y) const
{
for (int i = 0; i < RAM_BLOCK_SIZE; i++)
if (ram[y * MAX_RAM_COLS + x][i] != 0)
return false;
return true;
}
bool Die::is_ram_empty(int x, int y) const { return ram.at(std::make_pair(x, y)).empty(); }
bool Die::is_ram_data_empty(int x, int y) const
{
for (int i = 0; i < MEMORY_SIZE; i++)
if (ram_data[y * MAX_RAM_COLS + x][i] != 0)
return false;
return true;
}
bool Die::is_ram_data_empty(int x, int y) const { return ram_data.at(std::make_pair(x, y)).empty(); }
void Die::write_latch(int x, int y, const std::vector<uint8_t> &data)
{
int pos = 0;
auto &block = latch.at(std::make_pair(x, y));
block.resize(LATCH_BLOCK_SIZE, 0x00);
for (auto d : data)
latch[y * MAX_COLS + x][pos++] = d;
block[pos++] = d;
}
void Die::write_ram(int x, int y, const std::vector<uint8_t> &data)
{
int pos = 0;
auto &block = ram.at(std::make_pair(x, y));
block.resize(RAM_BLOCK_SIZE, 0x00);
for (auto d : data)
ram[y * MAX_RAM_COLS + x][pos++] = d;
block[pos++] = d;
}
void Die::write_ram_data(int x, int y, const std::vector<uint8_t> &data, uint16_t addr)
{
int pos = addr;
auto &block = ram_data.at(std::make_pair(x, y));
block.resize(MEMORY_SIZE, 0x00);
for (auto d : data)
ram_data[y * MAX_RAM_COLS + x][pos++] = d;
block[pos++] = d;
}
} // namespace GateMate

10
libgm/src/TileBitDatabase.cpp
View File

@ -27,7 +27,7 @@
namespace GateMate {
std::vector<bool> data_bytes_to_array(const uint8_t *data, size_t count)
std::vector<bool> data_bytes_to_array(const vector<uint8_t> &data, size_t count)
{
std::vector<bool> result(count * 8);
for (size_t j = 0; j < count; j++) {
@ -190,10 +190,10 @@ std::vector<uint8_t> TileBitDatabase::config_to_tile_data(const TileConfig &cfg)
return bits_to_bytes(tile);
}
TileConfig TileBitDatabase::tile_data_to_config(const uint8_t *data)
TileConfig TileBitDatabase::tile_data_to_config(const vector<uint8_t> &data)
{
TileConfig cfg;
std::vector<bool> d = data_bytes_to_array(&data[0], Die::LATCH_BLOCK_SIZE);
std::vector<bool> d = data_bytes_to_array(data, Die::LATCH_BLOCK_SIZE);
for (auto &w : words) {
auto val = w.second.get_value(d);
if (is_array_empty(val))
@ -214,10 +214,10 @@ std::vector<uint8_t> RamBitDatabase::config_to_ram_data(const TileConfig &cfg)
return bits_to_bytes(tile);
}
TileConfig RamBitDatabase::ram_data_to_config(const uint8_t *data)
TileConfig RamBitDatabase::ram_data_to_config(const vector<uint8_t> &data)
{
TileConfig cfg;
std::vector<bool> d = data_bytes_to_array(&data[0], Die::RAM_BLOCK_SIZE);
std::vector<bool> d = data_bytes_to_array(data, Die::RAM_BLOCK_SIZE);
for (auto &w : words) {
auto val = w.second.get_value(d);
if (is_array_empty(val))