Patrick Urban dce9406599 gatemate: fix failed signal polarity and update documentation ...

* CFG_FAILED signal is no longer inverted
* minor fix in CFG_MD settings in doc/vendors/colognechip.rst
* update evaluation board URL

Signed-off-by: Patrick Urban <[email protected]>

2022-04-09 13:08:57 +02:00

..

compatibility

doc/cable: move to yml

2022-02-20 15:47:35 +01:00

guide

doc/guide: Add instructions for manual installation on macOS

2022-03-22 21:40:06 +01:00

vendors

gatemate: fix failed signal polarity and update documentation

2022-04-09 13:08:57 +02:00

boards.yml

gatemate: fix failed signal polarity and update documentation

2022-04-09 13:08:57 +02:00

cable.yml

Support for the Papilio One board

2022-03-25 21:44:05 +01:00

conf.py

doc/cable: move to yml

2022-02-20 15:47:35 +01:00

data.py

doc/cable: move to yml

2022-02-20 15:47:35 +01:00

FPGAs.yml

doc: Update with a couple new supported Xilinx parts

2022-03-29 11:34:39 +02:00

index.rst

colognechip integration: update documentation

2021-12-12 18:26:14 +01:00

Makefile

doc: add Sphinx site

2021-11-28 10:20:43 +01:00

requirements.txt

doc: declare board compatibility through a YAML file

2022-01-12 03:00:55 +01:00

todo.rst

doc: convert TODO from md to rst

2021-11-28 10:24:07 +01:00