Add board preset for the Alinx AXKU095 Kintex UltraScale dev board,
using the Digilent HS2 cable (FT232H). Tested JTAG detect and SRAM
programming with IDCODE 0x23844093.
BPI (parallel CFI NOR) flash support was added in #676 for
program_bpi/write, but Xilinx::dumpFlash() only handles the XC95/XCF
and SPI (PRIMARY_FLASH/SECONDARY_FLASH) paths. On boards where
_is_bpi_board is set, --dump-flash silently falls through to the SPI
FlashInterface, producing garbage instead of reading the BPI NOR.
This adds a BPI branch mirroring the existing write path: load the
BPI JTAG bridge if needed, detect the flash, read the requested
region into the target BPI flash's buffer, and write it out.
Tested on a Kintex-7 XC7K480T board with a Micron MT28GU512AAA1EGC
BPI NOR (digilent_hs2 cable): wrote random data to a scratch flash
region with --write-flash, read it back with the patched
--dump-flash, and confirmed the two are byte-identical.
* fix(spiOverJtag): package-specific FGG676 bitstream build for QMTech XC7A100T
- Makefile: add xc7a100tfgg676 target
- build.py: parse device+package form (e.g. xc7a100tfgg676), stop aliasing
a package-specific bitstream to other packages via symlink
- constr_xc7a_fgg676.xdc: set BITSTREAM.STARTUP.STARTUPCLK JtagClk (camelCase;
all-caps JTAGCLK is silently rejected and falls back to Cclk, leaving EOS=0
over JTAG), correct SPI pins to LVCMOS33 per QMTech schematic
- README.md: document package-specific bitstream build
- remove stale spiOverJtag_xc7a100tfgg676.bit.gz (rebuilt by above)
* spiOverJtag: reword FGG676 SPI-flash pin comment as package-level
These pins are fixed by the XC7A*T-FGG676 package, not by the QMTech board.
Reword the comment to reflect that any XC7A35T/50T/75T/100T/200T in the FGG676
package routes the SPI-flash signals to the same balls. Keep the QMTech
schematic only as the cross-check reference. No pin values changed.
Addresses trabucayre review on constr_xc7a_fgg676.xdc.
---------
Co-authored-by: gHashTag <admin@t27.ai>
ll_write() can request more than 1.5K of data, but recv() call will
return right away as soon as one packet is received. This causes large
transfers to break as not enough data is received.
Fixed by adding rx_exact flag and enabled it for ll_write()
Tested with Zynq7010 on a slow WiFi. Before the patch all uploads were
silently failing with no error in the log.
Signed-off-by: Vadzim Dambrouski <pftbest@gmail.com>
The IS25WP256 (0x9d7019, 1.8V variant of the IS25LP256) was missing
from the database, and neither 256Mb part had its Quad Enable bit
described (status register bit 6 per the IS25LP(WP)256D datasheet),
making --enable-quad fail on these parts. Required to boot Xilinx
bitstreams generated with SPI_BUSWIDTH 4.
* OpenBSD-Patch: Added the #include <sys/socket.h> in xvc_server.cpp to allow for compilation. Added a section to the README.md.
* Moved the Note regarding OpenBSD from the README.md into the doc/guide/troubleshooting.rst.
* reverted the README.md back to its original form.
* Removed a copy&paste error in the main.cpp file. Updated the documentation on OpenBSD.
* slight change to reflect the nomenclature of modules/devices in OpenBSD.
* "Windows" is spelled with only one "o".
Do not apply the Zynq non-volatile memory restriction when only reading FPGA DNA. Allow Zynq devices to use the existing 7-series DNA read path.
Tested on xc7z010 over XVC with --read-dna.
Shorden
Gwenhael Goavec-Merou
gojimmypi
MiO
Dave Keeshan
aisuneko icecat
Craig Haywood
haomjc
Nicholas Dietz
Matt Thompson
Mario Reisinger
Vasilev Dmitrii
Vadzim Dambrouski
Martin C
gHashTag
Florent Kermarrec
Gonzalo Avila Alterach
dettus
MYJ695
Hannes Rüger