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openFPGALoader
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367 Commits

Author SHA1 Message Date
Vegard Storheil Eriksen 36783d74c4 progressBar: Use only stdout. 
The progress markers of the progress bar were output to stderr while the
rest was output to stdout. Move everything to stdout.
 2021-09-20 15:14:23 +02:00
Gwenhael Goavec-Merou 3698b98976 ftdiJtagMPSSE: improve a bit USB transaction 2021-09-18 14:54:40 +02:00
Gwenhael Goavec-Merou 57c0f16be4 ftdipp_mpsse: typo in setClkFreq 2021-09-16 07:41:05 +02:00
Gwenhael Goavec-Merou 85b53b5918 add gowin external spi in bscan and --external-flash option 2021-09-15 20:18:49 +02:00
Gwenhael Goavec-Merou ae2fcfdca1 main: args. Fix comments for load and write bitstream 2021-09-13 14:10:42 +02:00
Fabien Marteau b70bd83ced
Merge branch 'trabucayre:master' into master 2021-09-03 08:52:18 +02:00
Gwenhael Goavec-Merou 2ef040774e fsparser: gw1nsr-4c idcode/nb_line 2021-09-03 07:47:58 +02:00
Fabien Marteau 23cf631b85 fix part name GW1NSR-4 -> GW1NSR-4C 2021-09-02 14:56:22 +02:00
Fabien Marteau 11bdebd884 adding reference to Tang Nano 4K kit in doc 2021-09-02 13:54:34 +02:00
Fabien Marteau 94385a758e adding IDCODE for GW1NSR, for Tang Nano 4K kit 2021-09-02 13:46:35 +02:00
Gwenhael Goavec-Merou bb69297ed0 xilinx: with XCF reconfigure FPGA after write 2021-08-30 17:15:45 +02:00
Gwenhael Goavec-Merou 2606bf7017 xilinx/doc: add spartan3 and XCF flash 2021-08-30 15:08:11 +02:00
Gwenhael Goavec-Merou 92a4b9bcd8 jtag: fix idcode mask and display 2021-08-28 16:31:24 +02:00
Gwenhael Goavec-Merou 304ec0071c mask idcode upper nibble (version in IEEE 1149.1) 2021-08-27 15:10:12 +02:00
Gwenhael Goavec-Merou faedb0cfd7 lattice: throw exception when program fails 2021-08-23 16:27:28 +02:00
Gwenhael Goavec-Merou 74b8305730 xilinx: test parse return for jedec instead of catch exception 2021-08-20 09:54:43 +02:00
Gwenhael Goavec-Merou db5d4e75d9 jedParser: fix checksum for xc9500 2021-08-20 09:44:38 +02:00
Gwenhael Goavec-Merou 521c703842 part: add xc95 family idcode 2021-08-18 15:41:39 +02:00
Gwenhael Goavec-Merou b61884614e xilinx: add support for XC95 CPLD family 2021-08-18 15:38:49 +02:00
Gwenhael Goavec-Merou 471fbb6a81 jedParser: add xilinx compatibility 2021-08-18 15:38:24 +02:00
Gwenhael Goavec-Merou 274d4ea2dc main: fix display order for detect 2021-08-18 07:40:25 +02:00
Gwenhael Goavec-Merou c47b494311 jtag: add access to targeted idcode 2021-08-18 07:39:23 +02:00
Gwenhael Goavec-Merou 630d4428c6 main: DFU mode: pass board vid/pid 2021-07-17 08:36:32 +02:00
Gwenhael Goavec-Merou cbe2bf5494 dfu: try to open dfu vid/pid, next board vid/pid. without vid/pid download is forbidden. Simplify detection in not enumerate mode. Display iProduct 2021-07-17 08:36:13 +02:00
Gwenhael Goavec-Merou b8e2939776 board: add vid/pid for DFU at board level 2021-07-17 08:34:44 +02:00
Gwenhael Goavec-Merou 7113f4b36b part: add Gowin GW1N-2 2021-07-16 07:42:34 +02:00
Gwenhael Goavec-Merou 651fdd8beb ftdixx: improve workaround for arty. Not required with a classic ft2232 2021-07-14 19:09:39 +02:00
Gwenhael Goavec-Merou cd64bce4f2 fix warning in Debug mode 2021-07-14 17:59:02 +02:00
Gwenhael Goavec-Merou be6ed217dd main: display error message if program fails 2021-07-14 16:39:14 +02:00
Gwenhael Goavec-Merou 1e0a06288d configBitstreamParser: don't compute reverseByte, use a precomputed table: gain: 200ms for arty @30MHz 2021-07-14 08:44:22 +02:00
Gwenhael Goavec-Merou cc688d6db6 main: small fix 2021-07-14 08:07:51 +02:00
Gwenhael Goavec-Merou 894cda820f board: add default frequency option for BITBANG and SPI boards 2021-07-14 08:05:36 +02:00
Gwenhael Goavec-Merou 13af012163 main: avoid potential miss with probe clock frequency 2021-07-14 08:04:43 +02:00
Gwenhael Goavec-Merou fd329158de
Merge pull request #98 from ultraembedded/master 
Add board specific default frequency
 2021-07-14 07:53:13 +02:00
Gwenhael Goavec-Merou acf7d2a0a8 ftdiJtagMPSSE: add work around to deal with freq >= 15MHz 2021-07-13 07:00:30 +02:00
Gwenhael Goavec-Merou 594f065116 ftdipp_mpsse: use runtime_error instead of simple exception 2021-07-12 08:05:25 +02:00
ultraembedded f8831f329c Only use board clock speed if user does not specify an alternate freq 2021-07-11 15:27:46 +01:00
ultraembedded 797785ce93 Allow board configuration table to contain a default clock speed (as some boards are known to work at higher speeds safely). Move Digilent Arty to 10MHz (tested). 2021-07-11 15:20:15 +01:00
Gwenhael Goavec-Merou 3983726a66 all devices: use spiFlash dump & verify 2021-07-11 11:34:14 +02:00
Gwenhael Goavec-Merou f5254294eb altera: add verify and dump 2021-07-11 11:32:35 +02:00
Gwenhael Goavec-Merou b77c5a22df spiFlash: add verify and dump method 2021-07-11 11:32:10 +02:00
Gwenhael Goavec-Merou f19d0996a4 progressBar: limit resolution 2021-07-11 11:30:02 +02:00
Gwenhael Goavec-Merou 6639f0646a board: pipistrello: add spi flash support 2021-07-11 08:58:40 +02:00
Gwenhael Goavec-Merou c90a4b7734 altera: spi flash support for cycloneV and qmtech 2021-07-10 08:20:27 +02:00
Gwenhael Goavec-Merou 0c4aedcb23 altera: add spi flash support for de0nano (EP4CE22F17C6) 2021-07-09 07:40:55 +02:00
Gwenhael Goavec-Merou c99f5aa4e6 main: update to pass device type and prog type to altera class 2021-07-08 20:54:12 +02:00
Gwenhael Goavec-Merou 84bd19b19a board: cyc1000: add fpga model 2021-07-08 20:53:20 +02:00
Gwenhael Goavec-Merou c29fbb15f9 altera: use new epcq interface, add device type and prog type. Now more generic and not specific to cyc1000 2021-07-08 20:52:46 +02:00
Gwenhael Goavec-Merou 0d4b6143b5 epcq,spiFlash: epcq is now a subclass of spiFlash (real different part is power_(up|down) and read_id 2021-07-08 20:51:51 +02:00
Billy Stevens f937cb9ab5
Adds support for the xc6slx100fgg484. 
Tested on a Pano Logic G2.
 2021-07-03 05:01:56 -04:00