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openFPGALoader
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mask idcode upper nibble (version in IEEE 1149.1)

This commit is contained in:
Gwenhael Goavec-Merou 2021-08-27 15:10:12 +02:00
parent faedb0cfd7
commit 304ec0071c
5 changed files with 52 additions and 46 deletions
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4
src/gowin.cpp
View File

@ -63,7 +63,7 @@ Gowin::Gowin(Jtag *jtag, const string filename, const string &file_type,
verify, verbose), is_gw1n1(false)
{
_fs = NULL;
uint32_t idcode = idCode();
uint32_t idcode = _jtag->get_target_device_id();;
if (!_file_extension.empty()) {
if (_file_extension == "fs") {
@ -90,7 +90,7 @@ Gowin::Gowin(Jtag *jtag, const string filename, const string &file_type,
_fs->displayHeader();
string idcode_str = _fs->getHeaderVal("idcode");
uint32_t fs_idcode = std::stoul(idcode_str.c_str(), NULL, 16);
if (fs_idcode != idcode) {
if ((fs_idcode & 0x0fffffff) != idcode) {
throw std::runtime_error("mismatch between target's idcode and fs idcode");
}
} else {

2
src/jtag.cpp
View File

@ -132,7 +132,7 @@ int Jtag::detectChain(int max_dev)
for (int ii=0; ii < 4; ii++)
tmp |= (rx_buff[ii] << (8*ii));
if (tmp != 0 && tmp != 0xffffffff) {
_devices_list.insert(_devices_list.begin(), tmp);
_devices_list.insert(_devices_list.begin(), 0x0fffffff & tmp);
/* search for irlength in fpga_list or misc_dev_list */
uint16_t irlength = -1;

2
src/lattice.cpp
View File

@ -76,7 +76,7 @@ Lattice::Lattice(Jtag *jtag, const string filename, const string &file_type,
}
}
/* check device family */
uint32_t idcode = idCode();
uint32_t idcode = _jtag->get_target_device_id();
string family = fpga_list[idcode].family;
if (family == "MachXO2")
_fpga_family = MACHXO2_FAMILY;

76
src/part.hpp
View File

@ -16,32 +16,33 @@ typedef struct {
int irlength;
} fpga_model;
/* Highest nibble (version) must always be set to 0 */
static std::map <int, fpga_model> fpga_list = {
{0x0a014c35, {"anlogic", "eagle s20", "EG4S20BG256", 8}},
{0x0362D093, {"xilinx", "artix a7 35t", "xc7a35", 6}},
{0x0362c093, {"xilinx", "artix a7 50t", "xc7a50t", 6}},
{0x13632093, {"xilinx", "artix a7 75t", "xc7a75t", 6}},
{0x13631093, {"xilinx", "artix a7 100t", "xc7a100", 6}},
{0x13636093, {"xilinx", "artix a7 200t", "xc7a200", 6}},
{0x03632093, {"xilinx", "artix a7 75t", "xc7a75t", 6}},
{0x03631093, {"xilinx", "artix a7 100t", "xc7a100", 6}},
{0x03636093, {"xilinx", "artix a7 200t", "xc7a200", 6}},
{0x43651093, {"xilinx", "kintex7", "xc7k325t", 6}},
{0x03651093, {"xilinx", "kintex7", "xc7k325t", 6}},
{0x24001093, {"xilinx", "spartan6", "xc6slx9", 6}},
{0x24002093, {"xilinx", "spartan6", "xc6slx16", 6}},
{0x24004093, {"xilinx", "spartan6", "xc6slx25", 6}},
{0x24011093, {"xilinx", "spartan6", "xc6slx100", 6}},
{0x44008093, {"xilinx", "spartan6", "xc6slx45", 6}},
{0x04001093, {"xilinx", "spartan6", "xc6slx9", 6}},
{0x04002093, {"xilinx", "spartan6", "xc6slx16", 6}},
{0x04004093, {"xilinx", "spartan6", "xc6slx25", 6}},
{0x04011093, {"xilinx", "spartan6", "xc6slx100", 6}},
{0x04008093, {"xilinx", "spartan6", "xc6slx45", 6}},
{0x03620093, {"xilinx", "spartan7", "xc7s15ftgb196-1", 6}},
{0x037c4093, {"xilinx", "spartan7", "xc7s25", 6}},
{0x0362f093, {"xilinx", "spartan7", "xc7s50", 6}},
{0x59602093, {"xilinx", "xc9500xl", "xc9536xl", 8}},
{0x59604093, {"xilinx", "xc9500xl", "xc9572xl", 8}},
{0x59608093, {"xilinx", "xc9500xl", "xc95144xl", 8}},
{0x59616093, {"xilinx", "xc9500xl", "xc95188xl", 8}},
{0x09602093, {"xilinx", "xc9500xl", "xc9536xl", 8}},
{0x09604093, {"xilinx", "xc9500xl", "xc9572xl", 8}},
{0x09608093, {"xilinx", "xc9500xl", "xc95144xl", 8}},
{0x09616093, {"xilinx", "xc9500xl", "xc95188xl", 8}},
{0x23727093, {"xilinx", "zynq", "xc7z020", 6}},
{0x03727093, {"xilinx", "zynq", "xc7z020", 6}},
{0x020f20dd, {"altera", "cyclone III", "EP3C16", 10}},
@ -53,44 +54,43 @@ static std::map <int, fpga_model> fpga_list = {
{0x02d010dd, {"altera", "cyclone V Soc", "5CSEMA4", 10}},
{0x010F0043, {"lattice", "CrosslinkNX", "LIFCL-17", 8}},
{0x010F1043, {"lattice", "CrosslinkNX", "LIFCL-40-ES", 8}},
{0x110F1043, {"lattice", "CrosslinkNX", "LIFCL-40", 8}},
{0x010F1043, {"lattice", "CrosslinkNX", "LIFCL-40", 8}},
{0x310F0043, {"lattice", "CertusNX", "LFD2NX-17", 8}},
{0x310F1043, {"lattice", "CertusNX", "LFD2NX-40", 8}},
{0x010F0043, {"lattice", "CertusNX", "LFD2NX-17", 8}},
{0x010F1043, {"lattice", "CertusNX", "LFD2NX-40", 8}},
{0x012b9043, {"lattice", "MachXO2", "LCMXO2-640HC", 8}},
{0x012ba043, {"lattice", "MachXO2", "LCMXO2-1200HC", 8}},
{0x012bd043, {"lattice", "MachXO2", "LCMXO2-7000HC", 8}},
{0x012b5043, {"lattice", "MachXO2", "LCMXO2-7000HE", 8}},
{0xE12BB043, {"lattice", "MachXO3LF", "LCMX03LF-1300C", 8}},
{0x612B2043, {"lattice", "MachXO3LF", "LCMX03LF-1300E", 8}},
{0x612BB043, {"lattice", "MachXO3LF", "LCMX03LF-2100C", 8}},
{0x612B3043, {"lattice", "MachXO3LF", "LCMX03LF-2100E", 8}},
{0x612BC043, {"lattice", "MachXO3LF", "LCMX03LF-4300C", 8}},
{0x612B4043, {"lattice", "MachXO3LF", "LCMX03LF-4300E", 8}},
{0x612BD043, {"lattice", "MachXO3LF", "LCMX03LF-6900C", 8}},
{0x612B5043, {"lattice", "MachXO3LF", "LCMX03LF-6900E", 8}},
{0x612BE043, {"lattice", "MachXO3LF", "LCMX03LF-9400C", 8}},
{0x612B6043, {"lattice", "MachXO3LF", "LCMX03LF-9400E", 8}},
{0x012BB043, {"lattice", "MachXO3LF", "LCMX03LF-1300C", 8}},
{0x012B2043, {"lattice", "MachXO3LF", "LCMX03LF-1300E", 8}},
{0x012BB043, {"lattice", "MachXO3LF", "LCMX03LF-2100C", 8}},
{0x012B3043, {"lattice", "MachXO3LF", "LCMX03LF-2100E", 8}},
{0x012BC043, {"lattice", "MachXO3LF", "LCMX03LF-4300C", 8}},
{0x012B4043, {"lattice", "MachXO3LF", "LCMX03LF-4300E", 8}},
{0x012BD043, {"lattice", "MachXO3LF", "LCMX03LF-6900C", 8}},
{0x012B5043, {"lattice", "MachXO3LF", "LCMX03LF-6900E", 8}},
{0x012BE043, {"lattice", "MachXO3LF", "LCMX03LF-9400C", 8}},
{0x012B6043, {"lattice", "MachXO3LF", "LCMX03LF-9400E", 8}},
{0x212e3043, {"lattice", "MachXO3D", "LCMX03D-9400HC", 8}},
{0x012e3043, {"lattice", "MachXO3D", "LCMX03D-9400HC", 8}},
{0x21111043, {"lattice", "ECP5", "LFE5U-12", 8}},
{0x41111043, {"lattice", "ECP5", "LFE5U-25", 8}},
{0x41112043, {"lattice", "ECP5", "LFE5U-45", 8}},
{0x41113043, {"lattice", "ECP5", "LFE5U-85", 8}},
{0x01111043, {"lattice", "ECP5", "LFE5U-12", 8}},
{0x01111043, {"lattice", "ECP5", "LFE5U-25", 8}},
{0x01112043, {"lattice", "ECP5", "LFE5U-45", 8}},
{0x01113043, {"lattice", "ECP5", "LFE5U-85", 8}},
{0x01111043, {"lattice", "ECP5", "LFE5UM-25", 8}},
{0x01112043, {"lattice", "ECP5", "LFE5UM-45", 8}},
{0x01113043, {"lattice", "ECP5", "LFE5UM-85", 8}},
{0x81111043, {"lattice", "ECP5", "LFE5UM5G-25", 8}},
{0x81112043, {"lattice", "ECP5", "LFE5UM5G-45", 8}},
{0x81113043, {"lattice", "ECP5", "LFE5UM5G-85", 8}},
{0x01111043, {"lattice", "ECP5", "LFE5UM5G-25", 8}},
{0x01112043, {"lattice", "ECP5", "LFE5UM5G-45", 8}},
{0x01113043, {"lattice", "ECP5", "LFE5UM5G-85", 8}},
{0x0129a043, {"lattice", "XP2", "LFXP2-8E", 8}},
{0x1100581b, {"Gowin", "GW1N", "GW1NR-9", 8}},
{0x0100581b, {"Gowin", "GW1N", "GW1NR-9", 8}},
{0x0900281B, {"Gowin", "GW1N", "GW1N-1", 8}},
{0x0120681b, {"Gowin", "GW1N", "GW1N-2", 8}},
{0x0100381B, {"Gowin", "GW1N", "GW1N-4", 8}},
@ -104,7 +104,7 @@ typedef struct {
} misc_device;
static std::map <int, misc_device> misc_dev_list = {
{0x4ba00477, {"ARM cortex A9", 4}},
{0x0ba00477, {"ARM cortex A9", 4}},
};
#endif

14
src/xilinx.cpp
View File

@ -61,14 +61,20 @@ Xilinx::Xilinx(Jtag *jtag, const std::string &filename,
_fpga_family = SPARTAN6_FAMILY;
} else if (family == "xc9500xl") {
_fpga_family = XC95_FAMILY;
if (idcode == 0x59602093)
switch (idcode) {
case 0x09602093:
_xc95_line_len = 2;
else if (idcode == 0x59604093)
break;
case 0x09604093:
_xc95_line_len = 4;
else if (idcode == 0x59608093)
break;
case 0x09608093:
_xc95_line_len = 8;
else if (idcode == 0x59616093)
break;
case 0x09616093:
_xc95_line_len = 16;
break;
}
} else {
_fpga_family = UNKNOWN_FAMILY;
}