dba873af6e
spiOverJtag: add bitstream for EP4CE115F23
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Built with Quartus Prime Lite 18.1.1.
Signed-off-by: Icenowy Zheng <uwu@icenowy.me>
2022-06-16 08:58:49 +08:00
1c7a9a7ffe
spiOverJtag: support xc7k160tffg676
2022-05-14 14:30:01 +07:00
4c0f683f9f
spiOverJtag: support xc7k420tffg901
2022-05-14 09:53:56 +07:00
dd85b5a579
spiOverJtag: xc7a100tfgg676 variant
2022-05-10 19:09:21 +02:00
3a3fe9a3cb
spiOverJtag: add cycloneV 5CEBA9F27 variant
2022-05-05 07:03:06 +02:00
a12793ed70
Added spiOverJtag for Spartan3E (xc3s500evq100)
2022-03-25 21:29:00 +01:00
2ed5eb5eec
Rename 5cefa5f23 to 5ce523, add documentation for board and fpga
2022-03-13 09:14:52 -04:00
7b36bdc893
Add qmtechCycloneV_5cefa5f23 board and spiOverJtag/spiOverJtag_5cefa5f23.rbf.gz bitstream to write flash
2022-03-12 09:25:22 -05:00
03769be937
spiOverJtag: Xilinx Spartan6 LX150T
2022-03-03 15:36:11 +01:00
255d90b750
add spiOverJtag build process for Kintex7 ffg900-2 packages, amend and extend build process for ff676-1 package
2022-02-22 13:01:02 -04:00
11a85eb19d
added spi flash support for xc6slx16csg324
2022-01-27 08:19:55 +00:00
6597dcf374
spiOverJtag: add bitstream for spartan6 LX16 FTG256
2022-01-15 11:47:15 +01:00
3674406227
spiOverJtag: xc7a100tcsg324
2021-12-21 07:02:14 +01:00
70ed45fdef
spiOverJtag: gzip xilinx bitstream
2021-12-19 17:33:39 +01:00
ea4b8d8a6d
spiOverJtag: add xc7s25csga324
2021-12-19 17:30:06 +01:00
7ceaab0126
spiOverJtag: add bitstream for ECP4CE15F23
2021-11-28 16:51:42 +01:00
c6b02b4358
spiOverJtag: add 5CEBA4F23C8, fix sdc file and compress rbf file
2021-11-28 10:00:21 +01:00
0d57b58c26
spiOverJtag: use build.py for all devices, add xc6slx45
2021-07-11 08:57:46 +02:00
a4ccdae7df
add basys3 support
2021-04-20 21:28:14 +02:00
7039465353
rework xilinx fpga spiOverJtag to respect model/package
2021-04-19 21:17:08 +02:00
922d3b0b56
xilinx: add xca50t support
2020-12-08 07:32:30 +01:00
edad461d88
add support for artix-7 200t and nexys video board
2020-10-15 16:07:55 +02:00
20d72de3c4
spiOverJtag: add xc7a100 bitstream
2020-09-22 15:02:42 +02:00
ced3363ee5
Support Arty S7-50
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Added Xilinx xc7s50 device to part.hpp; added support for generating
spiOverJtag bitstream file for that device and added bitstream to repo.
Converted xdc file from DOC line endings to native line endings.
2020-08-08 11:42:38 +02:00
5acae16a82
add design and bitstream to access SPI through JTAG
2019-10-05 19:03:28 +02:00
Icenowy Zheng
Hans Baier
Gwenhael Goavec-Merou
Stephan Ruloff
Stéphane Chevigny
unbtorsten
Dave Berkeley
Giuseppe Gebbia
Staf Verhaegen